Samuel Pitoiset [Fri, 26 Jun 2020 07:23:40 +0000 (09:23 +0200)]
radv: remove the shader ballot workaround for Youngblood with LLVM
Now that ACO is default, this is now pointless.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5658>
Erik Faye-Lund [Wed, 17 Jun 2020 10:45:21 +0000 (12:45 +0200)]
docs: update favicon
I created a new and cleaner favicon for mesa3d.org, and it seems like a
good idea to use that one for the docs as well.
While we're at it, replace the original PNG with the original SVG asset
the ICO-file was generated from.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5643>
Jonathan Marek [Thu, 25 Jun 2020 14:55:48 +0000 (10:55 -0400)]
turnip: fix huge scissor min/max case
Now that tu_cs_emit_regs is used for the scissor, it hits an assert when
the scissor is too large. Fixes this dEQP test:
dEQP-VK.draw.scissor.static_scissor_max_int32
Fixes:
9c0ae5704d654108fd36b ("turnip: fix empty scissor case")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5655>
Jonathan Marek [Fri, 26 Jun 2020 03:32:20 +0000 (23:32 -0400)]
turnip: fix VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
My attempt to be clever here backfired, it overwrites the pNext and stops
the loop (causing deqp to fail to query extension features after that).
Fixes:
62de79ac4492ac9e ("turnip: implement VK_KHR_shader_draw_parameters")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5654>
Icecream95 [Sun, 21 Jun 2020 06:22:21 +0000 (18:22 +1200)]
panfrost: Add PAN_MESA_DEBUG=gl3 flag
This flag allows forcing GL 3.3 without having to use
MESA_GL_VERSION_OVERRIDE etc.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5584>
Connor Abbott [Thu, 25 Jun 2020 10:32:24 +0000 (12:32 +0200)]
freedreno/a6xx: use firstIndex field
Analogous to the turnip change.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
Connor Abbott [Thu, 25 Jun 2020 10:23:49 +0000 (12:23 +0200)]
tu: Pass firstIndex directly to CP_DRAW_INDX_OFFSET
Saves some minor overhead, cleans things up a bit, and removes one more
unknown. We now program the internal registers in the same way between
direct/indirect draws.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
Connor Abbott [Thu, 25 Jun 2020 10:17:31 +0000 (12:17 +0200)]
freedreno/registers: Label firstIndex field in CP_DRAW_INDX_OFFSET
Based on comparing the implementations of CP_DRAW_INDX_OFFSET and
CP_DRAW_INDIRECT, this is what this field is for.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
Connor Abbott [Thu, 25 Jun 2020 13:35:28 +0000 (15:35 +0200)]
freedreno: On a5xx+ INDX_SIZE is MAX_INDICES
This was already done correctly for the indirect variants, and turnip
was setting the correct value, but it seems freedreno missed the change
in the non-indirect variant. Also, fix a misspelling of "indices" and
add a type to INDX_SIZE.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
Connor Abbott [Tue, 23 Jun 2020 12:12:09 +0000 (14:12 +0200)]
freedreno: Share constlen between different stages properly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Connor Abbott [Tue, 23 Jun 2020 11:19:07 +0000 (13:19 +0200)]
freedreno: Refactor ir3_cache shader compilation
Use an array, which makes it more like turnip and makes implementing the
const limits easier.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Connor Abbott [Wed, 24 Jun 2020 10:56:09 +0000 (12:56 +0200)]
tu: Share constlen between different stages properly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Connor Abbott [Wed, 24 Jun 2020 10:55:23 +0000 (12:55 +0200)]
ir3: Add ir3_trim_constlen()
This provides the policy for how to handle reducing constlen for some
stages.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Connor Abbott [Wed, 24 Jun 2020 10:03:59 +0000 (12:03 +0200)]
ir3: Support variants with different constlen's
This provides the mechanism for compiling variants with a reduced
constlen. The next patch provides the policy for choosing which to
reduce.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Connor Abbott [Wed, 24 Jun 2020 10:02:56 +0000 (12:02 +0200)]
ir3: Include ir3_compiler from ir3_shader
I wanted to access the ir3_compiler from a small helper inside
ir3_shader.h, which currently isn't possible.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Connor Abbott [Tue, 23 Jun 2020 15:09:10 +0000 (17:09 +0200)]
ir3, freedreno: Round up constlen earlier
Prevents problems when calculating whether we overflow the shared limit.
Note that on a6xx, the macros handle the assert for us.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
Iago Toral Quiroga [Thu, 25 Jun 2020 09:54:04 +0000 (11:54 +0200)]
v3d/compiler: don't rewrite unused temporaries to point to NOP register
This was assuming that unused temporaries are written but never read,
since the NOP register can only be used as a destination register,
but we can end up here also for temporaries that are read once but
never written.
This was found with a graphicsfuzz test that has a switch with
cases that have unreachable discards. In that test, NIR genrates
code like this:
decl_reg vec3 32 r19
...
r20 = mov r19.z
r21 = mov r19.y
r22 = mov r19.x
Where r19.xyz would generate 3 temporary registers that are read but
never written, so we would rewrite them to point to the NOP register
as QPU instruction sources, which is not allowed and would hit an
assert that expect magic reads to be from [r0,r5] only.
Fixes:
dEQP-VK.graphicsfuzz.unreachable-switch-case-with-discards
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5645>
Neil Roberts [Tue, 23 Jun 2020 22:16:43 +0000 (00:16 +0200)]
v3d: Use stvpmd for non-uniform offsets in GS
The offset for the VPM write for storing outputs from the geometry
shader isn’t necessarily uniform across all the lanes. This can happen
if some of the lanes don’t emit some of the vertices. In that case the
offset for the subsequent vertices will be different in each lane. In
that case we need to use the stvpmd instruction instead of stvpmv
because it will scatter the values out.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3150
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>
Neil Roberts [Tue, 23 Jun 2020 22:15:12 +0000 (00:15 +0200)]
v3d: Add missing macro for stvpmd instruction
stvpmd is like stvpmv but it scatters the output. It can be used with
non-dynamically uniform offsets.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>
Marek Olšák [Sat, 20 Jun 2020 03:00:15 +0000 (23:00 -0400)]
radeonsi: remove tabs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Sat, 20 Jun 2020 01:40:18 +0000 (21:40 -0400)]
radeonsi: clear per-context buffers at the end of si_create_context
We don't want any packets before CONTEXT_CONTROL.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Tue, 16 Jun 2020 02:39:00 +0000 (22:39 -0400)]
radeonsi: make si_pm4_cmd_begin/end static and simplify all usages
There is no longer the confusing trailing si_pm4_cmd_end call.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Tue, 16 Jun 2020 02:21:50 +0000 (22:21 -0400)]
radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state
The si_shader pointer is already there, so use it and remove the array
of BOs.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Sat, 20 Jun 2020 00:54:58 +0000 (20:54 -0400)]
radeonsi: make wait_mem_scratch unmappable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Tue, 16 Jun 2020 17:56:10 +0000 (13:56 -0400)]
radeonsi: don't add the tess ring buffers into the cs_preamble state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Mon, 15 Jun 2020 21:00:09 +0000 (17:00 -0400)]
radeonsi: rename init_config states to cs_preamble states
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Sat, 23 May 2020 11:13:27 +0000 (07:13 -0400)]
radeonsi: don't add the border color buffer into the init_config state
We might have to replace init_config for preemption.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Sat, 20 Jun 2020 04:24:23 +0000 (00:24 -0400)]
ac,winsys/amdgpu: align IBs the same as the kernel
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Marek Olšák [Thu, 18 Jun 2020 05:04:51 +0000 (01:04 -0400)]
amd: add proper definitions for NOP packets
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
Samuel Pitoiset [Thu, 25 Jun 2020 09:21:12 +0000 (11:21 +0200)]
gitlab-ci: attach the Fossilize log file as artifact on failure
It might be help.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>
Samuel Pitoiset [Wed, 24 Jun 2020 12:07:39 +0000 (14:07 +0200)]
gitlab-ci: append Fossilize stdout/stderr to a file to reduce spam
Fossilize is really verbose and it's easy to reach the buffer
limit in GitLab CI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>
Samuel Pitoiset [Wed, 24 Jun 2020 10:16:31 +0000 (12:16 +0200)]
gitlab-ci: set the number of Fossilize threads to 4
The shared runners are set up for concurrent jobs ~= CPUs / 4 (x86)
or 8 (ARM).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>
Icecream95 [Thu, 25 Jun 2020 07:51:37 +0000 (19:51 +1200)]
panfrost: Only copy resources when they are in a pending batch
Fixes a performance regression in alacritty, and rendering is still
fine in GLQuake ports.
Fixes:
361fb38662f ("panfrost: Copy resources when mapping to avoid waiting for readers")
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5642>
Rafael Antognolli [Wed, 24 Jun 2020 18:57:51 +0000 (18:57 +0000)]
anv: Align "used" attribute to 64 bits.
This is a 64 bits value that might not be aligned on 32 bit plaforms.
Since it's used with atomics, let's make sure it gets properly aligned
to avoid any potential performance loss.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
Rafael Antognolli [Wed, 24 Jun 2020 18:52:55 +0000 (18:52 +0000)]
iris: Align last_seqnos to 64 bits.
last_seqnos is used in atomic operations. Specially on 32 bit platorms,
it tends to be slower if it's not aligned to 64 bits (see
cdc331c6f9f6b2ffc035018de4445dba9b67c1f7). This fixes a small regression
on Bioshock.
Fixes:
aba3aed96e4 ("iris: fix export of GEM handles")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
Eric Anholt [Thu, 25 Jun 2020 20:48:26 +0000 (13:48 -0700)]
ci: Remove a stray "always" on the freedreno traces job.
This was making it so that the CI would error if the set of files modified
or the pipeline involvd meant the jobs we depend on weren't enabled. It
was just some misplaced debug leftovers of mine.
Fixes:
b88c46fa11ae ("ci: Add a freedreno a630 tracie run.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5653>
Eric Anholt [Wed, 10 Jun 2020 20:11:21 +0000 (13:11 -0700)]
freedreno/a6xx: Add support for polygon fill mode (as long as front==back).
Unlike a4xx, we don't seem to have separate back vs front fields any more.
Still, this improves desktop GL conformance (and one of the traces in
traces-db).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
Eric Anholt [Wed, 10 Jun 2020 20:05:53 +0000 (13:05 -0700)]
turnip: Add support for polygon fill modes.
Passes the new tests in dEQP-VK.rasterization.culling.*
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
Eric Anholt [Wed, 10 Jun 2020 19:59:38 +0000 (12:59 -0700)]
freedreno/a6xx: Define the register fields for polygon fill mode.
Produced by comparing the traces of:
dEQP-VK.rasterization.culling.front_triangles
dEQP-VK.rasterization.culling.front_triangles_point
dEQP-VK.rasterization.culling.front_triangles_line
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
Eric Anholt [Mon, 8 Jun 2020 21:51:59 +0000 (14:51 -0700)]
ci: Add a freedreno a630 tracie run.
This job runs in about one minute on the current set of traces, and has
successfully revealed some bugs in our current rendering. Takes about 7
minutes currently.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Eric Anholt [Wed, 24 Jun 2020 17:47:37 +0000 (10:47 -0700)]
ci/tracie: Fix apitrace dump using "less" which isn't in the ARM rootfs.
You would get no output during the "find the last frame" step of the trace
replay.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Eric Anholt [Wed, 10 Jun 2020 02:01:06 +0000 (19:01 -0700)]
ci/tracie: Print the path if the trace isn't found.
I hit this a few times while setting up CI.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Rohan Garg [Tue, 28 Jan 2020 14:19:53 +0000 (15:19 +0100)]
ci: Include trace replay support in ARM rootfses.
Builds the renderdoc and apitrace programs so we can replay GL traces on
DUTs.
[Separated out from 5472's commit that also enabled the jobs in LAVA,
dropped unnecessary python packages from arm_build, fixed up arm64_test
build, traces-db in baremetal, new commit message by anholt]
Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Eric Anholt [Wed, 10 Jun 2020 21:17:23 +0000 (14:17 -0700)]
ci/bare-metal: Don't include dev packages in arm*test.
We just need these to build our rootfs, clean them out afterwards.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Eric Anholt [Mon, 22 Jun 2020 23:54:10 +0000 (16:54 -0700)]
ci/bare-metal: Skip setting of unset variables at startup.
It's silly to be setting (and logging the setting of!) all the env vars we
*didn't* set in a job.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Tomeu Vizoso [Mon, 15 Jun 2020 11:29:22 +0000 (13:29 +0200)]
ci: Move ARM rootfses to stable
We build in Debian buster but were currently testing in bullseye-based
ramdisks. This has started being a problem since Python 3.7 was removed
from bullseye.
[ Also bumped arm_test containers, by anholt ]
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Tomeu Vizoso [Tue, 14 Apr 2020 13:57:08 +0000 (15:57 +0200)]
ci: Don't call renderdoc's ReplayController.Shutdown()
If we do, Renderdoc will call eglDestroyContext twice, causing crashes
within Mesa.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
Jonathan Marek [Wed, 24 Jun 2020 20:00:30 +0000 (16:00 -0400)]
turnip: implement VK_KHR_shader_draw_parameters
Note: going by the blob, VFD_INDEX_OFFSET/FD_INSTANCE_START_OFFSET seem
completely unused by indirect draws, so this changes them to only be set
for non-indirect draws (and moves them to the vs_params draw state).
Passes dEQP-VK.draw.shader_draw_parameters.*
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
Jonathan Marek [Wed, 24 Jun 2020 19:58:44 +0000 (15:58 -0400)]
freedreno/ir3: add support for load_draw_id
This is part of adding VK_KHR_shader_draw_parameters for turnip.
IR3_DP_VTXID_BASE/IR3_DP_VTXCNT_MAX offsets are changed to match what
CP_DRAW_INDIRECT_MULTI requires.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
Jonathan Marek [Wed, 24 Jun 2020 19:53:28 +0000 (15:53 -0400)]
freedreno/registers: add CP_DRAW_INDIRECT_MULTI
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
Samuel Pitoiset [Thu, 25 Jun 2020 13:28:28 +0000 (15:28 +0200)]
gitlab-ci: add a list of expected failures for RADV/ACO on NAVI14
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5647>
Daniel Schürmann [Thu, 19 Sep 2019 11:43:35 +0000 (13:43 +0200)]
radv: enable ACO by default
No more dragons have been seen, caution is still required...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>
Daniel Schürmann [Thu, 11 Jun 2020 09:43:02 +0000 (10:43 +0100)]
radv: change use_aco -> use_llvm
We are about to make ACO the default backend.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>
Daniel Schürmann [Fri, 12 Jun 2020 16:55:00 +0000 (17:55 +0100)]
radv: introduce RADV_DEBUG=llvm option
This option enables the LLVM compiler backend to be used
for shader compilation
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>
Mike Blumenkrantz [Fri, 29 May 2020 18:46:53 +0000 (14:46 -0400)]
zink: unify code for setting resource barriers
no functional changes, this code was just duplicated
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5615>
Samuel Pitoiset [Wed, 24 Jun 2020 07:15:47 +0000 (09:15 +0200)]
radv: lower 64-bit dfloor on GFX6 for fixing precision issues
GFX6 doesn't support v_floor_f64 and the precision of v_fract_f64
which is used to implement 64-bit floor is less than what Vulkan
requires.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5609>
Samuel Pitoiset [Tue, 23 Jun 2020 16:29:22 +0000 (18:29 +0200)]
radv: lower 64-bit drcp/dsqrt/drsq for fixing precision issues
The hardware precision of v_rcp_f64, v_sqrt_f64 and v_rsq_f64
is less than what Vulkan requires.
This lowers using the Goldschmidt's algorithm to improve precision.
Fixes dEQP-VK.glsl.builtin.precision_double.* on both compiler
backends.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5609>
Danylo Piliaiev [Fri, 24 Apr 2020 12:11:44 +0000 (15:11 +0300)]
iris: Honor scanout requirement from DRI
Translate PIPE_BIND_SCANOUT as ISL_SURF_USAGE_DISPLAY_BIT,
instead of PIPE_BIND_DISPLAY_TARGET.
PIPE_BIND_DISPLAY_TARGET isn't used for dri images and seem to
be set only for fake winsys buffers (which aren't displayed).
The trouble is that a fake buffer could be multisampled and we
cannot have multisampled surface with display bit.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2313
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4784>
Pavel Asyutchenko [Tue, 23 Jun 2020 20:10:38 +0000 (23:10 +0300)]
vulkan/overlay: fix crash on destroying NULL swapchain
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5616>
Samuel Pitoiset [Thu, 18 Jun 2020 09:53:21 +0000 (11:53 +0200)]
gitlab-ci: add parallel-rdp fossils
https://github.com/Themaister/parallel-rdp
These fossils contain very large and complex shaders.
The small_*.foz files use 8/16-bit arithmetic.
Only RADV uses Fossilize.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5542>
Rob Clark [Mon, 22 Jun 2020 23:18:13 +0000 (16:18 -0700)]
freedreno/ir3/ra: fix pre-color edge case
Fixes a case where you have something like:
aVecOutput.z = aScalarInput;
In particular, skipping over things that are not the first component is
wrong.. in the above case the input we need to precolor is the 3rd
component. But we need to adjust the target register according to the
offset.
Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5601>
Jonathan Marek [Mon, 22 Jun 2020 02:08:45 +0000 (22:08 -0400)]
turnip: disable early_z for VK_FORMAT_S8_UINT
This format doesn't have depth, and apparently having earlyz enabled can
cause issues. Fixes at least these tests:
dEQP-VK.renderpass.suballocation.multisample.s8_uint.samples_*
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5586>
Jonathan Marek [Sun, 21 Jun 2020 03:34:53 +0000 (23:34 -0400)]
turnip: fix update_stencil_mask
The previous value was not being cleared, resulting in some dynamic stencil
state failures. Fixes these two tests:
dEQP-VK.dynamic_state.ds_state.stencil_params_advanced
dEQP-VK.dynamic_state.ds_state.stencil_params_basic_1
Fixes:
233610f8cf8d8810 ("turnip: refactor draw states and dynamic states")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5586>
Jonathan Marek [Sun, 21 Jun 2020 03:20:32 +0000 (23:20 -0400)]
turnip: fix empty scissor case
Fixes these two tests:
dEQP-VK.draw.scissor.empty_dynamic_scissor_first_draw
dEQP-VK.draw.scissor.empty_static_scissor
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5586>
Rob Clark [Wed, 24 Jun 2020 18:28:32 +0000 (11:28 -0700)]
freedreno: handle batch flush in resource tracking
In rare cases, we can get into situations where the tracking of read/
written resources triggers a flush of the current batch.
To handle that, (1) take a reference to the current batch, so it doesn't
disappear under us, and (2) check after resource tracking whether the
current batch was flushed. If it is, we have to re-do the resource
tracking, but since we have a fresh batch, it should not get flushed the
second time around.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3160
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
Rob Clark [Wed, 24 Jun 2020 16:31:03 +0000 (09:31 -0700)]
freedreno: split out batch clear tracking helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
Rob Clark [Wed, 24 Jun 2020 16:23:50 +0000 (09:23 -0700)]
freedreno: split out batch draw tracking helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
Rob Clark [Wed, 24 Jun 2020 16:06:50 +0000 (09:06 -0700)]
freedreno: make foreach_bit() declare it's cursor
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5634>
Jonathan Marek [Wed, 24 Jun 2020 23:56:01 +0000 (19:56 -0400)]
turnip: implement VK_EXT_vertex_attribute_divisor
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5640>
Eric Engestrom [Wed, 24 Jun 2020 23:48:24 +0000 (01:48 +0200)]
docs: fix 20.1.2 relnotes
I manually converted them from html and didn't double-check the
result...
Fixes:
e94f81e9df8f038813a4 ("docs: Add release notes for 20.1.2")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5639>
Eric Engestrom [Wed, 24 Jun 2020 22:58:56 +0000 (00:58 +0200)]
docs: update calendar and link releases notes for 20.1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5638>
Eric Engestrom [Wed, 24 Jun 2020 21:44:30 +0000 (23:44 +0200)]
docs: Add release notes for 20.1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5638>
Rob Clark [Sun, 21 Jun 2020 20:26:57 +0000 (13:26 -0700)]
freedreno/ir3: switch PIPE_CAP_TGSI_TEXCOORD
We don't really need the varying remapping, and it seems to somehow
happen twice when shader-cache comes into the picture. But we can
just choose not to have this problem.
Now that everything is using the ir3_point_sprite() helper, we can
flip this pipe cap without it being a massive flag-day.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 18:54:43 +0000 (11:54 -0700)]
freedreno: convert builtin blit VS prog to ureg builder
The correct varying semantic to use depends on PIPE_CAP_TGSI_TEXCOORD.
To handle this transition switch it over to ureg builder, and query the
pipe-cap to choose the appropriate semantic.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 15:47:33 +0000 (08:47 -0700)]
freedreno/a3xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 15:46:35 +0000 (08:46 -0700)]
freedreno/a4xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 15:45:13 +0000 (08:45 -0700)]
freedreno/a5xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 15:43:17 +0000 (08:43 -0700)]
freedreno/a6xx: use point-coord helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 15:39:12 +0000 (08:39 -0700)]
freedreno/a6xx: de-duplicate vinterp/vpsrepl state building
When we flip the texcoord patch, we'll setup PNTC input slot in the
pre-built interp stateobj, rather than this being a draw-time (slow-
path) built stateobj. But rather than duplicate more of the slow-
path logic, refactor it out into a helper that is reused in both
cases.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Rob Clark [Mon, 22 Jun 2020 15:24:55 +0000 (08:24 -0700)]
freedreno/ir3: add helper to determine point-coord inputs
This will simplify a bit the logic for setting up vinterp/vprepl in the
driver backend, and also avoid it being a flag-day when we switch the
texcoord pipe cap.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5595>
Jonathan Marek [Sat, 13 Jun 2020 02:12:51 +0000 (22:12 -0400)]
turnip: move some logic out of create_render_pass_common
CreateRenderPass2 is the common path now, it doesn't make sense to have a
create_render_pass_common. Rename it to tu_render_pass_gmem_config and
move logic not related to gmem config out of it.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5451>
Jonathan Marek [Sat, 13 Jun 2020 02:05:26 +0000 (22:05 -0400)]
turnip: use RenderPassCreateInfo for render_pass_add_implicit_deps
This gets rid of the some unnecessary values that were stored in
tu_render_pass for this. It also makes the render_pass_add_implicit_deps
more generic, with very few references to the tu_render_pass.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5451>
Jonathan Marek [Sat, 13 Jun 2020 01:43:24 +0000 (21:43 -0400)]
turnip: replace a memset(0) with zalloc in CreateRenderPass
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5451>
Jonathan Marek [Sat, 13 Jun 2020 01:19:20 +0000 (21:19 -0400)]
turnip: translate CreateRenderPass to CreateRenderPass2
It doesn't cut down the code size by much, and might not be the ideal for
performance (unless the compiler is unexpectedly smart), but makes it
easier to maintain (no modifying the same code in two places) and will
allow some simplifications since we wont have to worry about trying to
share code between the two versions.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5451>
Jonathan Marek [Tue, 23 Jun 2020 22:45:32 +0000 (18:45 -0400)]
turnip: implement depthBounds
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>
Jonathan Marek [Tue, 23 Jun 2020 22:44:42 +0000 (18:44 -0400)]
freedreno/registers: a6xx depth bounds test registers
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5628>
Rhys Perry [Tue, 16 Jun 2020 13:58:15 +0000 (14:58 +0100)]
aco: remove outdated assert in handle_operands()
"target" is no longer expected to be completely inside "swap".
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5626>
Rhys Perry [Wed, 24 Jun 2020 12:23:12 +0000 (13:23 +0100)]
aco: ignore blocked registers when checking edges in get_reg_impl()
If the only two registers available are consecutive and used by killed
operands, both of them will be blocked and fail the edge check.
Totals from 903 (0.66% of 135946) affected shaders:
VGPRs: 30892 -> 30884 (-0.03%)
CodeSize: 1584468 -> 1584044 (-0.03%); split: -0.05%, +0.02%
MaxWaves: 14374 -> 14378 (+0.03%)
Instrs: 306482 -> 306399 (-0.03%); split: -0.06%, +0.03%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5626>
Samuel Pitoiset [Wed, 24 Jun 2020 13:38:19 +0000 (15:38 +0200)]
radv: fix checking the return value of cs_finalize()
cs_finalize() now returns a Vulkan error code and VK_SUCCESS is 0.
Fixes:
64a92ef7a26 ("radv/winsys: Distinguish device/host memory errors.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5629>
Samuel Pitoiset [Wed, 24 Jun 2020 12:30:46 +0000 (14:30 +0200)]
gitlab-ci: update the list of expected failures for Pitcairn
These tests have been fixed as part of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5625>
Bas Nieuwenhuizen [Tue, 23 Jun 2020 23:28:54 +0000 (01:28 +0200)]
radv: Make radv_alloc_shader_memory static.
Just a cleanup.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5578>
Bas Nieuwenhuizen [Sun, 21 Jun 2020 17:36:16 +0000 (19:36 +0200)]
radv/winsys: Distinguish device/host memory errors.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5578>
Bas Nieuwenhuizen [Sat, 20 Jun 2020 19:12:01 +0000 (21:12 +0200)]
radv: Handle mmap failures.
Which can happen if we have to many mmaps active in the process.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5578>
Bas Nieuwenhuizen [Sat, 20 Jun 2020 18:34:59 +0000 (20:34 +0200)]
radv/winsys: Deal with realloc failures in BO lists.
Otherwise if realloc fails we silently try to use it. Make recording fail instead.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5578>
Rhys Perry [Mon, 25 May 2020 14:36:12 +0000 (15:36 +0100)]
aco: improve vectorization of 8/16-bit loads/stores
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>
Rhys Perry [Tue, 23 Jun 2020 18:19:00 +0000 (19:19 +0100)]
aco: fix when sub-dword create_vector operand cannot be placed perfectly
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>
Daniel Schürmann [Tue, 23 Jun 2020 09:19:27 +0000 (10:19 +0100)]
aco: don't allow partial copies on GFX6/7
These are not supported due to missing SDWA instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>
Daniel Schürmann [Tue, 23 Jun 2020 10:55:34 +0000 (11:55 +0100)]
aco: align swap operations to 4 bytes on GFX6/7
GFX6/7 can only swap full registers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>
Rhys Perry [Thu, 11 Jun 2020 14:38:07 +0000 (15:38 +0100)]
aco: don't create byte-aligned short loads
The ISA docs don't seem to say if this is allowed, so just assume short
loads require short alignment.
In practice, the only situation this should affect are byte-aligned u8vec2
loads.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>
Rhys Perry [Tue, 26 May 2020 16:45:56 +0000 (17:45 +0100)]
aco: add missing bld.scc() in byte_align_scalar()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5207>