Marek Olšák [Tue, 5 Sep 2017 22:50:45 +0000 (00:50 +0200)]
winsys/amdgpu: use the new raw CS API
This also cleans things up.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Sep 2017 22:31:58 +0000 (00:31 +0200)]
radeonsi: implement pipe_context::fence_server_sync
This will be more useful once we have sync_file support.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Sep 2017 22:22:35 +0000 (00:22 +0200)]
winsys/amdgpu: factor out some fence dependency code into separate functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Sep 2017 21:59:13 +0000 (23:59 +0200)]
winsys/amdgpu: rename fence_dependency functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Sep 2017 21:26:59 +0000 (23:26 +0200)]
gallium/radeon: add a proper fail path for calloc in r600_flush_from_st
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Sep 2017 01:21:29 +0000 (03:21 +0200)]
winsys/amdgpu: don't allow interprocess resource sharing for IBs
Now we should get IB submissions with bo_list == NULL when DRI buffers
aren't referenced.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Sep 2017 00:53:20 +0000 (02:53 +0200)]
radeonsi/gfx9: fix interprocess resource sharing on Raven
This kinda fragiile, but it at least unbreaks the driver.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 7 Sep 2017 16:43:42 +0000 (18:43 +0200)]
st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index
Don't get distracted by record dereferences between array references.
Fixes dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex_block.*
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Iglesias Gonsálvez [Tue, 29 Aug 2017 04:56:26 +0000 (06:56 +0200)]
nir/spirv: fix chain access with different index bit sizes
Currently we support 32-bit indexes/offsets all over the driver, so we
convert them to that bit size.
Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.*
v2: Use u2u32 instead (Jason).
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Mon, 21 Aug 2017 01:05:31 +0000 (11:05 +1000)]
r600: handle the non-TXF_LZ support path.
it appears that texcoord.z/w will be 0 in all cases already,
so just put them into the vbo always.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Thu, 17 Aug 2017 13:48:10 +0000 (15:48 +0200)]
gallium/u_blitter: use UTIL_BLITTER_ATTRIB_NONE (0) instead of 0 directly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 13:17:58 +0000 (15:17 +0200)]
gallium/u_blitter: don't pass GENERIC in VS if it's not needed
Now, depth-only clears and custom passes don't read memory in VS.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 01:32:23 +0000 (03:32 +0200)]
gallium/u_blitter: use draw_rectangle for all blits except cubemaps
Add ZW coordinates to the draw_rectangle callback and use it.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 00:38:23 +0000 (02:38 +0200)]
gallium/u_blitter: use draw_rectangle callback for layered clears
They are done with instancing.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 17 Aug 2017 00:09:54 +0000 (02:09 +0200)]
gallium/u_blitter: add new union blitter_attrib to replace pipe_color_union
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 16 Aug 2017 00:18:27 +0000 (02:18 +0200)]
gallium/radeon: use rectangles for 1D and 2D texture blits
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Engestrom [Sat, 9 Sep 2017 22:26:36 +0000 (23:26 +0100)]
i965/tex: add missing include
src/mesa/drivers/dri/i965/intel_tex.h:52:40: warning: ‘enum intel_miptree_create_flags’ declared inside parameter list will not be visible outside of this definition or declaration
enum intel_miptree_create_flags flags);
^~~~~~~~~~~~~~~~~~~~~~~~~~
Fixes:
cadcd89278edcda8aba2 "i965/tex: Change the flags type on
create_for_teximage"
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bas Nieuwenhuizen [Thu, 7 Sep 2017 20:12:50 +0000 (22:12 +0200)]
radv: Actually check for vm faults.
The code can check for vm faults having happened. If we only do it
on a hang we don't know when the faults happened. This changes the
behavior to when the first VM faults is found, even without a hang.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Roland Scheidegger [Fri, 8 Sep 2017 00:59:11 +0000 (02:59 +0200)]
llvmpipe, draw: improve shader cache debugging
With GALLIVM_DEBUG=perf set, output the relevant stats for shader cache usage
whenever we have to evict shader variants.
Also add some output when shaders are deleted (but not with the perf setting
to keep this one less noisy).
While here, also don't delete that many shaders when we have to evict. For fs,
there's potentially some cost if we have to evict due to the required flush,
however certainly shader recompiles have a high cost too so I don't think
evicting one quarter of the cache size makes sense (and, if we're evicting
based on IR count, we probably typically evict only very few or just one
shader too). For vs, I'm not sure it even makes sense to evict more than
one shader at a time, but keep the logic the same for now.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Fri, 8 Sep 2017 00:23:05 +0000 (02:23 +0200)]
llvmpipe: enable PIPE_CAP_QUERY_PIPELINE_STATISTICS
This was implemented since forever, but not enabled.
It passes all piglit tests except one, arb_pipeline_statistics_query-frag.
The reason is that the test (for drawing a 10x10 rect) expects between
100 and 150 pixel shader invocations. But since llvmpipe counts this with
4x4 granularity (and due to the rect being 2 tris) we end up with 224
invocations. I believe however what llvmpipe is doing violates neither the
spirit nor the letter of the spec (our fragment shader granularity really
is 4x4 pixels, albeit we will bail out early on 2x2 or 4x2 (the latter
if AVX is available) granularity), the spec allows to count additional
invocations due to implementation reasons.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sat, 9 Sep 2017 00:58:21 +0000 (02:58 +0200)]
gallivm: fix gather implementation a bit
gather is defined in terms of bilinear filtering, just without the filtering
part. However, there's actually some subtle differences required in our
implementation, because we use some tricks to simplify coord wrapping for the
two coords per direction.
For bilinear filtering, we don't care if we end up with an incorrect
texel, as long as the filter weight is 0.0 for it. Likewise, the order of
the texels doesn't actually matter (as long as they still have the correct
filter weight).
But for gather, these tricks lead to incorrect results.
Fix this for CLAMP_TO_EDGE, and add some comments to the other wrap functions
which look broken (the 3 mirror_clamp plus mirror_repeat) (too complex to fix
right now, and noone really seems to care...).
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Andres Gomez [Fri, 8 Sep 2017 23:15:41 +0000 (02:15 +0300)]
docs: update calendar, add news item and link release notes for 17.1.9
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 8 Sep 2017 23:09:33 +0000 (02:09 +0300)]
docs: add sha256 checksums for 17.1.9
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Fri, 8 Sep 2017 22:59:59 +0000 (01:59 +0300)]
docs: add release notes for 17.1.9
Signed-off-by: Andres Gomez <agomez@igalia.com>
Brian Paul [Tue, 5 Sep 2017 19:03:45 +0000 (13:03 -0600)]
mesa: whitespace, formatting fixes in teximage.c
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Tue, 5 Sep 2017 18:56:19 +0000 (12:56 -0600)]
mesa: provide more info in some texture image error messages
Reviewed-by: Eric Anholt <eric@anholt.net>
Charmaine Lee [Wed, 2 Aug 2017 01:02:57 +0000 (18:02 -0700)]
svga: abort shader translation upon indirect indexing of temporaries
This patch aborts shader translation upon indirect indexing of temporary
register on non-vgpu10 device. This prevents non-supported feature
sending to the device.
Tested wth MTT-piglit, glretrace.
Reviewed-by: Brian Paul <brianp@vmware.com>
Samuel Pitoiset [Fri, 1 Sep 2017 11:45:33 +0000 (13:45 +0200)]
radv: keep track of the disasm string in debug mode only
This will allow to dump the active shaders when a hang is
detected. Only the ASM will be dumped for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 1 Sep 2017 14:51:12 +0000 (16:51 +0200)]
radv: add shader_variant_create() helper function
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 1 Sep 2017 10:09:56 +0000 (12:09 +0200)]
radv: drop 'dump' parameters from some shader related functions
The device object contains the debug flags.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 1 Sep 2017 09:41:18 +0000 (11:41 +0200)]
radv: move shaders related code to radv_shader.c
Reduce size of radv_pipeline.c and improve code isolation. More
code can probably moved but it's a start.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Sep 2017 14:09:46 +0000 (16:09 +0200)]
radv: fix error code when initializing the push descriptors
malloc() failures are unrelated to the device memory.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 6 Sep 2017 15:25:27 +0000 (17:25 +0200)]
radv: do not update vertex descriptors if the allocation failed
A return code error is stored in the command buffer and should
be returned to the user via EndCommandBuffer().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 6 Sep 2017 15:21:47 +0000 (17:21 +0200)]
radv: add radv_vertex_elements_info data structure
In my opinion, this improves code readability.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Wed, 6 Sep 2017 10:33:15 +0000 (11:33 +0100)]
gallium/tests: use ARRAY_SIZE macro
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Engestrom [Wed, 6 Sep 2017 10:20:46 +0000 (11:20 +0100)]
r300: use ARRAY_SIZE macro
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Engestrom [Mon, 4 Sep 2017 12:51:53 +0000 (13:51 +0100)]
glx: use ARRAY_SIZE macro
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>
Samuel Pitoiset [Thu, 7 Sep 2017 13:30:38 +0000 (15:30 +0200)]
radv: add an assertion when pushing meta descriptor sets
Just to make sure we are using the set 0, because it's the
only one which is saved/restored when doing meta operations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Thomas Hellstrom [Thu, 7 Sep 2017 08:45:10 +0000 (10:45 +0200)]
mesa/st: Fix frontbuffer rendering regression
This fixes a regression introduced with commit
"mesa/st: Reduce the number of frontbuffer flush calls"
where we, after flushing the front buffer marked it as not-rendered-to,
the idea being that it should be marked as "rendered-to" again as soon as
any rendering was touching the front.
Now the latter part never happened, because it was part of a state
validation and we never marked that part of the state as dirty.
So mark the framebuffer state dirty after a frontbuffer flush.
(fdo bugzilla 102496)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102496
Fixes:
eceb671002 (mesa/st: Reduce the number of frontbuffer flush calls)
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>
Kenneth Graunke [Sat, 2 Sep 2017 00:32:01 +0000 (17:32 -0700)]
i965: Don't special case the batchbuffer when reference counting.
We don't need to special case the batch - when we add the batch to the
validation list, we can simply increase the refcount to 2, and when we
make a new batch, we'll drop it back down to 1 (when unreferencing all
buffers in the validation list). The final reference is still held by
brw->batch.bo, as it was before.
This removes the special case from a bunch of loops.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Connor Abbott [Wed, 19 Jul 2017 00:35:35 +0000 (17:35 -0700)]
ac: remove bitcast_to_float()
ac_to_float() does a superset of what it does.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Connor Abbott [Wed, 19 Jul 2017 00:32:10 +0000 (17:32 -0700)]
ac: move ac_to_integer() and ac_to_float() to ac_llvm_build.c
We'll need to use ac_to_integer() for other stuff in ac_llvm_build.c.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Connor Abbott [Wed, 19 Jul 2017 03:44:47 +0000 (20:44 -0700)]
ac: fix ac_get_type_size() for doubles
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 8 Sep 2017 03:15:50 +0000 (04:15 +0100)]
radv/ac: use ac_get_type_size.
Just moved to newly shared code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Connor Abbott [Tue, 6 Jun 2017 23:40:26 +0000 (16:40 -0700)]
radeonsi: move the guts of ARB_shader_group_vote emission to ac
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Connor Abbott [Mon, 5 Jun 2017 22:20:04 +0000 (15:20 -0700)]
radeonsi: move si_emit_ballot() to ac
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Connor Abbott [Mon, 5 Jun 2017 21:16:43 +0000 (14:16 -0700)]
radeonsi: move emit_optimization_barrier() to ac
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Connor Abbott [Mon, 5 Jun 2017 21:37:01 +0000 (14:37 -0700)]
radeonsi: move llvm_get_type_size() to ac
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 8 Sep 2017 02:30:23 +0000 (12:30 +1000)]
radv/winsys: fix flags vs va_flags thinko.
Fixes:
e8d57802f (radv/gfx9: allocate events from uncached VA space)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 7 Sep 2017 03:02:33 +0000 (04:02 +0100)]
radv: use simpler indirect packet 3 if possible.
This fixes some observed hangs on CIK GPUs.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 7 Sep 2017 03:40:57 +0000 (20:40 -0700)]
radv/gfx9: allocate events from uncached VA space
This copies what amdgpu-pro does, and allocates the memory
for an event with an uncached mtype.
This fixes hangs with:
dEQP-VK.api.command_buffers.record_simul_use_primary
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 7 Sep 2017 19:54:51 +0000 (20:54 +0100)]
radv/winsys: use amdgpu_bo_va_op_raw.
This is a precursor to the gfx9 fix to use uncached for the event
memory. Move to the interface which allows setting the flags,
but wrap it to avoid having to copy it around the place.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Leo Liu [Wed, 23 Aug 2017 20:24:59 +0000 (16:24 -0400)]
Revert "st/va: add enviromental variable to disable interlace"
This reverts commit
10dec2de2d9f568675d66d736b48701fa26f7b50.
The environment variable is no longer needed with the previous change
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 29 Aug 2017 03:07:33 +0000 (23:07 -0400)]
st/va: move YUV content to deinterlaced buffer when reallocated for encoder
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 29 Aug 2017 02:59:56 +0000 (22:59 -0400)]
st/va: reallocate the buffer if the layout isn't supported
So that it makes more clear for buffer reallocation based
on buffers layout for both decoder and encoder.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 29 Aug 2017 01:12:57 +0000 (21:12 -0400)]
vl/compositor: make vl_compositor_set_yuv_layer() static
Since it's no longer being called outside of compositor
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 29 Aug 2017 01:05:03 +0000 (21:05 -0400)]
st/omx: use vl/compositor helper function for YUV deinterlacing
v2: separate helper function in different patch
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Leo Liu [Tue, 29 Aug 2017 00:58:48 +0000 (20:58 -0400)]
vl/compositor: make a helper function for YUV deinterlacing
The similar function is in OMX, and only used by OMX. Now have it
moved to vl/compositor for other state tracker to use later.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Wed, 6 Sep 2017 22:13:37 +0000 (00:13 +0200)]
ac/surface: add radeon_surf::has_stencil for convenience
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Gert Wollny [Wed, 6 Sep 2017 19:24:34 +0000 (21:24 +0200)]
mesa/st/tests: Fix regressions with libunwind enabled introduced with
7be6d8fe12
Add the according flags to link with libunwind.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102565
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Gert Wollny [Wed, 6 Sep 2017 19:24:33 +0000 (21:24 +0200)]
mesa/st/tests: Fix classic build regressions introduced with
7be6d8fe12
Fixes the build in classic only mode, i.e. the new state tracker tests are
only build when Gallium is enabled.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Iago Toral Quiroga [Tue, 5 Sep 2017 11:54:31 +0000 (13:54 +0200)]
mesa/main: Fix GetTransformFeedbacki64 for glTransformFeedbackBufferBase
The spec has special rules for querying buffer offsets and sizes
when BindBufferBase is used, described in the OpenGL 4.6 spec,
section 6.8 Buffer Object State:
"To query the starting offset or size of the range of a buffer
object binding in an indexed array, call GetInteger64i_v with
target set to respectively the starting offset or binding size
name from table 6.5 for that array. Index must be in the range
zero to the number of bind points supported minus one. If the
starting offset or size was not specified when the buffer object
was bound (e.g. if it was bound with BindBufferBase), or if no
buffer object is bound to the target array at index, zero is
returned."
Transform feedback buffer queries should follow the same rules, since
it is the same case for them. There is a CTS test for this.
Fixes:
KHR-GL45.direct_state_access.xfb_buffers
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Marek Olšák [Tue, 5 Sep 2017 18:09:05 +0000 (20:09 +0200)]
radeonsi: don't read tcs_out_lds_layout.patch_stride from an SGPR
Same as before, writing TCS outputs to LDS is rare.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Sep 2017 17:52:23 +0000 (19:52 +0200)]
radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPR
TCS outputs are usually not written to LDS, so no stats here.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Sep 2017 17:02:13 +0000 (19:02 +0200)]
radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HS
-44 bytes in a monolithic LS-HS binary.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Sep 2017 15:46:09 +0000 (17:46 +0200)]
radeonsi: don't read the LS output vertex stride from an SGPR in LS
Now it's able to generate ds_write2_b64 instead of ds_write2_b32.
-20 bytes in one shader binary. (having only 1 output)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Sep 2017 15:46:09 +0000 (17:46 +0200)]
radeonsi: don't read the number of TCS out vertices from an SGPR in TCS
-16 bytes in one shader binary.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Sep 2017 15:04:31 +0000 (17:04 +0200)]
radeonsi: don't always apply the PrimID instancing bug workaround on SI
It looks like commit
391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908 that should
have fixed the perf regression didn't really change much if anything.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Sep 2017 11:01:43 +0000 (13:01 +0200)]
radeonsi: remove 2 callbacks from si_shader_context
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Sep 2017 22:32:39 +0000 (00:32 +0200)]
winsys/amdgpu: disable local BOs on Raven
It hangs with a high degree of reproducibility.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 6 Sep 2017 21:09:41 +0000 (23:09 +0200)]
disk_cache: make the thread queue resizable and low priority
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Thomas Hellstrom [Tue, 5 Sep 2017 08:07:13 +0000 (10:07 +0200)]
loader/dri3: Make sure we invalidate a drawable on size change
If we're seeing a drawable size change, in particular after processing a
configure notify event, make sure we invalidate so that the state tracker
picks up the new geometry.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Tue, 5 Sep 2017 07:58:08 +0000 (09:58 +0200)]
loader/dri3: Process event after each fence wait
This tries to mimic dri2 behaviour where events are typically processed
while waiting for X replies. Since, during steady-state dri3 rendering, we
seldom wait for xcb replies, and haven't enabled any automatic event
processing, instead check for events after a fence wait.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Fri, 1 Sep 2017 21:27:35 +0000 (23:27 +0200)]
st/mesa: skip draw calls with pipe_draw_info::count == 0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102502
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Eric Engestrom [Thu, 7 Sep 2017 10:10:55 +0000 (11:10 +0100)]
docs: update envvar docs to reflect MESA_NO_ERROR change
I changed the behaviour earlier today, but forgot to update the
corresponding docs.
Fixes:
77713a0acb09f475d29f "mesa: allow user to set MESA_NO_ERROR=0"
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Samuel Pitoiset [Wed, 6 Sep 2017 13:46:18 +0000 (15:46 +0200)]
radv: do not use a bitfield when dirtying the vertex buffers
Useless to track which one has been updated because we
re-upload all the vertex buffers in one shot.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 6 Sep 2017 13:38:59 +0000 (15:38 +0200)]
radv: remove unused radv_meta_saved_state::vertex_saved field
It's always false.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Wed, 6 Sep 2017 14:24:02 +0000 (14:24 +0000)]
mesa: allow user to set MESA_NO_ERROR=0
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102530
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Eric Engestrom [Wed, 6 Sep 2017 14:23:52 +0000 (14:23 +0000)]
util: rename include guard to avoid clash
src/mesa/main/debug.h uses the same include guard.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Roland Scheidegger [Tue, 5 Sep 2017 15:59:37 +0000 (17:59 +0200)]
llvmpipe, tgsi: hook up dx10 gather4 opcode
Trivial. We already support tg4 for legacy tex opcodes, so the actual
texture sampling code already handles it.
(Just like TG4, we don't handle additional capabilities and always sample
red channel.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 4 Sep 2017 22:17:31 +0000 (00:17 +0200)]
llvmpipe, draw: increase shader cache limits
We're not particularly concerned with memory usage, if the tradeoff is
shader recompiles. And it's common for apps to have a lot of shaders
nowadays (and, since our shaders include a LOT of context state of course
we may create quite a bit more shaders even).
So quadruple the amount of shaders draw will cache (from 128 to 512).
For llvmpipe (fs shaders) quadruple the number of instructions, keep the
number of variants the same for now (only with very simple, non-texturing
shaders the variant limit could really be reached), and simplify the
definition, it's probably easier to just have one different definition
per branch...
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Dave Airlie [Wed, 6 Sep 2017 03:47:51 +0000 (13:47 +1000)]
ac/surface: reduce gfx9_surface_layout size.
152->144.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Sep 2017 03:40:50 +0000 (13:40 +1000)]
radv: reduce radv_amdgpu_winsys struct size.
1168->1160.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Sep 2017 03:39:58 +0000 (13:39 +1000)]
radv: reduce radv_image struct size.
1480->1472.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Sep 2017 03:39:07 +0000 (13:39 +1000)]
radv: reduce radv_shader_variant struct size.
544->536
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Sep 2017 03:38:30 +0000 (13:38 +1000)]
radv: reduce radv_cmd_state struct size.
1632->1624.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Sep 2017 03:37:42 +0000 (13:37 +1000)]
radv: reduce meta_saved_state struct size.
904->896.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 6 Sep 2017 03:18:45 +0000 (13:18 +1000)]
nir: put compact into bitfields in nir_variable_data
This being declared bool means it won't get merged with the previous
bitfields, this seems like an oversight rather than deliberate.
Noticed when running pahole.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Chad Versace [Fri, 25 Aug 2017 12:04:13 +0000 (05:04 -0700)]
anv: Annotate entrypoint table with index and func name
This helps when debugging a broken entrypoint table.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Leo Liu [Tue, 5 Sep 2017 17:30:57 +0000 (13:30 -0400)]
radeon/uvd: fix the assertion check for YUYV format
Fixes:
7319ff87("radeon/uvd: add YUYV format support for target buffer")
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Anuj Phogat [Thu, 31 Aug 2017 18:33:12 +0000 (11:33 -0700)]
intel: Add brand string for KBL-R
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Anuj Phogat [Thu, 31 Aug 2017 18:29:03 +0000 (11:29 -0700)]
intel: Remove unused device info for KBL GT1.5
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Anuj Phogat [Thu, 31 Aug 2017 18:32:41 +0000 (11:32 -0700)]
intel: Change a KBL pci id to GT2 from GT1.5
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Anuj Phogat [Thu, 31 Aug 2017 18:18:21 +0000 (11:18 -0700)]
intel: Fix few KBL brand strings
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Anuj Phogat [Thu, 31 Aug 2017 18:14:42 +0000 (11:14 -0700)]
intel: Remove unused Kabylake pci ids
These PCI IDs are not used in any Kabylake SKUs.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Tue, 5 Sep 2017 14:10:45 +0000 (15:10 +0100)]
Revert "Android: add -Wno-date-time flag for clang"
This reverts commit
6dae9176d60d12de61aa03906c44f81e20ef7622.
No longer needed as of last commit.
Cc: Rob Herring <robh@kernel.org>
Emil Velikov [Tue, 5 Sep 2017 14:02:03 +0000 (15:02 +0100)]
mesa: replace date/time macros with MESA_GIT_SHA1
Former is non-deterministic, results in non-reproducible builds and
compilers throw a warning about it.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Emil Velikov [Tue, 5 Sep 2017 13:48:49 +0000 (14:48 +0100)]
mesa: don't use %s for PACKAGE_VERSION macro
The macro itself is a well defined string, which cannot cause issues
with printf or other printf-like functions.
All other places through Mesa already use it directly, so let's update
the final two instances.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Emil Velikov [Tue, 5 Sep 2017 14:09:15 +0000 (15:09 +0100)]
docs/release-calendar: update and extend
v2: Correct 17.1.10 version, adjust some names.
v3: Add missing <tr> (Andres)
Cc: Juan A. Suárez <jasuarez@igalia.com>
Cc: Andres Gomez <agomez@igalia.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Emil Velikov [Mon, 4 Sep 2017 16:19:43 +0000 (17:19 +0100)]
docs/releasing: polish LLVM_CONFIG wording/handling
Use consistent way to manage "non-default" llvm installations, clearly
documenting it.
AKA, use LLVM_CONFIG throughout and unset for the Windows/mingw builds.
v2: unset the save_ variable (Andres)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)