Giorgis Georgakoudis [Mon, 3 May 2021 04:49:05 +0000 (21:49 -0700)]
[OpenMP] Fix non-determinism in clang task codegen
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D101739
Benjamin Kramer [Mon, 3 May 2021 17:24:00 +0000 (19:24 +0200)]
[mlir] Fix multidimensional lowering from std.select to llvm.select
The converter assumed that all operands have the same type, that's not
true for select.
Differential Revision: https://reviews.llvm.org/D101767
thomasraoux [Mon, 3 May 2021 17:04:12 +0000 (10:04 -0700)]
[mlir][vector][NFC] split TransposeOp lowerning out of contractLowering
Move TransposeOp lowering in its own populate function as in some cases
it is better to keep it during ContractOp lowering to better
canonicalize it rather than emiting scalar insert/extract.
Differential Revision: https://reviews.llvm.org/D101647
Arthur Eubanks [Tue, 20 Apr 2021 19:44:19 +0000 (12:44 -0700)]
[docs][NewPM] Add section on analyses
Reviewed By: asbirlea, ychen
Differential Revision: https://reviews.llvm.org/D100912
Uday Bondhugula [Sun, 2 May 2021 09:40:22 +0000 (15:10 +0530)]
[MLIR] Fix TestAffineDataCopy for test cases with no load ops
Add missing check in -test-affine-data-copy without which a test case
that has no affine.loads at all would crash this test pass. Fix two
clang-tidy warnings in the file while at this. (Not adding a test case
given the triviality.)
Differential Revision: https://reviews.llvm.org/D101719
Stella Laurenzo [Sun, 2 May 2021 22:15:21 +0000 (15:15 -0700)]
[mlir][Python] Add casting constructor to Type and Attribute.
* This makes them consistent with custom types/attributes, whose constructors will do a type checked conversion. Of course, the base classes can represent everything so never error.
* More importantly, this makes it possible to subclass Type and Attribute out of tree in sensible ways.
Differential Revision: https://reviews.llvm.org/D101734
Chris Lattner [Sat, 1 May 2021 21:07:17 +0000 (14:07 -0700)]
[Support/Parallel] Add a special case for 0/1 items to llvm::parallel_for_each.
This avoids the non-trivial overhead of creating a TaskGroup in these degenerate
cases, but also exposes parallelism. It turns out that the default executor
underlying TaskGroup prevents recursive parallelism - so an instance of a task
group being alive will make nested ones become serial.
This is a big issue in MLIR in some dialects, if they have a single instance of
an outer op (e.g. a firrtl.circuit) that has many parallel ops within it (e.g.
a firrtl.module). This patch side-steps the problem by avoiding creating the
TaskGroup in the unneeded case. See this issue for more details:
https://github.com/llvm/circt/issues/993
Note that this isn't a really great solution for the general case of nested
parallelism. A redesign of the TaskGroup stuff would be better, but would be
a much more invasive change.
Differential Revision: https://reviews.llvm.org/D101699
Marek Kurdej [Mon, 3 May 2021 16:52:19 +0000 (18:52 +0200)]
[clang-format] Fix build on gcc < 7 introduced in rG8d93d7ff.
This fixes another bogus build error on gcc, e.g. https://lab.llvm.org/buildbot/#/builders/118/builds/2504.
/home/ssglocal/clang-cmake-x86_64-avx2-linux/clang-cmake-x86_64-avx2-linux-perf/llvm/clang/lib/Format/UnwrappedLineFormatter.cpp:424:42: error: binding ‘clang::format::FormatToken* const’ to reference of type ‘clang::format::FormatToken*&’ discards qualifiers
auto IsElseLine = [&First = TheLine->First]() -> bool {
^
Frederik Gossen [Mon, 3 May 2021 16:45:28 +0000 (18:45 +0200)]
[MLIR][Linalg] Lower `linalg.tiled_loop` to `scf` loops
Differential Revision: https://reviews.llvm.org/D101747
Marek Kurdej [Mon, 3 May 2021 16:46:13 +0000 (18:46 +0200)]
[docs] Automatically update copyright year in libc++.
Marek Kurdej [Mon, 3 May 2021 16:44:47 +0000 (18:44 +0200)]
[docs] Bump the trunk major version to 13 and update copyright year.
David Green [Mon, 3 May 2021 16:34:05 +0000 (17:34 +0100)]
[AArch64] Fold CSEL x, x, cc -> x
This can come up in rare situations, where a csel is created with
identical operands. These can be folded simply to the original value,
allowing the csel to be removed and further simplification to happen.
This patch also removes FCSEL as it is unused, not being produced
anywhere or lowered to anything.
Differential Revision: https://reviews.llvm.org/D101687
Marek Kurdej [Mon, 3 May 2021 16:32:36 +0000 (18:32 +0200)]
[docs] Fix title overline.
Marek Kurdej [Mon, 3 May 2021 16:28:54 +0000 (18:28 +0200)]
[docs] Fix syntax typo.
Marek Kurdej [Mon, 3 May 2021 15:59:32 +0000 (17:59 +0200)]
[clang-format] Add options to AllowShortIfStatementsOnASingleLine to apply to "else if" and "else".
This fixes the bug http://llvm.org/pr50019.
Reviewed By: MyDeveloperDay
Differential Revision: https://reviews.llvm.org/D100727
Fangrui Song [Mon, 3 May 2021 16:04:55 +0000 (09:04 -0700)]
[ELF] Don't suggest alternative spelling of an empty name
Fix PR50111
Differential Revision: https://reviews.llvm.org/D101698
William S. Moses [Sun, 2 May 2021 02:54:23 +0000 (22:54 -0400)]
[MLIR] Canonicalize sub/add of a constant and another sub/add of a constant
Differential Revision: https://reviews.llvm.org/D101705
Anirudh Prasad [Mon, 3 May 2021 15:42:39 +0000 (11:42 -0400)]
[SystemZ][z/OS] Enforce prefix-less registers in SystemZAsmParser for the HLASM dialect.
- Previously, https://reviews.llvm.org/D101308 removed prefixes from register while printing them out. This was especially needed for inline asm statements which used input/output operands.
- However, the backend SystemZAsmParser, accepts both prefixed registers and prefix-less registers as part of its implementation
- This patch aims to change that by ensuring that prefixed registers are only allowed for the ATT dialect.
Reviewed By: uweigand
Differential Revision: https://reviews.llvm.org/D101665
Utkarsh Saxena [Mon, 3 May 2021 09:41:24 +0000 (11:41 +0200)]
[clangd] Find implementors only when index is present.
Differential Revision: https://reviews.llvm.org/D101750
Alexey Bataev [Mon, 3 May 2021 14:23:29 +0000 (07:23 -0700)]
[SLP]Allow masked gathers only if allowed by target.
Need to check if target allows/supports masked gathers before trying to
estimate its cost, otherwise we may fail to vectorize some of the
patterns because of too pessimistic cost model.
Part of D57059.
Differential Revision: https://reviews.llvm.org/D101297
Dávid Bolvanský [Mon, 3 May 2021 15:04:50 +0000 (17:04 +0200)]
[InstCombine] cttz(zext(x)) -> zext(cttz(x)) if the 'ZeroIsUndef' parameter is 'true' (PR50172)
Zext doesn't change the number of trailing zeros, so narrow cttz(zext(x)) -> zext(cttz(x)) if the 'ZeroIsUndef' parameter is 'true'.
Proofs:
https://alive2.llvm.org/ce/z/o2dnjY
Solves https://bugs.llvm.org/show_bug.cgi?id=50172
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D101582
Jon Roelofs [Thu, 29 Apr 2021 22:36:24 +0000 (15:36 -0700)]
Partial revert of "Use std::foo_t rather than std::foo in LLVM." in googlebench
Since googlebench builds as c++11, the change there is incorrect and breaks the
googlebench build when the STL implementation is strict about std::enable_if_t
not being available in lesser c++ versions.
partial revert of:
1bd6123b781120c9190b9ba58b900cdcb718cdd1 (https://reviews.llvm.org/D74384)
Differential Revision: https://reviews.llvm.org/D101583
Louis Dionne [Fri, 30 Apr 2021 22:03:17 +0000 (18:03 -0400)]
[libc++] Acquire locks on Ranges work
This commit acquires locks on a few elements of Ranges to make sure we don't
duplicate work.
Differential Revision: https://reviews.llvm.org/D101668
Saurabh Jha [Mon, 3 May 2021 13:57:31 +0000 (14:57 +0100)]
[Matrix] Remove bitcast when casting between matrices of the same size
In matrix type casts, we were doing bitcast when the matrices had the same size. This was incorrect and this patch fixes that.
Also added some new CodeGen tests for signed <-> usigned conversions
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D101754
Alexey Bataev [Mon, 3 May 2021 14:20:00 +0000 (07:20 -0700)]
Revert "[SLP]Allow masked gathers only if allowed by target."
This reverts commit
b5f64768cfeecca16c7c9c53cbd97ac7289c43aa to fix
a compiler crash revealed by buildbots.
Alexey Bataev [Mon, 26 Apr 2021 14:37:53 +0000 (07:37 -0700)]
[SLP]Allow masked gathers only if allowed by target.
Need to check if target allows/supports masked gathers before trying to
estimate its cost, otherwise we may fail to vectorize some of the
patterns because of too pessimistic cost model.
Part of D57059.
Differential Revision: https://reviews.llvm.org/D101297
Konstantin Zhuravlyov [Mon, 3 May 2021 13:44:16 +0000 (09:44 -0400)]
AMDGPU: XFAIL LLVM::note-amd-valid-v2.test for big endian
Florian Hahn [Mon, 3 May 2021 11:13:17 +0000 (12:13 +0100)]
[LV] Iterate over recipes in VPlan to fix PHI (NFC).
As we gradually move more elements of LV to VPlan, we are trying to
reduce the number of places that still has to check IR of the original
loop.
This patch adjusts the code to fix cross iteration phis to get the PHIs
to fix directly from the VPlan that is executed. We still need the
original PHI to check for first-order recurrences, but we can get rid of
that once we model that explicitly in VPlan as well.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D99293
LLVM GN Syncbot [Mon, 3 May 2021 12:53:10 +0000 (12:53 +0000)]
[gn build] Port
1527a5e4b483
Abhina Sreeskantharajan [Mon, 3 May 2021 12:49:35 +0000 (08:49 -0400)]
[SystemZ][z/OS] Add the functions needed for handling EBCDIC I/O
This patch adds the basic functions needed for controlling auto conversion on z/OS.
Auto conversion is enabled on untagged input file to ASCII by making the assumption that all untagged files are EBCDIC encoded. Output files are auto converted to EBCDIC IBM-1047.
This change also enables conversion for stdin/stdout/stderr.
For more information on how fcntl controls codepage https://www.ibm.com/docs/en/zos/2.4.0?topic=descriptions-fcntl-bpx1fct-bpx4fct-control-open-file-descriptors
Reviewed By: anirudhp
Differential Revision: https://reviews.llvm.org/D100483
Sanjay Patel [Mon, 3 May 2021 12:17:14 +0000 (08:17 -0400)]
[InstCombine] improve demanded bits analysis of left-shifted operand
If we don't demand high bits, then we also don't care about those
high bits of a left-shift operand regardless of shift amount.
I noticed the sext/trunc pattern in a motivating example.
It seems like there should be a low-bits with right-shift sibling,
but I haven't looked at that yet.
https://alive2.llvm.org/ce/z/JuS6jc
https://rise4fun.com/Alive/Trm (not sure how to use 'width' with Alive1)
https://alive2.llvm.org/ce/z/gRadbF
Differential Revision: https://reviews.llvm.org/D101489
Nathan Sidwell [Mon, 3 May 2021 12:00:26 +0000 (05:00 -0700)]
[clang] Spell correct variable
fix Trailling -> Trailing (two ll-> one l)
Differential Revision: https://reviews.llvm.org/D101753
Aaron Puchert [Mon, 3 May 2021 11:59:47 +0000 (13:59 +0200)]
Thread safety analysis: Fix false negative on break
We weren't modifying the lock set when intersecting with one coming
from a break-terminated block. This is inconsistent, since break isn't a
back edge, and it leads to false negatives with scoped locks. We usually
don't warn for those when joining locksets aren't the same, we just
silently remove locks that are not in the intersection. But not warning
and not removing them isn't right.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D101202
Aaron Puchert [Mon, 3 May 2021 11:57:44 +0000 (13:57 +0200)]
Thread safety analysis: Replace flags in FactEntry by SourceKind (NFC)
The motivation here is to make it available in the base class whether a
fact is managed or not. That would have meant three flags on the base
class, so I had a look whether we really have 8 possible combinations.
It turns out we don't: asserted and declared are obviously mutually
exclusive. Managed facts are only created when we acquire a capability
through a scoped capability. Adopting an asserted or declared lock will
not (in fact can not, because Facts are immutable) make them managed.
We probably don't want to allow adopting an asserted lock (because then
the function should probably have a release attribute, and then the
assertion is pointless), but we might at some point decide to replace a
declared fact on adoption.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D100801
Hans Wennborg [Wed, 28 Apr 2021 10:21:09 +0000 (12:21 +0200)]
[clang-cl] Add parsing support for a bunch of new flags
MSVC has added some new flags. Although they're not supported, this adds
parsing support for them so clang-cl doesn't treat them as filenames.
Except for /fsanitize=address which we do support. (clang-cl already
exposes the -fsanitize= option, but this allows using the
MSVC-spelling with a slash.)
Differential revision: https://reviews.llvm.org/D101439
Nathan Sidwell [Tue, 27 Apr 2021 19:03:40 +0000 (12:03 -0700)]
[clang] Remove libstdc++ friend template hack
this hack is for a now-unsupported version of libstdc++
Differential Revision: https://reviews.llvm.org/D101392
Muhammad Omair Javaid [Mon, 3 May 2021 10:59:30 +0000 (15:59 +0500)]
Support AArch64 PAC elf-core register read
This adds support for reading AArch64 Pointer Authentication regset
from elf-core file. Also includes a test-case for the same. Furthermore
there is also a slight refactoring of RegisterContextPOSIXCore_arm64
members and constructor. linux-aarch64-pac.core file is generated using
lldb/test/API/functionalities/postmortem/elf-core/main.c with following
clang arguments:
-march=armv8.5-a -mbranch-protection=pac-ret+leaf -nostdlib -static -g
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D99941
David Green [Mon, 3 May 2021 10:24:59 +0000 (11:24 +0100)]
[ARM] Memory operands for MVE gathers/scatters
Similarly to D101096, this makes sure that MMO operands get propagated
through from MVE gathers/scatters to the Machine Instructions. This
allows extra scheduling freedom, not forcing the instructions to act as
scheduling barriers. We create MMO's with an unknown size, specifying
that they can load from anywhere in memory, similar to the masked_gather
or X86 intrinsics.
Differential Revision: https://reviews.llvm.org/D101219
Nathan James [Mon, 3 May 2021 10:20:20 +0000 (11:20 +0100)]
[clang-tidy][NFC] Short circuit getting enum options suggestions.
Use the MaxEditDistance to skip checking candidates we know we'll skip.
Fraser Cormack [Thu, 29 Apr 2021 10:35:33 +0000 (11:35 +0100)]
[RISCV] Add support for fmin/fmax vector reductions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D101518
Benjamin Kramer [Thu, 29 Apr 2021 13:53:12 +0000 (15:53 +0200)]
[mlir] Allow lowering cmpi/cmpf with multidimensional vectors to LLVM
Differential Revision: https://reviews.llvm.org/D101535
Christian Kühnel [Mon, 3 May 2021 08:59:51 +0000 (10:59 +0200)]
[doc] typo fixes
as proposed by @FlashSheridan in
https://reviews.llvm.org/rG7f9717b922d4
Guillaume Chatelet [Mon, 3 May 2021 08:39:26 +0000 (08:39 +0000)]
[libc] warns about missing linting only in full build mode
Differential Revision: https://reviews.llvm.org/D101609
Sebastian Neubauer [Mon, 3 May 2021 08:33:11 +0000 (10:33 +0200)]
[AMDGPU] Do not annotate features for graphics
SITargetLowering::LowerFormalArguments asserts that none of these
features are used for graphics calling conventions, so
AnnotateKernelFeatures should not add them.
Differential Revision: https://reviews.llvm.org/D101534
Diana Picus [Tue, 27 Apr 2021 08:56:14 +0000 (08:56 +0000)]
[flang] Fix a bug in the character runtime
The number of bytes copied in CopyAndPad should depend on the size of
the type being copied, not on its shift value (which in the case of char
is 0, leading to no bytes at all being copied).
Add unit tests for CharacterMin and CharacterMax, which exercise this
code path.
Differential Revision: https://reviews.llvm.org/D101355
Diana Picus [Fri, 30 Apr 2021 18:22:01 +0000 (18:22 +0000)]
[flang] Fix handling of elem_len in CFI_establish
The current code computes the minimum element length based on the `type`
used to create the descriptor and uses that as the element length
whenever it is greater than 0. This means that the `elem_len` parameter
is essentially ignored for any type where we can compute a minimum
element length (which includes `CFI_type_char[16|32]_t`), and we may
therefore end up with descriptors with a lower element length than
expected.
This patch fixes the issue by explicitly doing what the standard says,
i.e. it uses the given `elem_len` for character types, `CFI_type_struct`
and `CFI_type_other`, and ignores it (falls back to the minimum element
length) for everything else.
Differential Revision: https://reviews.llvm.org/D101659
Diana Picus [Fri, 30 Apr 2021 17:21:56 +0000 (17:21 +0000)]
[flang] Use CFI_TYPE_LAST instead of CFI_type_struct
It looks like CFI_type_struct was once used as the last valid CFI_type
value, but in the meantime CFI_type_char16_t and CFI_type_char32_t were
added, making that assumption no longer true. Luckily, in the meantime
we also got a define for CFI_TYPE_LAST, which we can now use to allow
CFI_establish and CFI_allocate to work with descriptors of
CFI_type_char16_t, CFI_type_char32_t and any other future types.
Differential Revision: https://reviews.llvm.org/D101658
Nathan Ridge [Mon, 19 Apr 2021 07:25:57 +0000 (03:25 -0400)]
[clangd] Parameter hints for dependent calls
Differential Revision: https://reviews.llvm.org/D100742
Pushpinder Singh [Wed, 28 Apr 2021 06:53:46 +0000 (06:53 +0000)]
[AMDGPU][OpenMP] Enable Libomptarget runtime tests
This enables the runtime tests on amdgpu targets.
10 tests have been marked as XFAIL on amdgcn currently mostly due to
missing printf.
Reviewed By: protze.joachim
Differential Revision: https://reviews.llvm.org/D99656
Nathan Ridge [Mon, 3 May 2021 05:36:08 +0000 (01:36 -0400)]
[clangd] Fix test failure in initialize-params.test
Differential Revision: https://reviews.llvm.org/D101740
Nathan Ridge [Mon, 3 May 2021 05:18:49 +0000 (01:18 -0400)]
[clangd] Fix build error in SemanticHighlighting.cpp
Nathan Ridge [Mon, 26 Apr 2021 03:46:51 +0000 (23:46 -0400)]
[clangd] Hide inlay hints capability behind a command-line flag
Differential Revision: https://reviews.llvm.org/D101275
Nathan Ridge [Mon, 26 Apr 2021 00:01:32 +0000 (20:01 -0400)]
[clangd] Avoid including HeuristicResolver.h from ParsedAST.h
Differential Revision: https://reviews.llvm.org/D101270
Reshabh Sharma [Mon, 3 May 2021 03:31:15 +0000 (09:01 +0530)]
[ASAN][AMDGPU] Add support for accesses to global and constant addrspaces
Add address sanitizer instrumentation support for accesses to global
and constant address spaces in AMDGPU. It strictly avoids instrumenting
the stack and assumes x86 as the host.
Reviewed by: vitalybuka
Differential Revision: https://reviews.llvm.org/D99071
Konstantin Zhuravlyov [Fri, 30 Apr 2021 19:20:28 +0000 (15:20 -0400)]
Reland "AMDGPU/llvm-readobj: Add missing tests for note parsing/displaying"
This reverts commit
54aad6365951247e9f18c718c14422745b3afa4c.
Includes fix for note-amd-valid-v3.s test.
Sergio Perez Gonzalez [Mon, 3 May 2021 02:25:39 +0000 (19:25 -0700)]
[Object] Fix e_machine description for EM_CR16 and add EM_MICROBLAZE
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D101133
David Green [Sun, 2 May 2021 23:04:21 +0000 (00:04 +0100)]
[ARM] Transfer memory operands for VLDn
We create MMO's for the VLDn/VSTn intrinsics in ARMTargetLowering::
getTgtMemIntrinsic, but they do not currently make it ll the way through
ISel. This changes that in the various places it needs changing, making
sure that the MMO is propagate through to the final instruction. This
can help in scheduling, not treating the VLD2/VST2 as a scheduling
barrier.
Differential Revision: https://reviews.llvm.org/D101096
Stelios Ioannou [Fri, 30 Apr 2021 16:55:35 +0000 (17:55 +0100)]
[AArch64] Sets the preferred function alignment for Cortex-A53/A55.
Setting the preffered function alignment to 16 for Cortex A53/A55
improves performance in a wide range of benchmarks. This brings it
in line with the Cortex-A53/A55 tuning that is used in GCC
(gcc/config/aarch64/aarch64.c).
Differential Revision: https://reviews.llvm.org/D101636
Change-Id: I2ce47fe7ab5e3b54f49c89038d8da4e404742de2
Craig Topper [Sun, 2 May 2021 19:33:44 +0000 (12:33 -0700)]
[TableGen] Use sign rotated VBR for OPC_EmitInteger.
This allows for a much more efficient encoding for small negative
numbers by storing the sign bit first and negating the rest of
the bits. This was already being used for OPC_CheckInteger.
For every in tree target this affects, the table got smaller.
R600GenDAGISel.inc saw the largest reduction of 7K.
I did have to add a new opcode for StringIntegers used for
register class ids and subregister indices since we don't have the
integer value to encode. The enum name is emitted directly into
the table. Previously assumed the enum would expand to a positive
7-bit number. We might be able to just shift that right by 1 and
assume it is a positive 6 bit number, but that will need more
investigation.
Craig Topper [Sun, 2 May 2021 19:01:18 +0000 (12:01 -0700)]
[RISCV] Store SEW in RISCV vector pseudo instructions in log2 form.
This shrinks the immediate that isel table needs to emit for these
instructions. Hoping this allows me to change OPC_EmitInteger to
use a better variable length encoding for representing negative
numbers. Similar to what was done a few months ago for OPC_CheckInteger.
The alternative encoding uses less bytes for negative numbers, but
increases the number of bytes need to encode 64 which was a very
common number in the RISCV table due to SEW=64. By using Log2 this
becomes 6 and is no longer a problem.
Martin Storsjö [Sun, 2 May 2021 18:50:25 +0000 (21:50 +0300)]
[OpenMP] Fix warnings due to redundant semicolons. NFC.
Arthur Eubanks [Sun, 2 May 2021 04:44:32 +0000 (21:44 -0700)]
[NFC] Use Aliasee to determine Type and AddrSpace in GlobalAlias::create()
As opposed to going through the Aliasee type.
For opaque pointers, we're trying to remove uses of PointerType::getElementType().
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D101715
Florian Hahn [Sun, 2 May 2021 17:56:42 +0000 (18:56 +0100)]
[VPlan] Add VPBasicBlock::phis() helper (NFC).
This patch introduces a helper to obtain an iterator range for the
PHI-like recipes in a block.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D100101
Craig Topper [Sat, 1 May 2021 20:18:21 +0000 (13:18 -0700)]
[RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.
This patch makes the builtin operand order match the C operand order
for all intrinsics. With this we can use clang_builtin_alias for
all overloaded intrinsics.
This should further reduce the test time for vector intrinsics.
Differential Revision: https://reviews.llvm.org/D101700
Christopher Di Bella [Sun, 2 May 2021 17:43:05 +0000 (17:43 +0000)]
[libcxx][nfc] removes duplicate test file
`test/std/ranges/range.access/range.access.cbegin/incomplete.compile.verify.cpp`
was accidentally copied (and apparently the author either forgot to
delete it or forgot to commit the deletion).
TEST=`ninja cxx && ninja check-cxx` locally
Nikita Popov [Sun, 2 May 2021 16:12:59 +0000 (18:12 +0200)]
[SCEV] Add test for non-unit stride with multiple exits (NFC)
We currently can't determine any exit counts here, because there
is no "controlling exit".
William S. Moses [Sun, 2 May 2021 04:39:45 +0000 (00:39 -0400)]
[MLIR] Canonicalization of Integer Cast Operations
1) Canonicalize IndexCast(SExt(x)) => IndexCast(x)
2) Provide constant folds of sign_extend and truncate
Differential Revision: https://reviews.llvm.org/D101714
Mark de Wever [Sun, 2 May 2021 11:13:07 +0000 (13:13 +0200)]
[libc++][doc] Update the Format library status.
- Use the proper review for 'Fix integral conformance'.
- Mark 'Fix integral conformance' as completed.
- Move some tasks to in progress.
Juneyoung Lee [Tue, 27 Apr 2021 16:13:07 +0000 (01:13 +0900)]
[InstCombine] Add a few more patterns for folding select of select
This is a patch that folds select of select to salvage some optimizations after select -> and/or folding is disabled.
```
select (select a, true, b), c, false -> select a, c, false
select c, (select a, true, b), false -> select c, a, false
if c implies that b is false (isImpliedCondition).
```
https://alive2.llvm.org/ce/z/ANatjt, https://alive2.llvm.org/ce/z/rv8zTB
```
sel (sel c, a, false), true, (sel !c, b, false) -> sel c, a, b
sel (sel !c, a, false), true, (sel c, b, false) -> sel c, b, a
```
https://alive2.llvm.org/ce/z/U2kp-t, https://alive2.llvm.org/ce/z/bc88EE
See D101191
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D101375
Juneyoung Lee [Tue, 27 Apr 2021 16:10:12 +0000 (01:10 +0900)]
[InstCombine] Precommit tests for D101375 (NFC)
William S. Moses [Sun, 2 May 2021 04:58:06 +0000 (00:58 -0400)]
[MLIR] Handle llvm.icmp of pointers
Differential Revision: https://reviews.llvm.org/D101712
Christopher Di Bella [Sat, 24 Apr 2021 21:31:23 +0000 (21:31 +0000)]
[libcxx][nfc] prefixes test type `input_iterator` with `cpp17_`
C++20 revised the definition of what it means to be an iterator. While
all _Cpp17InputIterators_ satisfy `std::input_iterator`, the reverse
isn't true. D100271 introduces a new test adaptor to accommodate this
new definition (`cpp20_input_iterator`).
In order to help readers immediately distinguish which input iterator
adaptor is _Cpp17InputIterator_, the current `input_iterator` adaptor
has been prefixed with `cpp17_`.
Differential Revision: https://reviews.llvm.org/D101242
Juneyoung Lee [Sun, 2 May 2021 04:44:43 +0000 (13:44 +0900)]
Fix MSan crash after
1977c53b
Arthur Eubanks [Sun, 2 May 2021 04:01:06 +0000 (21:01 -0700)]
[NFC] Use getParamByValType instead of pointee type
To reduce dependence on pointee types for opaque pointers.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D101706
Juneyoung Lee [Sun, 2 May 2021 04:10:20 +0000 (13:10 +0900)]
run update_test_checks.py for the tests in D101191 (NFC)
This is an NFC that reruns update_test_checks.py on the tests that are
going to be updated in D101191.
Juneyoung Lee [Sun, 2 May 2021 04:00:33 +0000 (13:00 +0900)]
[ValueTracking] ctpop propagates poison
This is a patch that adds ctpop intrinsics to propagatesPoison.
Splitted from D101191
eopXD [Sun, 2 May 2021 02:59:12 +0000 (08:29 +0530)]
[mlir] [affine] add canonicalization for affine.vector_load, vector_store
Added canonicalization for vector_load and vector_store. An existing
pattern SimplifyAffineOp can be reused to compose maps that supplies
result into them. Added AffineVectorStoreOp and AffineVectorLoadOp
into static_assert of SimplifyAffineOp to allow operation to use it.
This fixes the bug filed: https://bugs.llvm.org/show_bug.cgi?id=50058
Reviewed By: bondhugula
Differential Revision: https://reviews.llvm.org/D101691
Juneyoung Lee [Sun, 2 May 2021 03:02:02 +0000 (12:02 +0900)]
[ValueTracking] Improve impliesPoison to look into overflow intrinsics
This update supports the following transformation:
```
select(extract(mul_with_overflow(a, _), _), (a == 0), false)
=>
and(extract(mul_with_overflow(a, _), _), (a == 0))
```
which is correct because if `a` was poison the select's condition was
also poison.
This update is splitted from D101423.
LLVM GN Syncbot [Sun, 2 May 2021 02:55:47 +0000 (02:55 +0000)]
[gn build] Port
1977c53b2ae4
Juneyoung Lee [Wed, 28 Apr 2021 02:34:45 +0000 (11:34 +0900)]
[InstCombine] Fold overflow bit of [u|s]mul.with.overflow in a poison-safe way
As discussed in D101191, this patch adds a poison-safe folding of overflow bit check:
```
%Op0 = icmp ne i4 %X, 0
%Agg = call { i4, i1 } @llvm.[us]mul.with.overflow.i4(i4 %X, i4 %Y)
%Op1 = extractvalue { i4, i1 } %Agg, 1
%ret = select i1 %Op0, i1 %Op1, i1 false
=>
%Y.fr = freeze %Y
%Agg = call { i4, i1 } @llvm.[us]mul.with.overflow.i4(i4 %X, i4 %Y.fr)
%Op1 = extractvalue { i4, i1 } %Agg, 1
%ret = %Op1
```
https://alive2.llvm.org/ce/z/zgPUGT
https://alive2.llvm.org/ce/z/h2gZ_6
Note that there are cases where inserting freeze is not necessary: e.g. %Y is `noundef`.
In this case, LLVM is already good because `%ret` is already successfully folded into `and`,
triggering the pre-existing optimization in InstSimplify: https://godbolt.org/z/v6qena15K
Differential Revision: https://reviews.llvm.org/D101423
Juneyoung Lee [Wed, 28 Apr 2021 02:25:30 +0000 (11:25 +0900)]
[InstCombine] Precommit tests for D101423 (NFC)
Yaxun (Sam) Liu [Fri, 30 Apr 2021 18:54:03 +0000 (14:54 -0400)]
[HIP] Fix device lib selection
Choose optimized device lib bitcode by fp options
for performance.
Reviewed by: Artem Belevich, Fangrui Song
Differential Revision: https://reviews.llvm.org/D101654
Fangrui Song [Sat, 1 May 2021 23:24:39 +0000 (16:24 -0700)]
[Cuda] Internalize a struct and a global variable
Harald van Dijk [Sat, 1 May 2021 21:17:04 +0000 (22:17 +0100)]
[X32][CET] Fix size and alignment of .note.gnu.property section
X32 uses 32-bit ELF object files with 32-bit alignment, so the
.note.gnu.property section needs to be emitted as it is for X86.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D101689
Nikita Popov [Sat, 1 May 2021 20:54:51 +0000 (22:54 +0200)]
[LVI] Handle mask not equal zero conditions
If V & Mask != 0, we know that at least one of the bits in Mask
must be set, so the value must be >= the lowest bit in Mask.
Nikita Popov [Sat, 1 May 2021 21:01:34 +0000 (23:01 +0200)]
[CVP] Add tests for mask not equal zero guard (NFC)
Michał Górny [Thu, 29 Apr 2021 11:55:21 +0000 (13:55 +0200)]
[lldb] [Process/FreeBSD] Fix arm64 build after RegisterInfoPOSIX_arm64 changes
Commit
88a5b35d63f927db69ec953ff487a7ba2504a610 changed the API
of RegisterInfoPOSIX_arm64 and effectively broke the FreeBSD plugin.
Update it to work with the new API.
Differential Revision: https://reviews.llvm.org/D101521
Craig Topper [Sat, 1 May 2021 20:07:28 +0000 (13:07 -0700)]
[RISCV] Add missing frontend tests for vcompress intrinsics.
Chris Lattner [Sat, 1 May 2021 19:39:01 +0000 (12:39 -0700)]
Microoptimize dominance a bit - NFC.
Don't get RegionKindInterface if we won't use it. Noticed by inspection.
Roman Lebedev [Sat, 1 May 2021 19:04:48 +0000 (22:04 +0300)]
[X86] AMD Zen 3 Scheduler Model
Introduce basic schedule model for AMD Zen 3 CPU's, a.k.a `znver3`.
This is fully built from scratch, from llvm-mca measurements
and documented reference materials.
Nothing was copied from `znver2`/`znver1`.
I believe this is in a reasonable state of completion for inclusion,
probably better than D52779 `bdver2` was :)
Namely:
* uops are pretty spot-on (at least what llvm-mca can measure)
{
F16422596}
* latency is also pretty spot-on (at least what llvm-mca can measure)
{
F16422601}
* throughput is within reason
{
F16422607}
I haven't run much benchmarks with this,
however RawSpeed benchmarks says this is beneficial:
{
F16603978}
{
F16604029}
I'll call out the obvious problems there:
* i didn't really bother with X87 instructions
* i didn't really bother with obviously-microcoded/system instructions
* There are large discrepancy in throughput for `mr` and `rm` instructions.
I'm not really sure if it's a modelling defect that needs to be fixed,
or it's a defect of measurments.
* Pipe distributions are probably bad :)
I can't do much here until AMD allows that to be fixed
by documenting the appropriate counters and updating libpfm
That being said, as @RKSimon notes:
>>! In D94395#2647381, @RKSimon wrote:
> I'll mention again that all the znver* models appear to be very inaccurate wrt SIMD/FPU instructions <...>
so how much worse this could possibly be?!
Things that aren't there:
* Various tunings: zero idioms, etc. That is follow-ups.
Differential Revision: https://reviews.llvm.org/D94395
Pratyush Das [Sat, 1 May 2021 18:47:27 +0000 (18:47 +0000)]
Fix type printing of array template args
The code example:
```
constexpr const char kEta[] = "Eta";
template <const char*, typename T> class Column {};
using quick = Column<kEta,double>;
void lookup() {
quick c1;
c1.ls();
}
```
emits error: no member named 'ls' in 'Column<&kEta, double>'. The patch fixes
the printed type name by not printing the ampersand for array types.
Differential Revision: https://reviews.llvm.org/D36368
Chris Lattner [Sat, 1 May 2021 18:42:28 +0000 (11:42 -0700)]
[Verifier] Slightly refactor code to reduce duplication, NFC.
Nikita Popov [Sat, 1 May 2021 15:40:26 +0000 (17:40 +0200)]
[SCEV] Simplify backedge count clearing (NFC)
This seems to be a leftover from when the BackedgeTakenInfo
stored multiple exit counts with manual memory management. At
some point this was switchted to a simple vector, and there should
be no need to micro-manage the clearing anymore. We can simply
drop the loop from the map and the the destructor do its job.
Nikita Popov [Sat, 1 May 2021 15:21:20 +0000 (17:21 +0200)]
[IndVars] Remove redundant loop invariance check (NFC)
This is checked again directly below this condition.
LemonBoy [Sat, 1 May 2021 15:13:50 +0000 (17:13 +0200)]
[AArch64] Prevent spilling between ldxr/stxr pairs
Apply the same logic used to check if CMPXCHG nodes should be expanded
at -O0: the register allocator may end up spilling some register in
between the atomic load/store pairs, breaking the atomicity and possibly
stalling the execution.
Fixes PR48017
Reviewed By: efriedman
Differential Revision: https://reviews.llvm.org/D101163
Nikita Popov [Sat, 1 May 2021 14:45:28 +0000 (16:45 +0200)]
[SCEV] Add tests for and/or loop guards (NFC)
LemonBoy [Sat, 1 May 2021 14:29:03 +0000 (16:29 +0200)]
[NFC][ARM] Regenerate arm64-atomic.ll test
Pre-requisite for D101163, the `NOLSE-0O` case shows registers being
spilled inside the rmw loop.
Use two separate prefixes for the `LSE-O0` case as some outputs differ
only by a comment that update_llc_test_checks.py ignores but lit does
not, causing the test to fail unexpectedly when run.
Arthur O'Dwyer [Sat, 1 May 2021 14:11:46 +0000 (10:11 -0400)]
[libc++] [test] Don't nasty-macro `__opt` yet; we actually use that one.
This reverts another of the macros just added in D101613, because it turns out
that the <optional> and <filesystem> headers use the identifier __opt.
Arthur O'Dwyer [Sat, 1 May 2021 13:09:06 +0000 (09:09 -0400)]
[libc++] [test] Don't nasty-macro `__z` yet; we actually use that one.
This reverts one of the macros just added in D101613, because it turns out
that the <utility> header actually uses the identifiers __x, __y, __z.
We probably *shouldn't* use __z if it's reserved on Windows; but since
it's not causing us any active problem even on Windows, I think this is
the safest way to unbreak the test.
Yaxun (Sam) Liu [Sun, 29 Mar 2020 14:32:03 +0000 (10:32 -0400)]
[AMDGPU] Add options -mamdgpu-ieee -mno-amdgpu-ieee
AMDGPU backend need to know whether floating point opcodes that support exception
flag gathering quiet and propagate signaling NaN inputs per IEEE754-2008, which is
conveyed by a function attribute "amdgpu-ieee". "amdgpu-ieee"="false" turns this off.
Without this function attribute backend assumes it is on for compute functions.
-mamdgpu-ieee and -mno-amdgpu-ieee are added to Clang to control this function attribute.
By default it is on. -mno-amdgpu-ieee requires -fno-honor-nans or equivalent.
Reviewed by: Matt Arsenault
Differential Revision: https://reviews.llvm.org/D77013