Eric Schweitz [Wed, 7 Sep 2022 15:40:55 +0000 (08:40 -0700)]
Removing myself from the CODE_OWNERS.TXT file as I am no longer working
on the flang project. Ownership reverts to Steve Scalpone for now.
Georg Kotheimer [Mon, 5 Sep 2022 09:14:27 +0000 (11:14 +0200)]
[clangd] Fix hover crashing on integral or enumeral casts
When pretty printing the value of an expression, we cannot infer from
the type of the expression the type of the constant that the expression
evaluates to, as the expression might contain a type cast.
Sam McCall [Wed, 7 Sep 2022 14:00:21 +0000 (16:00 +0200)]
[clangd] Improve Selection testcase, pin to C++17
17 vs 14 have different ASTs, this causes D131465 to have to touch this test.
While here, make sure we're being clear about *which* nodes we're matching.
Differential Revision: https://reviews.llvm.org/D133423
Sam McCall [Wed, 13 Jul 2022 19:11:44 +0000 (21:11 +0200)]
[Sema] Move Diags.isIgnored() checks off hot paths, it's not free. NFC
This speeds up clangd's buildAST() (i.e. parsing with a preamble) by 5% on
clangd/AST.cpp, by avoiding filling up the diagnostic state map with entries for
all the files where templates are being instantiated from.
(I would assume it has a similar effect on PCH and modules compiles).
This approach is obviously pretty fragile, and we should find ways to make
isIgnored() cheaper instead. But these changes in particular don't seem to make
the code worse in any case.
Differential Revision: https://reviews.llvm.org/D129683
Johannes Reifferscheid [Wed, 7 Sep 2022 12:35:50 +0000 (14:35 +0200)]
One-shot-bufferize: allow non-tensor arguments in scg.while/for.
Currently, one-shot-bufferize crashes as soon as there's
a mixture of tensor and non-tensor arguments. This seems
to happen for no good reason.
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D133419
Kai Sasaki [Wed, 7 Sep 2022 12:55:28 +0000 (14:55 +0200)]
[mlir][complex] Canonicalization for complex.sub adding same numbers
Canonicalization for complex.sub adding same numbers. This canonicalization supports the case like complex.sub(complex.add(a, b), b) -> a.
Reviewed By: pifon2a
Differential Revision: https://reviews.llvm.org/D133397
jacquesguan [Wed, 7 Sep 2022 12:45:57 +0000 (12:45 +0000)]
[mlir][Math] Fix RoundEven constant folder.
Use roundToIntegral instead roundeven of libm to avoid window build failed.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D133402
Sanjay Patel [Wed, 7 Sep 2022 11:53:38 +0000 (07:53 -0400)]
[InstCombine] fold add+negate through select into sub
This transform came up as a potential DAGCombine in D133282,
so I wanted to see how it escaped in IR too.
We do general folds in InstCombiner::SimplifySelectsFeedingBinaryOp()
by checking if either arm of a select simplifies when the trailing
binop is threaded into the select.
So as long as one side simplifies, it's a good fold to combine a
negate and add into 1 subtract.
This is an example with a zero arm in the select:
https://alive2.llvm.org/ce/z/Hgu_Tj
And this models the tests with a cancelling 'not' op:
https://alive2.llvm.org/ce/z/BuzVV_
Differential Revision: https://reviews.llvm.org/D133369
Sanjay Patel [Tue, 6 Sep 2022 17:24:27 +0000 (13:24 -0400)]
[InstCombine] add tests for SimplifySelectsFeedingBinaryOp(); NFC
Aaron Kogon [Wed, 7 Sep 2022 11:42:00 +0000 (07:42 -0400)]
Sink/hoist memory instructions between loop fusion candidates
Currently, instructions in the preheader of the second of two fusion
candidates are sunk and hoisted whenever possible, to try to allow the
loops to fuse. Memory instructions are skipped, and are never sunk or
hoisted. This change adds memory instructions for sinking/hoisting
consideration.
This change uses DependenceAnalysis to check if a mem inst in the
preheader of FC1 depends on an instruction in FC0's header, across
which it will be hoisted, or FC1's header, across which it will be
sunk. We reject cases where the dependency is a data hazard.
Differential Revision: https://reviews.llvm.org/D131606
Oleg Shyshkov [Wed, 7 Sep 2022 11:33:02 +0000 (13:33 +0200)]
[mlir] Change CombiningKind in Vector dialect to EnumAttr.
CombiningKind was implemented before EnumAttr, so it reimplements the same behaviour with the custom code. Except for a few places, EnumAttr is a drop-in replacement.
Reviewed By: nicolasvasilache, pifon2a
Differential Revision: https://reviews.llvm.org/D133343
Andrea Di Biagio [Wed, 7 Sep 2022 10:27:22 +0000 (11:27 +0100)]
[MCA] Correctly check pipeline availability for partially overlapping resource groups.
This patch mostly reverts commit
70b37f4c03c which fixed PR50725.
In case of explicit consumption of multiple partially overlapping group
resources, the ResourceManager was not correctly checking pipeline
esources availability.
The fix for PR50725 only partially addressed a few instances of that issue.
This is a more general (although, technically slower) fix for that same issue.
It also fixes Issue #57548
Thanks to Haohai Wen for the small reproducible.
Tom Praschan [Wed, 7 Sep 2022 10:03:55 +0000 (12:03 +0200)]
[clangd] Support renaming virtual methods
Fixes https://github.com/clangd/clangd/issues/706
Differential Revision: https://reviews.llvm.org/D132797
Simon Pilgrim [Wed, 7 Sep 2022 10:27:40 +0000 (11:27 +0100)]
[CostModel][X86] Merge getTypeBasedIntrinsicInstrCost into getIntrinsicInstrCost
For the few non type based intrinsic cases we can just check for !isTypeBasedOnly() to access the args directly.
I don't think we have a need to keep getTypeBasedIntrinsicInstrCost in BasicTTIImpl.h any more and can do a similar merge there as well - but it's a messier refactor and will take a while.
Dmitry Preobrazhensky [Wed, 7 Sep 2022 10:55:27 +0000 (13:55 +0300)]
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3 instructions
Differential Revision: https://reviews.llvm.org/D133350
Dmitry Preobrazhensky [Wed, 7 Sep 2022 10:51:31 +0000 (13:51 +0300)]
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP8 instructions
Differential Revision: https://reviews.llvm.org/D133353
Dmitry Preobrazhensky [Wed, 7 Sep 2022 10:46:38 +0000 (13:46 +0300)]
[AMDGPU][MC][GFX11][NFC] Update disassembler tests for VOP3.DPP16 instructions
Differential Revision: https://reviews.llvm.org/D133356
Nikita Popov [Wed, 7 Sep 2022 10:46:32 +0000 (12:46 +0200)]
[Bitcode] Fix constexpr autoupgrade for arrays and structs
While vectors use insertelement, structs and arrays should use
insertvalue.
Dmitry Preobrazhensky [Wed, 7 Sep 2022 10:41:44 +0000 (13:41 +0300)]
[AMDGPU][MC][GFX11][NFC] Update assembler tests for VOPD instructions
Differential Revision: https://reviews.llvm.org/D133205
Nikita Popov [Wed, 7 Sep 2022 10:28:26 +0000 (12:28 +0200)]
[Bitcode] Convert constexpr-to-instr.ll to use bitcode input (NFC)
We can't use an IR input once the relevant constant expressions
are no longer supported. Use a bitcode file instead, which will
be auto-upgraded (the whole point of this code...)
Jay Foad [Wed, 7 Sep 2022 10:16:40 +0000 (11:16 +0100)]
[AMDGPU] Add an operand folding test case from D114232
Jay Foad [Wed, 7 Sep 2022 09:49:50 +0000 (10:49 +0100)]
[AMDGPU] Refactor SIFoldOperands. NFC.
Refactor static functions into class methods so they have access to TII, MRI
etc.
Nikita Popov [Wed, 7 Sep 2022 09:40:30 +0000 (11:40 +0200)]
[ConstantFold] Avoid unary ConstantExpr::get()
Call ConstantFoldUnaryInstruction() instead, to only produce a
result if it folds.
Mehdi Amini [Mon, 29 Aug 2022 11:08:54 +0000 (11:08 +0000)]
Apply clang-tidy fixes for performance-for-range-copy in TileUsingInterface.cpp (NFC)
Mehdi Amini [Mon, 29 Aug 2022 11:06:51 +0000 (11:06 +0000)]
Apply clang-tidy fixes for llvm-qualified-auto in Bufferize.cpp (NFC)
Marco Elver [Tue, 6 Sep 2022 13:49:28 +0000 (15:49 +0200)]
[AsmPrinter] Emit PCs into requested PCSections
Interpret MD_pcsections in AsmPrinter emitting the requested metadata to
the associated sections. Functions and normal instructions are handled.
Differential Revision: https://reviews.llvm.org/D130879
Marco Elver [Tue, 6 Sep 2022 13:49:23 +0000 (15:49 +0200)]
[GlobalISel] Propagate PCSections metadata to MachineInstr
Propagate (most) PC sections metadata to MachineInstr when GlobalISel is
doing instruction selection.
This change results in support for architectures using GlobalISel (such
as -O0 with AArch64). Not all instructions may be supported yet, and
requires further target-specific handling (such as done for AArch64
pseudo-atomics). Expanding supported instructions is planned on a
case-by-case basis and new use cases for PC sections metadata.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D130886
Marco Elver [Tue, 6 Sep 2022 13:49:18 +0000 (15:49 +0200)]
[AtomicExpandPass] Always copy pcsections Metadata to expanded atomics
When expanding IR atomics to target-specific atomics, copy all
!pcsections Metadata to expanded atomics automatically.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D130885
Marco Elver [Tue, 6 Sep 2022 13:49:13 +0000 (15:49 +0200)]
[FastISel] Propagate PCSections metadata to MachineInstr
Propagate PC sections metadata to MachineInstr when FastISel is doing
instruction selection.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D130884
Nikita Popov [Wed, 7 Sep 2022 08:56:36 +0000 (10:56 +0200)]
[ConstantExpr] Don't create fneg expressions
Don't create fneg expressions unless explicitly requested by IR or
bitcode.
Marco Elver [Tue, 6 Sep 2022 13:49:08 +0000 (15:49 +0200)]
[MachineInstrBuilder] Introduce MIMetadata to simplify metadata propagation
In many places DebugLoc and PCSections metadata are just copied along to
propagate them through MachineInstrs. Simplify doing so by bundling them
up in a MIMetadata class that replaces the DebugLoc argument to most
BuildMI() variants.
The DebugLoc-only constructors allow implicit construction, so that
existing usage of `BuildMI(.., DL, ..)` works as before, and the rest of
the codebase using BuildMI() does not require changes.
NFC.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D130883
Marco Elver [Tue, 6 Sep 2022 13:49:03 +0000 (15:49 +0200)]
[SelectionDAG] Propagate PCSections through SDNodes
Add a new entry to SDNodeExtraInfo to propagate PCSections through
SelectionDAG.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D130882
Jay Foad [Mon, 5 Sep 2022 14:11:15 +0000 (15:11 +0100)]
[AMDGPU] Simplify mad/mac patterns. NFC.
Simplify instruction selection patterns for mad/mac:
- Use any_fmad consistently to make it clear that all patterns treat
fmad and AMDGPUfmad_ftz identically.
- For mad, put the patterns on the instruction definitions. For mac the
patterns are still out-of-line because we want to set AddedComplexity
and to have special handling of the source modifiers.
Differential Revision: https://reviews.llvm.org/D133305
Jay Foad [Mon, 5 Sep 2022 12:20:11 +0000 (13:20 +0100)]
[TableGen] Document sequence with stride
Document (in comments) the optional fourth "stride" argument to the
sequence operator, which was added in svn r157416.
Differential Revision: https://reviews.llvm.org/D133297
Jay Foad [Wed, 7 Sep 2022 08:56:55 +0000 (09:56 +0100)]
[AMDGPU] Add a comment for a missing fold
Nikita Popov [Wed, 7 Sep 2022 08:46:58 +0000 (10:46 +0200)]
[Reassociate] Avoid ConstantExpr::getFNeg() (NFCI)
Use ConstantFoldUnaryOpOperand() instead. Also make the code below
robust against non-instruction users, just in case it doesn't fold.
Alexander Belyaev [Wed, 7 Sep 2022 08:10:48 +0000 (10:10 +0200)]
[mlir] Remove `materializeOpFoldResult` functions.
We can use `getValueOrCreateConstantIndexOp` instead.
Differential Revision: https://reviews.llvm.org/D133403
chenglin.bi [Wed, 7 Sep 2022 08:07:26 +0000 (16:07 +0800)]
[AArch64] add tests for non-power2 int types; NFC
serge-sans-paille [Tue, 6 Sep 2022 12:22:40 +0000 (14:22 +0200)]
[clang][doc] Do not keep a copy of ClangCommandLineReference.rst in tree
This file is auto-generated, it's a bit confusing for the maintainers to have it
in tree while it shouldn't be modified *and* already have a rule to be
generated.
Differential Revision: https://reviews.llvm.org/D133349
Uday Bondhugula [Wed, 7 Sep 2022 04:39:47 +0000 (10:09 +0530)]
[MLIR] NFC. Introduce mlir::hasEffect and refactor usages dialect util
Introduce mlir::hasEffect and refactor existing usage to use utility.
NFC.
Reviewed By: rriddle, mehdi_amini
Differential Revision: https://reviews.llvm.org/D132117
Zi Xuan Wu (Zeson) [Wed, 7 Sep 2022 06:40:01 +0000 (14:40 +0800)]
[CSKY] Fix the compiling error about missing Log2 function with Log2_64
Xiang1 Zhang [Wed, 31 Aug 2022 03:16:09 +0000 (11:16 +0800)]
[X86][NFC] Refine load/store reg to StackSlot for extensibility
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D133078
Jan Ole Hüser [Wed, 7 Sep 2022 06:17:10 +0000 (09:17 +0300)]
[LLD][COFF] Fix writing a map file when range extension thunks are inserted
Bug: An assertion fails:
Assertion failed: isa<To>(Val) && "cast<Ty>() argument of incompatible type!",
file C:\Users\<user>\prog\llvm\llvm-git-lld-bug\llvm\include\llvm/Support/Casting.h, line 578
Bug is triggered, if
- a map file is requested with /MAP, and
- Architecture is ARMv7, Thumb, and
- a relative jump (branch instruction) is greater than 16 MiB (2^24)
The reason for the Bug is:
- a Thunk is created for the jump
- a Symbol for the Thunk is created
- of type `DefinedSynthetic`
- in file `Writer.cpp`
- in function `getThunk`
- the Symbol has no name
- when creating the map file, the name of the Symbol is queried
- the function `Symbol::computeName` of the base class `Symbol`
casts the `this` pointer to type `DefinedCOFF` (a derived type),
but the acutal type is `DefinedSynthetic`
- The in the llvm::cast an assertion fails
Changes:
- Modify regression test to trigger this bug
- Give the symbol pointing to the thunk a name, to fix the bug
- Add assertion, that only DefinedCOFF symbols are allowed to have an
empty name, when the constructor of the base class Symbol is executed
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D133201
Michał Górny [Tue, 6 Sep 2022 13:40:10 +0000 (15:40 +0200)]
[compiler-rt] [test] Handle missing ld.gold gracefully
Fix the is_binutils_lto_supported() function to handle missing
executables gracefully. Currently, the function does not catch
exceptions from subprocess.Popen() and therefore causes lit to crash
if config.gold_executable does not specify a valid executable:
```
lit: /usr/lib/python3.11/site-packages/lit/TestingConfig.py:136: fatal: unable to parse config file '/tmp/portage/sys-libs/compiler-rt-
15.0.0/work/compiler-rt/test/lit.common.cfg.py', traceback: Traceback (most recent call last):
File "/usr/lib/python3.11/site-packages/lit/TestingConfig.py", line 125, in load_from_path
exec(compile(data, path, 'exec'), cfg_globals, None)
File "/tmp/portage/sys-libs/compiler-rt-15.0.0/work/compiler-rt/test/lit.common.cfg.py", line 561, in <module>
if is_binutils_lto_supported():
^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/tmp/portage/sys-libs/compiler-rt-15.0.0/work/compiler-rt/test/lit.common.cfg.py", line 543, in is_binutils_lto_supported
ld_cmd = subprocess.Popen([exe, '--help'], stdout=subprocess.PIPE, env={'LANG': 'C'})
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/lib/python3.11/subprocess.py", line 1022, in __init__
self._execute_child(args, executable, preexec_fn, close_fds,
File "/usr/lib/python3.11/subprocess.py", line 1899, in _execute_child
raise child_exception_type(errno_num, err_msg, err_filename)
FileNotFoundError: [Errno 2] No such file or directory: 'GOLD_EXECUTABLE-NOTFOUND'
```
Differential Revision: https://reviews.llvm.org/D133358
Vitaly Buka [Wed, 7 Sep 2022 03:55:39 +0000 (20:55 -0700)]
[NFC][sancov] Rename ModuleSanitizerCoveragePass
Vitaly Buka [Tue, 6 Sep 2022 05:30:23 +0000 (22:30 -0700)]
[NFC][msan] Rename ModuleMemorySanitizerPass
jacquesguan [Tue, 6 Sep 2022 09:11:20 +0000 (17:11 +0800)]
[mlir][Math] Add constant folder for RoundEvenOp.
This patch uses roundeven/roundevenf of libm to fold RoundEvenOp of constant.
Differential Revision: https://reviews.llvm.org/D133344
Sinan Lin [Mon, 5 Sep 2022 14:00:00 +0000 (22:00 +0800)]
[cmake] do not set execution permission to regular files.
some regular files(e.g. files have no shebang and no execute
bit in source dir) are wrongly assigned an execution permission,
such as scanview.css and ear.c from libscanbuild, which is
unnecessary and introduces warnings in some envs.
Reviewed By: MaskRay, phosek
Differential Revision: https://reviews.llvm.org/D133308
jacquesguan [Fri, 5 Aug 2022 03:03:20 +0000 (11:03 +0800)]
[mlir][Math] Add constant folder for CosOp.
This patch adds constant folder for CosOp which only supports single and double precision floating-point.
Differential Revision: https://reviews.llvm.org/D131233
Chuanqi Xu [Wed, 7 Sep 2022 02:35:54 +0000 (10:35 +0800)]
[NFC] [Frontend] Correct the use of 'auto' in SemaCoroutine and CGCoroutine
We should only use 'auto' in case we can know the type from the right
hand side of the expression. Also we need keep '*' around if the type is
a pointer actually. Few uses of 'auto' in SemaCoroutine.cpp and
CGCoroutine.cpp violates the rule. This commit tries to fix it.
Xiang1 Zhang [Tue, 30 Aug 2022 05:58:35 +0000 (13:58 +0800)]
[CodeGen] Limit building time in CodeGenPrepare for huge function
Details:
Currently CodeGenPrepare is very time consuming in handling big functions.
Old Algorithm :
It iterate each BB in function, and go on handle very instructions in BB.
Due to some instruction optimizations may affect the BBs' dominate tree.
The old logic will re-iterate and try optimize for each BB.
Suppose we have a big function with 20000 BBs, If we handled the last BB
with fine tuning the dominate tree. We need totally re-iterate and try optimize
the 20000 BBs from the beginning.
The Complex is near N!
And we really encounter somes big tests (> 20000 BBs) that cost more than 30
mins in this pass. (Debug version compiler will cost 2 hours here)
What this patch do for huge function ?
It mainly changes the iteration way for optimization.
1 We do optimizeBlock for each BB (that is same with old way).
And, in the meaning time, If BB is changed/updated in the optimization, it will
be put into FreshBBs (try do optimizeBlock again).
The new created BB at previous iteration will also put into FreshBBs.
2 For the BBs which not updated at previous iteration, we directly skip it.
Strictly speaking, here may miss some opportunity, but the probability is very
small.
3 For Instructions in single BB, we do optimizeInst for each instruction.
If optimizeInst change the instruction dominator in this BB, rather than break
and go back to optimize the first BB (the old way), we directly iterate
instructions (to do optimizeInst) in this updated BB again (the new way).
What this patch do for small/normal (not huge) function ?
It is same with the Old Algorithm. (NFC)
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D129352
Jordan Rupprecht [Wed, 7 Sep 2022 01:59:03 +0000 (18:59 -0700)]
[test] Fix typo in setting the wrong Context test field
This manifests as an msan error because we check the value of `es`, but it's actually uninitialized because we mistakenly set `ss` twice.
Joseph Huber [Wed, 7 Sep 2022 01:31:27 +0000 (20:31 -0500)]
[CUDA] Actually fix the test correctly this time
Joseph Huber [Wed, 7 Sep 2022 01:14:20 +0000 (20:14 -0500)]
[CUDA] Fix test failing when using the new driver
Summary:
Previously the new driver crashed when using `-fsyntax-only` which
required a work-around in one of the test files. This was not properly
updated when it was fixed for the new driver. This patch fixes the test
and also adjusts a missing boolean check.
Joseph Huber [Thu, 1 Sep 2022 22:04:49 +0000 (17:04 -0500)]
[Clang] Fix the new driver crashing when using '-fsyntax-only'
The new driver currently crashses when attempting to use the
'-fsyntax-only' option. This is because the option causes all output to
be given the `TY_Nothing' type which should signal the end of the
pipeline. The new driver was not treating this correctly and attempting
to use empty input. This patch fixes the handling so we do not attempt
to continue when the input is nothing.
One concession is that we must now check when generating the arguments
for Clang if the input is of 'TY_Nothing'. This is because the new
driver will only create code if the device code is a dependency on the
host, creating the output without the dependency would require a
complete rewrite of the logic as we do not maintain any state between
calls to 'BuildOffloadingActions' so I believe this is the most
straightforward method.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D133161
natashaknk [Wed, 7 Sep 2022 00:13:12 +0000 (17:13 -0700)]
[mlir][tosa] Support non-batch dynamic dims for tosa.rescale to linalg
Reviewed By: rsuderman
Differential Revision: https://reviews.llvm.org/D133383
Richard Smith [Wed, 7 Sep 2022 00:10:55 +0000 (17:10 -0700)]
Enforce module decl-use restrictions and private header restrictions in textual headers
Per the documentation, these restrictions were intended to apply to textual headers but previously this didn't work because we decided there was no requesting module when the `#include` was in a textual header.
A `-cc1` flag is provided to restore the old behavior for transitionary purposes.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D132779
Florian Mayer [Tue, 6 Sep 2022 22:18:28 +0000 (15:18 -0700)]
[HWASan] Show memory rather than tag addresses in tag dump
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D133380
Fangrui Song [Tue, 6 Sep 2022 23:48:16 +0000 (16:48 -0700)]
[test] Remove PowerPC/aix-xcoff-exported-nondefault.ll
This is not asserted by IR verifier.
Craig Topper [Tue, 6 Sep 2022 23:03:45 +0000 (16:03 -0700)]
[RISCV] Use llvm::none_of to replace a loop. NFC
Ruobing Han [Sun, 4 Sep 2022 16:56:25 +0000 (12:56 -0400)]
[SimpleLoopUnswitch] Skip non-trivial unswitching of cold functions
In the current main branch, all cold loops will not be applied non-trivial unswitch. As reported in D129599, skipping these cold loops will incur regression in SPEC benchmark.
Thus, instead of skipping cold loops, now only skipping loops in cold functions.
Reviewed By: alexgatea, aeubanks
Differential Revision: https://reviews.llvm.org/D133275
River Riddle [Fri, 2 Sep 2022 02:31:31 +0000 (19:31 -0700)]
[mlir] Flip default value of emitAccessorPrefix to kEmitAccessorPrefix_Prefixed
Most dialects have already flipped to prefixed, and the intention to switch
has been telegraphed for a while.
Differential Revision: https://reviews.llvm.org/D133179
Vitaly Buka [Tue, 6 Sep 2022 22:42:13 +0000 (15:42 -0700)]
[test][hwasan] Update test for D132622
Vitaly Buka [Tue, 6 Sep 2022 03:31:43 +0000 (20:31 -0700)]
[pipelines] OptimizerEarlyEPCallbacks for ThinLTO prelink
Similar to OptimizerLastEPCallbacks workaround
added D96320.
Probably NFC as-is, I don't see anything hooked with this callbacks yet,
but I we are looking to move sanitizers.
Reviewed By: aeubanks, MaskRay
Differential Revision: https://reviews.llvm.org/D133333
Anastasia Stulova [Tue, 6 Sep 2022 22:07:29 +0000 (15:07 -0700)]
[mlir][tosa] Fix dynamic shape inference in conv2d
The comment in the code correctly states the equation for the shape inference as follows:
```
H = ((IH+pad_top+pad_bottom-(dilation_y*(KH-1)+1))/stride_y)+1
```
However the final operation is generated as `-` instead of `+`. I believe `+`
is indeed correct. For example if we have an image with dimension 6 and kernel
of dimension 3 (assuming padding is 0 and stride and dilation are both 1) we
are expecting 4 elements in the output (computed for image elements `(0, 1, 2)
x kernel`, `(1, 2, 3) x kernel`, `(2, 3, 4) x kernel` and `(3, 4, 5) x kernel`.
However currently only 2 elements are produced in the output.
Reviewed By: NatashaKnk
Differential Revision: https://reviews.llvm.org/D133208
Peiming Liu [Tue, 6 Sep 2022 22:25:41 +0000 (22:25 +0000)]
[mlir][tensor] Fix a typo in the example code for UnrankedTensorType
The syntax for unrank tensor type is defined as tensor-type ::= `tensor` `<` `*` `x` type `>`, the example code missed the `x` in between.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D133381
Fangrui Song [Tue, 6 Sep 2022 22:28:29 +0000 (15:28 -0700)]
[Verifier] Allow dllexport protected after D133267
I have noticed that this combo makes sense (D133266) but rejected it for
simplicity. It turns out to be used by PlayStation, so let's allow it.
Vitaly Buka [Tue, 6 Sep 2022 05:37:45 +0000 (22:37 -0700)]
[NFC][asan] Rename ModuleAddressSanitizerPass
Vitaly Buka [Tue, 6 Sep 2022 04:28:02 +0000 (21:28 -0700)]
[msan] Convert Msan to ModulePass
MemorySanitizerPass function pass violatied requirement 4 of function
pass to do not insert globals. Msan nees to insert globals for origin
tracking, and paramereters tracking.
https://llvm.org/docs/WritingAnLLVMPass.html#the-functionpass-class
Reviewed By: kstoimenov, fmayer
Differential Revision: https://reviews.llvm.org/D133336
River Riddle [Sat, 3 Sep 2022 01:52:43 +0000 (18:52 -0700)]
[mlir:vscode] Add support for loading big bytecode files
VSCode doesn't let our extension manage files >50mb. This commit
adds a proper diagnostic in this case, and also gives the user an option
to open as a temporary .mlir file instead.
Differential Revision: https://reviews.llvm.org/D133242
Arthur Eubanks [Tue, 6 Sep 2022 21:35:14 +0000 (14:35 -0700)]
[ThinLTOBitcodeWriter] Mark pass as required
Or else with -opt-bisect-limit we don't write ThinLTO bitcode.
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D133378
Craig Topper [Tue, 6 Sep 2022 21:45:17 +0000 (14:45 -0700)]
[RISCV] Add '32bit' feature to rv32 only builtins.
The backend now has a 32bit feature as part of the recent mtune
patch. We can now use that make our rv32-only builtin error checking
work the same way as rv64-only errors.
Reviewed By: kito-cheng
Differential Revision: https://reviews.llvm.org/D132192
River Riddle [Sat, 3 Sep 2022 04:23:47 +0000 (21:23 -0700)]
[mlir] Allow passing AsmState when printing Attributes and Types
This allows for extracting assembly information when printing an attribute
or type, such as the dialect resources referenced. This functionality is used in
a followup that adds resource support to the bytecode. This change also results
in a nice cleanup of AsmPrinter now that we don't need to awkwardly workaround
optional AsmStates.
Differential Revision: https://reviews.llvm.org/D132728
Krzysztof Drewniak [Tue, 6 Sep 2022 20:25:20 +0000 (20:25 +0000)]
[mlir] Improve BitEnumAttr, update documentation
- Add new operators to BitEnumAttr, mainly not (which only inverts
bits that can be valid bits for the attribute) and xor
- Add new bit enum utility functions: bitEnumClear(bits, bit) and
bitEnumSet(bits, bit, value=true) as they've come up in code I've been
writing that makes use of such enums
- Add rudimentary tests for the enum generator
- Update the OpDefinition documentation to make it contain a correct
example and to have it account for the changes mentioned above.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D133374
Simon Pilgrim [Tue, 6 Sep 2022 21:05:27 +0000 (22:05 +0100)]
[CostModel][X86] getIntrinsicInstrCost - convert to CostKindTblEntry
Begin the refactoring to use CostKindTblEntry and return real latency/codesize/sizelatency costs instead of reusing the throughput numbers
This should allow us to merge getTypeBasedIntrinsicInstrCost into getIntrinsicInstrCost and remove all remaining references
Peiming Liu [Tue, 6 Sep 2022 18:13:55 +0000 (18:13 +0000)]
[mlir][sparse] Add lowering rules for sparse_tensor.storage Op
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D133368
bzcheeseman [Fri, 2 Sep 2022 17:23:43 +0000 (10:23 -0700)]
[LLVM][Support/ADT] Add assert for isPresent to dyn_cast.
This change adds an assert to dyn_cast that the value passed-in is present. In the past, this relied on the isa_impl assertion (which still works in many cases) but which we can tighten up for a better QoI.
The PointerUnion change is because it seems like (based on the call sites) the semantics of the member dyn_cast are actually dyn_cast_if_present.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D133221
Florian Mayer [Wed, 24 Aug 2022 23:40:26 +0000 (16:40 -0700)]
[HWASan] rename left/right to before/after.
left/right is a weird way to refer to address ordering.
Reviewed By: eugenis, vitalybuka
Differential Revision: https://reviews.llvm.org/D132622
Aaron Ballman [Tue, 6 Sep 2022 20:47:40 +0000 (16:47 -0400)]
Fix the Clang sphinx build bot; NFC
This should address the failure introduced in:
https://lab.llvm.org/buildbot/#/builders/92/builds/32377
raghavmedicherla [Tue, 6 Sep 2022 20:41:00 +0000 (16:41 -0400)]
[AMDGPU/Metadata] Rename HSAMD::MetadataStreamer classes
Renamed all HSAMD::MetadataStreamer classes to improve readability of the code.
Differential Revision: https://reviews.llvm.org/D133156
raghavmedicherla [Tue, 6 Sep 2022 18:45:25 +0000 (14:45 -0400)]
Support: Add mapped_file_region::sync(), equivalent to msync
Add mapped_file_region::sync(), equivalent to POSIX msync,
synchronizing written content to disk without unmapping the region.
Asserts if the mode is not mapped_file_region::readwrite.
Note that I don't have access to a Windows machine, so I can't
easily run those unit tests.
Change by dexonsmith
Differential Revision: https://reviews.llvm.org/D95494
Vitaly Buka [Tue, 6 Sep 2022 20:42:57 +0000 (13:42 -0700)]
[test][libcxx] Mark ubsan test as UNSUPPORTED
It inconsistently fails on bots.
Florian Mayer [Tue, 6 Sep 2022 20:37:35 +0000 (13:37 -0700)]
[ASan] Fix libfuzzer test
Philip Reames [Tue, 6 Sep 2022 20:35:39 +0000 (13:35 -0700)]
[docs][RISCV] Document status of Zicpo(m,p,z) extensions
Unless I missed something when checking, we only support these in assembly. Given that, documenting them is a good opportunity to define support levels which will be useful for other extensions as well.
Differential Revision: https://reviews.llvm.org/D133372
Alexander Shaposhnikov [Tue, 6 Sep 2022 20:28:17 +0000 (20:28 +0000)]
[AArch64] Increase AddedComplexity of BIC
This diff adjusts AddedComplexity of BIC to bump its position
in the list of patterns to make LLVM pick it instead of MVN + AND.
MVN + AND requires 2 cycles, so does e.g. MOV + BIC, but the latter
outperforms the former if the instructions producing the operands of
BIC can be issued in parallel.
One may consider the following example:
ldur x15, [x0, #2] # 4 cycles
mvn x10, x15 # 1 cycle (depends on ldur)
and x9, x10, #0x8080808080808080
vs.
ldur x15, [x0, #2] # 4 cycles
mov x9, #0x8080808080808080 # 1 cycle (can be executed in parallel with ldur)
bic x9, x9, x15. # 1 cycle
Test plan: ninja check-all
Differential revision: https://reviews.llvm.org/D133345
Joseph Huber [Tue, 6 Sep 2022 20:25:32 +0000 (15:25 -0500)]
[Libomptarget][NFC] Clean up CUDA plugin and address warnings
Simon Pilgrim [Tue, 6 Sep 2022 20:27:46 +0000 (21:27 +0100)]
[CostModel][X86] Fix check prefixes on cttz cost kinds tests
Add missing SSE2 + BMI/NOBMI coverage
Florian Mayer [Wed, 24 Aug 2022 21:30:14 +0000 (14:30 -0700)]
[ASan] rename left/right to before/after.
left/right is a weird way to refer to address ordering.
Reviewed By: eugenis, MaskRay
Differential Revision: https://reviews.llvm.org/D132611
Jim Ingham [Tue, 6 Sep 2022 20:24:21 +0000 (13:24 -0700)]
Fix another place were we suggest lldb.target in a Frame Recognizer.
Jim Ingham [Tue, 6 Sep 2022 20:20:03 +0000 (13:20 -0700)]
You can't use lldb.target in a frame recognizer.
Alexander Shaposhnikov [Tue, 6 Sep 2022 20:19:47 +0000 (20:19 +0000)]
[clang-tidy] Skip union-like classes in use-equals-default
Skip unions/union-like classes since in this case constructors
with empty bodies behave differently in comparison with regular
structs/classes.
Test plan: ninja check-clang-tools
Differential revision: https://reviews.llvm.org/D132713
Vitaly Buka [Sun, 4 Sep 2022 05:24:33 +0000 (22:24 -0700)]
[tsan] Replace mem intrinsics with calls to interceptors
After https://reviews.llvm.org/rG463aa814182a23 tsan replaces llvm
intrinsics with calls to glibc functions. However this approach is
fragile, as slight changes in pipeline can return llvm intrinsics back.
In particular InstCombine can do that.
Msan/Asan already declare own version of these memory
functions for the similar purpose.
KCSAN, or anything that uses something else than compiler-rt, needs to
implement this callbacks.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D133268
Vitaly Buka [Tue, 6 Sep 2022 20:00:57 +0000 (13:00 -0700)]
[tsan][go] Fix buildgo.sh when GOAMD64 undefined
Chenguang Wang [Tue, 6 Sep 2022 19:28:23 +0000 (21:28 +0200)]
[mlir] Fix DenseElementsAttr::mapValues(i1, splat).
Splat of bool is encoded as a byte with all-ones in it [1]. Without this
change, this piece of code:
auto xs = builder.getI32TensorAttr({42, 42, 42, 42});
auto xs2 = xs.mapValues(builder.getI1Type(), [](const llvm::APInt &x) {
return x.isZero() ? llvm::APInt::getZero(1) : llvm::APInt::getAllOnes(1);
});
xs2.dump();
Prints:
dense<[true, false, false, false]> : tensor<4xi1>
Because only the first bit is set. This applies to both
DenseIntElementsAttr::mapValues() and DenseFPElementsAttr::mapValues().
[1]: https://github.com/llvm/llvm-project/blob/
e877b42e2c70813352c1963ea33e992f481d5cba/mlir/lib/IR/BuiltinAttributes.cpp#L984
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D132767
Philip Reames [Tue, 6 Sep 2022 19:06:53 +0000 (12:06 -0700)]
[docs] Add a RISC-V Usage page
This follows the pattern set by e.g. SPIR-V, AMDGPU, and WebAssembly.
For the moment, this page is fairly minimal stub. I mostly want a place to record which extensions we support, and when that support is not complete, a central place to note that. I'm deliberately starting with a subset of extensions which are pretty straight forward with only one case needing a detail note.
I figure the partial support cases are going to need a bunch of discussion, and having each of them in their own review seemed worthwhile. Similarly, the experimental extensions probably fall into the same bucket of triggering a bunch of review discussion.
Differential Revision: https://reviews.llvm.org/D133063
Roy Jacobson [Tue, 6 Sep 2022 18:59:27 +0000 (21:59 +0300)]
[DOC][Clang] Update cxx_status.html after the 15 release and fix a broken link in release notes
Joseph Huber [Tue, 6 Sep 2022 18:56:24 +0000 (13:56 -0500)]
[OpenMP] Fix logic error when building offloading applications
Summary:
A previous patch removed support for the `-fopenmp-new-driver` and
accidentally used the `isHostOffloading` flag instead of
`isDeviceOffloading` which lead to some build errors when compiling for
the offloading device. This patch addresses that.
Joseph Huber [Tue, 6 Sep 2022 17:51:43 +0000 (12:51 -0500)]
[OpenMP] Remove use of removed '-f[no-]openmp-new-driver' flag
The changes in D130020 removed all support for the old method of
compiling OpenMP offloading programs. This means that
`-fopenmp-new-driver` has no effect and `-fno-openmp-new-driver` does
not work. This patch removes the use and documentation of this flag.
Note that the `--offload-new-driver` flag still exists for using the new
driver optionally with CUDA and HIP.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D133367
Markus Böck [Tue, 6 Sep 2022 18:20:40 +0000 (20:20 +0200)]
[MC] Emit Stackmaps before debug info
This patch is essentially an alternative to https://reviews.llvm.org/D75836 and was mentioned by @lhames in a comment.
The gist of the issue is that Mach-O has restrictions on which kind of sections are allowed after debug info has been emitted, which is also properly asserted within LLVM. Problem is that stack maps are currently emitted as one of the last sections in each target-specific AsmPrinter so far, which would cause the assertion to trigger. The current approach of special casing for the `__LLVM_STACKMAPS` section is not viable either, as downstream users can overwrite the stackmap format using plugins, which may want to use different sections.
This patch fixes the issue by emitting the stack map earlier, right before debug info is emitted. The way this is implemented is by taking the choice when to emit the StackMap away from the target AsmPrinter and doing so in the base class. The only disadvantage of this approach is that the `StackMaps` member is now part of the base class, even for targets that do not support them. This is functionaly not a problem however, as emitting an empty `StackMaps` is a no-op.
Differential Revision: https://reviews.llvm.org/D132708
Joseph Huber [Tue, 6 Sep 2022 15:22:25 +0000 (10:22 -0500)]
[OpenMP] Fix `omp_get_wtime` function being marked incorrectly as readonly
OpenMP has a list of of optimistic attributes that can be attached to
known runtime functions to aid some analysis. The `omp_get_wtime`
function incorrectly used the `readonly` attribute. This is not correct
at the `omp_get_wtime` function changes values depending on some
external state. This is more correctly modeled with
`inaccessiblememonly` meaning that the value does not depend on anything
within the module, but can not be removes as it depends on external
state.
Fixes #57578
Reviewed By: tianshilei1992
Differential Revision: https://reviews.llvm.org/D133360