Zhao Qiang [Fri, 5 Feb 2016 02:04:19 +0000 (10:04 +0800)]
board: ls1043ardb: Modify pin-muxing code for USB and QE-HDLC
QE-HDLC and USB multi-use the pins, modify the pin-muxing code
for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins
to QE-HDLC, if not, assgin it to USB
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Zhao Qiang [Fri, 5 Feb 2016 02:04:18 +0000 (10:04 +0800)]
board: ls1043rdb: Move USB muxing config to config_board_mux
Pin-muxing code should be in config_board_mux, move USB muxing
config to config_board_mux.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Zhao Qiang [Fri, 5 Feb 2016 02:04:17 +0000 (10:04 +0800)]
board: ls1043ardb: Add micro QE support for ls1043ardb
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Zhao Qiang [Fri, 5 Feb 2016 02:04:16 +0000 (10:04 +0800)]
driver: qe: Mask the codes not used for micro QE
there are some code in qe.c not used for micro QE,
use "#ifdef CONFIG_QE" to mask them.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Tue, 16 Feb 2016 05:12:53 +0000 (13:12 +0800)]
armv8/ls1043aqds: Add USB support for ls1043aqds
Add USB XHCI support for ls1043qds board.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Thu, 18 Feb 2016 05:02:02 +0000 (13:02 +0800)]
armv8/fsl-layerscape: fdt: add fixup for Fman ucode
Add fdt fixup to insert Fman firmware into the device tree.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Thu, 18 Feb 2016 05:02:01 +0000 (13:02 +0800)]
driver/fm: fdt.c: fix fdt_fixup_fman_firmware() to support ARM platforms
Use fdt32_to_cpu() to convert the data correctly for both endianness
platforms.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Thu, 18 Feb 2016 05:02:00 +0000 (13:02 +0800)]
fm: fdt: Move fman ucode fixup to driver code
Not only powerpc/mpc85xx but also Freescale Layerscape platforms will
use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device
tree. So move the function to Fman driver code.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Qianyu Gong [Thu, 18 Feb 2016 05:01:59 +0000 (13:01 +0800)]
qe: move drivers/qe/qe.h to include/fsl_qe.h
As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha [Wed, 3 Feb 2016 11:34:07 +0000 (17:04 +0530)]
armv8: ls2080: Update bootcmd env variable
Before Linux boot DPL must be deployed to DPAA2 interface.
So update bootcmd env variable to make sure DPL deployment before
Linux boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Prabhakar Kushwaha [Wed, 3 Feb 2016 11:33:51 +0000 (17:03 +0530)]
armv8: ls2080: Add mcinitcmd env variable in default env
Define mcinitcmd env variable to load Management complex during
u-boot boot sequence.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Alison Wang [Tue, 2 Feb 2016 07:16:23 +0000 (15:16 +0800)]
arm: ls1021a: Add QSPI or IFC support in SD boot for LS1021AQDS board
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported
in SD boot now. For the customer's demand, QSPI needs to be supported
in SD boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig
is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig
is used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Mingkai Hu [Tue, 2 Feb 2016 03:28:03 +0000 (11:28 +0800)]
armv8/ls1043a: Implement workaround for erratum A009660
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Shengzhou Liu [Fri, 29 Jan 2016 08:56:01 +0000 (16:56 +0800)]
armv8/ls1043a: enable workaround for errarum A009942
DDR erratum A-009942 applies to LS1043A.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Aneesh Bansal [Fri, 22 Jan 2016 11:35:59 +0000 (17:05 +0530)]
powerpc/SECURE_BOOT: Add PAMU driver
PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.
The patch reverts commit
7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ruchika Gupta [Fri, 22 Jan 2016 10:42:55 +0000 (16:12 +0530)]
drivers/crypto/fsl : Allocate output ring with size aligned to CACHELNE SIZE
The output ring needs to be invalidated before enqueuing the job to SEC.
While allocation of space to output ring, it should be taken care that the
size is cacheline size aligned inorder to prevent invalidating valid data.
The patch also correct the method of aligning end of structs while flushing caches
Since start = align(start_of_struct), it is incorrect to assign
end = align(start + struct_size). It should instead be,
end = align(start_of_struct + struct_size).
Signed-off-by: Saksham Jain <saksham@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Ashish Kumar [Thu, 14 Jan 2016 12:42:29 +0000 (18:12 +0530)]
armv8: ls2080a: Increase default hugepage count
Increase default hugepage count to 256 from 16
Signed-off-by: Ashish Kumar <Ashish.Kumar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Mon, 8 Feb 2016 21:47:29 +0000 (13:47 -0800)]
arm: ls1021aqds: Enable driver model lpuart serial driver
Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart
to driver model suport. Enable lpuart port driver.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
York Sun [Mon, 8 Feb 2016 21:04:17 +0000 (13:04 -0800)]
arm: ls1021aqds: Convert to driver model and enable serial support
Split duart configuration as device tree file. Move /chosen node
out of board commone device tree. Convert ls1021aqds nor and SD
configurations to driver model support (qspi already uses DM).
Enable ns16550 DM serial driver for nor configurations.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Tom Rini [Sun, 21 Feb 2016 12:56:16 +0000 (07:56 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Peng Fan [Thu, 28 Jan 2016 08:55:09 +0000 (16:55 +0800)]
imx: mx7d: isolate resources to domain 0 for A7 core
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.
This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:08 +0000 (16:55 +0800)]
imx: mx7dsabresd: add command and macros for boot m4 core
Introduce macros and command to support booting M4 core for
i.MX7D SabreSD board.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:07 +0000 (16:55 +0800)]
imx: mx7: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:06 +0000 (16:55 +0800)]
imx: mx6sxsabresd: add command and macros for boot m4 core
Introduce macros and command to support booting M4 core for
i.MX6SX SabreSD board.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:05 +0000 (16:55 +0800)]
imx: mx6: implement functions to boot auxiliary core
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:04 +0000 (16:55 +0800)]
imx: imx-common: introduce boot auxiliary core
To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".
Introduce Kconfig option IMX_BOOTAUX.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:03 +0000 (16:55 +0800)]
imx: mx7d: clock support for RDC
If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:02 +0000 (16:55 +0800)]
imx: mx7d: Add RDC support
Add the peripherals/masters definitions and registers base addresses
for mx7d RDC.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:01 +0000 (16:55 +0800)]
imx: mx6sx Add RDC mappings of masters and peripherals
Add the definitions for the RDC mappings for i.MX6 SoloX.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:55:00 +0000 (16:55 +0800)]
imx: imx-common: introduce Resource Domain Controller support
Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 28 Jan 2016 08:54:59 +0000 (16:54 +0800)]
imx: mx6: introduce rdc regs
Introudce rdc regs structure and rdc sema reg structure for i.MX6.
For now, to i.MX6, only i.MX6SX supports this.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Julien CORJON [Fri, 5 Feb 2016 15:19:33 +0000 (16:19 +0100)]
imx: mx6quq7: add sd card detection
Add board_mmc_getcd function and declare CD_GPIO for SDCard.
Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
Julien CORJON [Fri, 5 Feb 2016 15:19:32 +0000 (16:19 +0100)]
imx: mx6quq7: specify max_bus_witdh directly in usdhc_cfg
Specify max_bus_width directly in usdhc_cfg static definition instead
of tweaking it in the board_mmc_init() function.
Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
Julien CORJON [Fri, 5 Feb 2016 15:19:31 +0000 (16:19 +0100)]
imx: mx6quq7: fix USDHC4 declaration
USDHC2 does not exist on mx6quq7 board, as USDHC4 was already been
declared this is probably a typo.
Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Soeren Moch [Thu, 4 Feb 2016 13:41:16 +0000 (14:41 +0100)]
board: tbs2910: Autoselect environment device when booting from SD
Implement board specific functions to select the environment device and
partition when booting from SD/MMC.
SD2: mmc 0 0
SD3: mmc 1 0
eMMC: mmc 2 1
Signed-off-by: Soeren Moch <smoch@web.de>
Soeren Moch [Thu, 4 Feb 2016 13:41:15 +0000 (14:41 +0100)]
imx: mx6: Implement mmc_get_env_part
commit
216d286c7e3d3d83d4d8ccaf0415192e1b1040c0 [imx: mx6: implement
mmc_get_env_dev] introduced selection of the environment device according
to the boot device when booting from SD/MMC.
Extend this functionality for also selecting the device partition.
Signed-off-by: Soeren Moch <smoch@web.de>
Peng Fan [Wed, 3 Feb 2016 02:06:08 +0000 (10:06 +0800)]
pinctrl: imx: Support i.MX7D
Introudce i.MX7 pinctrl driver support.
For now only i.MX7D supported.
There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr.
To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg
and conf_reg can begin at 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Peng Fan [Wed, 3 Feb 2016 02:06:07 +0000 (10:06 +0800)]
pinctrl: imx: Introduce pinctrl driver for i.MX6
Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
pinctrl-names = "default";
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
>;
};
[.....]
};
there is no property named function or groups. So pinctrl_generic_set_state
can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
"
set_state_simple op missing
imx_pinctrl_set_state: i2c1grp
mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x14c val 0x10
select_input: offset 0x5d8 val 0x1
write config: offset 0x3bc val 0x7f
mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x148 val 0x10
select_input: offset 0x5d4 val 0x1
write config: offset 0x3b8 val 0x7f
"
this means imx6 pinctrl driver works as expected.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ulises Cardenas [Tue, 2 Feb 2016 10:39:39 +0000 (04:39 -0600)]
imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7
Refactored data structure for CAAM's job ring and Secure Memory
to support i.MX7.
The new memory map use macros to resolve SM's offset by version.
This will solve the versioning issue caused by the new version of
secure memory of i.MX7
Signed-off-by: Ulises Cardenas <raul.casas@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Wed, 17 Feb 2016 15:34:22 +0000 (13:34 -0200)]
mx7dsabresd: Make 'ums' command functional
When running the 'ums' command we get:
=> ums 0 mmc 0
UMS: disk start sector: 0x0, count: 0xe18000
g_dnl_register: failed!, error: -22
ERROR: g_dnl_register failed
at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage()
Fix this by initializing USB OTG1 port as USB device mode instead of host.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Wed, 17 Feb 2016 15:37:13 +0000 (13:37 -0200)]
mx7dsabresd: Use Adrian's NXP email address
Use the new NXP email address for the board maintainer.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Wed, 17 Feb 2016 19:32:14 +0000 (17:32 -0200)]
mx6ul_14x14_evk: Select CONFIG_FSL_QSPI
Select CONFIG_FSL_QSPI so that the SPI can be probed:
=> sf probe
SF: Detected N25Q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Andreas Bießmann [Tue, 16 Feb 2016 22:29:29 +0000 (23:29 +0100)]
mxsboot: remove unused include
Commit
276d3ebb883024d753cd9c69ab2fd243ffa1262e removed htole32() but missed
to remove the corresponding header. This is annoying, since BSD systems do not
have endian.h.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Michael Heimpold <mhei@heimpold.de>
Bin Meng [Wed, 17 Feb 2016 08:47:04 +0000 (00:47 -0800)]
x86: doc: Update to include Intel Bayley Bay board instructions
Update existing documentation to mention Intel Bayley Bay board
instructions, an additional Bay Trail based board to MinnowMax.
This also adds a minor change to QEMU section to indicate clearly
the instructions are for bare mode.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:25 +0000 (00:16 -0800)]
x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:24 +0000 (00:16 -0800)]
x86: ivybridge: bd82x6x: Support FSP enabled configuration
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:23 +0000 (00:16 -0800)]
x86: fsp: Make sure HOB list is not overwritten by U-Boot
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.
To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:22 +0000 (00:16 -0800)]
superio: Add SMSC SIO1007 driver
The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.
This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Feb 2016 08:16:21 +0000 (00:16 -0800)]
x86: ivybridge: Add FSP support
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
Stephen Warren [Fri, 12 Feb 2016 21:27:56 +0000 (14:27 -0700)]
x86: fix memalign() parameter order
Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)
Fixes:
45b5a37836d5 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Sat, 20 Feb 2016 22:32:48 +0000 (17:32 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-atmel
Andreas Bießmann [Sat, 20 Feb 2016 20:39:36 +0000 (21:39 +0100)]
vinco: add Maintainers file
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Alexey Brodkin [Mon, 14 Dec 2015 14:15:13 +0000 (17:15 +0300)]
arc: cache - utilize IO coherency (AKA IOC) engine
With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.
With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Alexey Brodkin [Mon, 14 Dec 2015 14:14:46 +0000 (17:14 +0300)]
arc: cache - accommodate different L1 cache line lengths
ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.
Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.
With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Guillaume GARDET [Thu, 18 Feb 2016 17:17:36 +0000 (18:17 +0100)]
spl: if MMCSD_MODE_RAW fails, try MMCSD_MODE_FS
Since commit
fd61d39970b9901217efc7536d9f3a61b4e1752a:
spl: mmc: add break statements in spl_mmc_load_image()
RAW and FS boot modes are now exclusive again. So, if MMCSD_MODE_RAW fails, the
board hangs. This patch allows to try MMCSD_MODE_FS then.
It has been tested on a beaglebone black to boot on an EXT partition.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@konsulko.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
Tom Rini [Fri, 19 Feb 2016 14:25:09 +0000 (09:25 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-tegra
Gregory CLEMENT [Wed, 16 Dec 2015 16:01:44 +0000 (17:01 +0100)]
ARM: Add Support for the VInCo platform
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[rebase on current TOT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Samuel Mescoff [Tue, 16 Feb 2016 08:45:06 +0000 (09:45 +0100)]
ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit
b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Thu, 11 Feb 2016 13:13:38 +0000 (14:13 +0100)]
arm: at91: Add support for DENX MA5D4 SoM and EVK
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the
Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI
CAN controllers and DRAM, the baseboard contains UART connectors,
ethernet port, microSD slot, LCD header, 2x CAN connector and a
lot of expansion headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Matthias Michel [Wed, 27 Jan 2016 14:56:07 +0000 (15:56 +0100)]
siemens,at91: enable features for smartweb
New features for smartweb:
* switch to hush command parser
* change autoboot stop to <ESC><ESC>
* allow to write ethaddr
Signed-off-by: Matthias Michel <matthias.michel@siemens.com>
Reviewed-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 04:46:14 +0000 (12:46 +0800)]
board: atmel: clean up the PMC_PLLICPR init code
Due to introducing the PMC_PLLICPR init function, use this
function to clean up the code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 04:46:13 +0000 (12:46 +0800)]
ARM: at91: clean up the PMC_PLLICPR init code
Due to introducing the PMC_PLLICPR init function, use this
function to clean up the code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 04:46:12 +0000 (12:46 +0800)]
ARM: at91: clock: add PMC_PLLICPR init function
To avoid the duplicated code, add the PMC_PLLICPR init function.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:20:45 +0000 (10:20 +0800)]
board: atmel: siemens: clean up PLLB code
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Wenyou Yang [Wed, 3 Feb 2016 02:20:44 +0000 (10:20 +0800)]
drivers: usb: ohci-at91: clean up the PLLB code
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable/disable code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Wenyou Yang [Wed, 3 Feb 2016 02:20:43 +0000 (10:20 +0800)]
ARM: at91: clock: add PLLB enable/disable functions
To avoid the duplicated code, add the PLLB handle functions.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
[add enable/disable functions to arm920t]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:54 +0000 (11:11 +0800)]
board: atmel: siemens: clean up UTMI PLL code
Due to introducing the new UTMI PLL clock handle functions,
use the functions to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:53 +0000 (11:11 +0800)]
drivers: usb: atmel: clean up the UTMI PLL code
Due to introducing the new UTMI PLL clock handle functions,
use these function to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:52 +0000 (11:11 +0800)]
ARM: at91: armv7: clean up UTMI PLL handle code
Due to introducing the UTMI PLL enable function, use this function
to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Tue, 2 Feb 2016 03:11:51 +0000 (11:11 +0800)]
ARM: at91: clock: add UTMI PLL enable/disable function
To avoid the duplicated code, add the UTMI PLL handle functions,
and add PMC_USB init function too.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:51 +0000 (10:16 +0800)]
drivers: at91: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
[fixup for missing clk.h in at91_emac.c]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:50 +0000 (10:16 +0800)]
board: atmel: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to reduce duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
[Rebased on current master, fixup for at91rm9200ek]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:49 +0000 (10:16 +0800)]
ARM: cpu: at91: clean up peripheral clock code
Due to introducing the new peripheral clock handle functions,
use these functions to clean up the duplicated code.
Meanwhile, remove unneeded header file include, at91_pmc.h.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
[fixup for arm920t code]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:48 +0000 (10:16 +0800)]
ARM: at91: clock: add a new file to handle clock
To reduce the duplicated code, add a new file to accommodate
the peripheral's and system's clock handle code, shared with
the SoCs with different ARM core.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Wed, 3 Feb 2016 02:16:47 +0000 (10:16 +0800)]
ARM: at91: asm/at91_pmc.h: fix trival register offset
Remove unnecessary #ifdef CPU_HAS_PCR.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Stefan Roese [Wed, 10 Feb 2016 06:06:06 +0000 (07:06 +0100)]
net: phy: marvell: Fix problem with phy_reset() clearing BMCR
With commit
a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.
At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.
Tested on clearfog.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stefan Roese [Wed, 10 Feb 2016 06:06:05 +0000 (07:06 +0100)]
net: phy: marvell: Call phy_reset() where possible
Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Hao Zhang <hzhang@ti.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Stephen Warren [Mon, 15 Feb 2016 17:34:04 +0000 (10:34 -0700)]
ARM: tegra: enable USB device mode port on Dalmore
This allows U-Boot to expose UMS and DFU protocols on this port in device
mode, or to act as a USB host on the port, using an "OTG" (micro-B to
female A host) cable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 15 Feb 2016 17:34:03 +0000 (10:34 -0700)]
ARM: tegra: don't set CONFIG_USB_MAX_CONTROLLER_COUNT
This option is no longer used now that DM_USB is enabled.
Fixes:
534f9d3feffd ("dm: tegra: usb: Move USB to driver model")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Wed, 17 Feb 2016 01:09:19 +0000 (18:09 -0700)]
video: tegra: Correct a Kconfig warning with VIDCONSOLE_AS_LCD
This new feature causes a Kconfig warning on boards without a display
enabled. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:38:02 +0000 (16:38 -0700)]
tegra: video: Clean up the old LCD/PWM driver code
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we
are using driver model for video.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:38:01 +0000 (16:38 -0700)]
tegra: video: Move LCD driver to use the DM PWM driver
Use the driver-model PWM driver in preference to the old code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:38:00 +0000 (16:38 -0700)]
tegra: Convert CONFIG_PWM_TEGRA to Kconfig
Move this option to Kconfig and clean up the header files. Adjust the only
user (the LCD driver) to work with the new driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:59 +0000 (16:37 -0700)]
tegra: video: Move all fdt-decoding into a single function
Join the two functions which decode the device tree and put them in the
ofdata_to_platdata() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:58 +0000 (16:37 -0700)]
tegra: video: Move LCD enums into the driver
There is no need to have these in a separate file as they are not
referenced from anywhere else.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:57 +0000 (16:37 -0700)]
tegra: video: Remove the static variables
We can move the static variables into the driver-private data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:56 +0000 (16:37 -0700)]
tegra: video: Convert tegra20 LCD driver to driver model
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.
Boards which use this are fixed up, but only seaboard is tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:55 +0000 (16:37 -0700)]
tegra: video: Merge the two config structures together
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:54 +0000 (16:37 -0700)]
tegra: video: Move the check for CONFIG_OF_CONTROL to Kconfig
We can check this in Kconfig now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:53 +0000 (16:37 -0700)]
tegra: video: Merge the display driver into one file
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.
Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:52 +0000 (16:37 -0700)]
tegra: dts: Sync tegra20.dtsi with Linux v4.4
This file has changed quite a bit since it was set up. Sync it back with
Linux v4.4. Adjust the users slightly to cope with the changes:
- the host1x node is now called host1x@
50000000
- we need a clocks node to provide the clk32k_in phandle
- active usb nodes need status = "okay"
- active i2c nodes need status = "okay"
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:51 +0000 (16:37 -0700)]
tegra: video: Rename CONFIG_VIDEO_TEGRA to CONFIG_VIDEO_TEGRA20
This option refers only to the tegra20 video driver, so name it as such
to avoid confusion with tegra124.
Also move this option to Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:50 +0000 (16:37 -0700)]
tegra: nyan-big: Move the LCD driver to driver model
Adjust the driver to use driver model. The SOR becomes a bridge device. We
use the normal simple_panel driver to handle the display itself. We also
need to enable some options such as regulators, PWMs and DM_VIDEO itself.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:49 +0000 (16:37 -0700)]
tegra: Allow CONFIG_DM_VIDEO to be used as well as CONFIG_LCD
While we transition to using driver model for video, we need to support both
options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:48 +0000 (16:37 -0700)]
tegra: Allow driver model to be used for the PWM
We can skip this manual init when using driver model for the PWM.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:47 +0000 (16:37 -0700)]
tegra: lcd: Merge tegra124-lcd.c into display.c
There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:46 +0000 (16:37 -0700)]
tegra: pwm: Add a driver for the tegra PWM
This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:45 +0000 (16:37 -0700)]
tegra: gpio: Show the GPIO value for outputs
The tegra GPIO controller has two ways of reading the value of a GPIO. It
can supply the 'input' value (which is the value read from the pin) and the
'output' value (which is the value being driven from the pin. With a GPIO
set to output mode, the 'input' value is always low which is not very
useful.
This has the unfortunate result that setting a GPIO high still leaves it
showing as low in the 'gpio status' command.
Adjust the driver to check which direction the GPIO is set to, then read
the value from the appropriate register: 'input' for input GPIOs, 'output'
for output GPIOs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:44 +0000 (16:37 -0700)]
tegra: dts: Sync up nyan-big files with Linux
Sync up these files with Linux v4.4. Some differences remain, principally
that the addresses are still 32-bit in U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sat, 30 Jan 2016 23:37:43 +0000 (16:37 -0700)]
tegra: dts: Sync up the tegra124 device tree files with Linux
Sync up these files with Linux v4.4.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>