radv: add segregated fit shader memory allocator

Way faster than the previous one, especially with a large number of
shaders.

This doesn't have much of an effect right now, but the previous allocator
was expensive compared to the cost of compiling vertex shader prologs.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>

radv: add radv_shader_variant_get_va and radv_find_shader_variant helpers

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>

radv: add radv_translate_vertex_format()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>

radv: add and use radv_vs_input_alpha_adjust

Unlike ac_fetch_format, this enum can be packed into two bits.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>

aco: fix vadd32() when b is neither a constant nor temporary

This will be useful for compiling vertex shader prologs, where we
basically use ACO as an assembler.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11717>

nir/linker: rename replace_constant_input to replace_varying_input_by_constant_load

To align with replace_varying_input_by_uniform_load and better
describe what it does.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>

nir/linker: support uniform when optimizing varying

Varying assigned from uniform won't change after interpolation,
so move uniform load to fragment shader to eliminate the varying.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>

mesa/st: delay nir spirv link

Following commit for st_nir_link_shaders->nir_link_opt_varyings
may copy uniform variable from one shader to another, so delay
the nir_spirv link which contains mesa uniform information
update (gl_nir_link_uniforms) after it and align with glsl link.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12613>

anv: dirty only state impacted by blorp_exec

Instead of dirtying all state after blorp operations,
avoid dirtying state that blorp never touches.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5077
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12567>

r300: fixes for UB caused by left shifts

r300_vs.c:252:37: runtime error: left shift of negative value -1
r300_state.c:1824:66: runtime error: left shift of 63112 by 16 places
cannot be represented in type 'int'

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13308>

radeonsi: fix an out-of-bounds access in si_create_vertex_state

Fixes: fb8f532ea1b - radeonsi: implement draw_vertex_state for lower display list overhead
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5484

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13309>

radeonsi: align pipe_resource & sampler_view allocations to a cache line

It eliminates "False Sharing" for atomic operations. (see wikipedia)

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11618>

util,gallium: put count in pipe_resource & sampler_view on its own cache line

This adds 60 bytes to both structures. It eliminates "False Sharing"
for atomic operations (see wikipedia).

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11618>

driconf: set vk_x11_strict_image_count for Wolfenstein: Youngblood

Otherwise, the game refuses to start on xwayland.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13289>

nir: avoiding reading unitialized memory when using nir_dest_copy

Deeper in chain of calls, function "src_has_indirect" is used (which
reads "is_ssa" and "reg.indirect").

Fixes: d1eae6f36be6 ("nir: Properly clean up nir_src/dest indirects")

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13317>

turnip: fix streamout buffer offset calculations

Fixes vkd3d test "test_vbv_stride_edge_cases"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13315>

ci: Update piglit to 7d7dd2688c214e1b3c00f37226500cbec4a58efb.

This brings in a bunch of i915g spurious fail fixes, fixes for !12613, and
new tests.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13253>

ci: Update deqp to vulkan-cts-1.2.7.1.

Brings in some VK fixes for tilers.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13253>

vulkan/wsi/display: Delete the wrapper entrypoints

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi/wayland: Delete the wrapper entrypoints

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi/x11: Delete the wrapper entrypoints

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi/common: Delete the wrapper entrypoints

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

venus: Use the common WSI wrappers

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

lavapipe: Use the common WSI wrappers

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

panvk: Use the common WSI wrappers

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

v3dv: Use the common WSI wrappers

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

turnip: Use the common WSI wrappers

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

radv: Use the common WSI wrappers

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

anv: Use the common WSI wrappers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi: Add common wrappers for most entrypoints

For a long time, our Vulkan WSI code has acted as something of a layer.
The WSI code calls into various Vulkan entrypoints inside the driver to
create images, allocate memory, etc.  It then implements the API-facing
interface almost entirely.  The only thing the driver has to provide is
little wrappers that wrap around the WSI calls to expose them through
the API.

However, now that we have a common dispatch framework, we can implement
entrypoints directly in the WSI code.  As long as the driver uses
vk_instance, vk_physical_device, and vk_device, we can provide common
wrappers for the vast majority of entrypoints.  The only exceptions are
vkAcquireNextImage, vkQueuePresent, vkRegisterDeviceEventEXT, and
vkRegisterDisplayEventEXT because those may have to manually poke at
synchronization primitives.  We provide wrappers for vkAcquireNextImage
and vkQueuePresent because some drivers can use the default versions.

For now, we're intentionally avoiding any link-time dependencies between
WSI and the common code.  We only use VK_FROM_HANDLE and associated
inline helpers and vk_physical_device has a pointer to a wsi_device.
Eventually, we may tie the two together closer, but this lets us get 95%
of the way there without reworking the universe.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi: Add a dispatch table for WSI entrypoints

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

meson: Add and use an idep for Vulkan WSI

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

v3dv: enable VK_KHR_surface_protected_capabilities

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13298>

egl: implement EGL_EXT_present_opaque on wayland

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: James Jones <jajones@nvidia.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>

egl: sync eglext.h & egl.xml from Khronos

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>

ci/freedreno: Disable the minetest trace due to flaky shader code.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4595
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13316>

iris: Tile cache flush for depth before fast clear

Instead of doing a tile cache flush after slow clears or when the clear
value changes, do it before every fast clear of a HIZ_CCS_WT surface.
This agrees with the Bspec.

Fixes: c85ea824bca ("iris: reduce redundant tile cache flushes")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>

anv: Tile cache flush for depth before fast clear

Instead of doing a tile cache flush after slow clears, resolves, and
ambiguates, do it before fast clears of HIZ_CCS_WT surfaces. This agrees
with the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>

anv: Allow HIZ_CCS_WT with subpass self-dependencies

This unblocks later commits that aim to align the driver with the tile
cache flushing requirements in the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>

ir3/freedreno: handle non-uniform a1en instructions

Fixes vkd3d test "test_bindless_samplers_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>

ir3/freedreno: handle non-uniform resinfo

We forgot to handle non-uniform resinfo case.

Fixes vkd3d test "test_bindless_bufinfo_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>

aco/optimizer: Skip SDWA on v_lshlrev when unnecessary in apply_extract.

In the following cases:
- lower 16 bits are extracted and the shift amount is 16 or more
- lower 8 bits are extracted and the shift amount is 24 or more
the undesireable upper bits are already shifted out, and therefore
there is no need to add SDWA to the v_lshlrev instruction.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize: 153498624 -> 153265616 (-0.15%); split: -0.15%, +0.00%
Instrs: 29636304 -> 29578064 (-0.20%); split: -0.20%, +0.00%
Latency: 136931496 -> 136876379 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 21134367 -> 21078861 (-0.26%); split: -0.26%, +0.00%
Copies: 2777550 -> 2777548 (-0.00%); split: -0.00%, +0.00%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>

ac/nir/nggc: Write undef to variables in non-repacked ES threads.

This helps the compiler generate a little bit more efficient code.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 4659 (3.62% of 128647) affected shaders:
CodeSize: 7468320 -> 7404484 (-0.85%); split: -0.88%, +0.03%
Instrs: 1423425 -> 1407454 (-1.12%); split: -1.16%, +0.03%
Latency: 5250593 -> 5226163 (-0.47%); split: -0.47%, +0.00%
InvThroughput: 739848 -> 733373 (-0.88%); split: -0.90%, +0.02%
Copies: 200139 -> 190307 (-4.91%); split: -5.13%, +0.22%
Branches: 87925 -> 85998 (-2.19%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>

ac/nir/cull: Accept NaN and +/- Inf in face culling.

When the determinant that we use for calculating triangle area
is NaN, it's not possible to decide the facing of the triangle.

This can happen when a coordinate of one of the triangle's vertices
is INFINITY. It's better to just accept these triangles in the shader
and let the PA deal with them.

Let's do the same for +/- Infinity too.
Though we haven't seen this yet, it may be troublesome as well.

Fixes: 651a3da1b59446a6e392321d1dbbc1891a0544a8
Closes: #5470
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13299>

amd/common: Add fallback for misreported clocks for RGP.

Traces with clock = 0 are totally useless due to RGP getting very
confused.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13301>

ir3: Fold ldc src immediates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Fix handling cat6 immediates

We were treating them the same as regular cat2/cat3/cat4 immediates, but
that's not right because cat6 sources are only 8 bits.

Our bindless code was handling this before for bindless resources, and
it was disabled for most other things, so this was mostly harmless, but
fixing it will be necessary for handling ldc offsets.

In addition enable tests for this that were just commented out, and add
a custom test making sure that the immediate source is treated as
unsigned.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Fix check for immediate range

This would incorrectly allow both e.g. 0x2000 and 0xffffe000 to be
encoded as 0x2000.

Fixes: f0a1f3de278 ("freedreno/ir3: cp small negative integers too")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3/legalize: handle WAR for special regs

In particular many cat5/cat6 instructions read a1.x, and we need to add
a (ss) before any mova1 instruction afterwards, as the blob does.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Handle special regs in regmask

Use the same hack as post-RA scheduling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Remove separate regmask.h

Inline it into its one user. There's no point in keeping it separate,
and in order to handle special registers it will have to become a bit
more intertwined with core ir3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Always create barycentrics in the input block

Otherwise, when there are uses in multiple blocks the collect may not
dominate some of the uses.

This is a bugfix, but before it would've mattered only in weird
scenarios with interpolateAt*. When we start moving prefetch textures
into the block before the preamble it will start to matter more, because
it will need to read the barycentrics from a different block than the
bary.f instructions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Make ir3_create_collect() take a block

There's no reason to make this any different from the other builders,
since it just creates a collect instruction, and in the next commit
we'll need to create a collect in the first block for prefetch textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Fix printing branch type

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

nir/lower_ubo_vec4: Fix align_mul=8 special case

In order for the load to never straddle the load can't extend past 8
bytes, not 16. For example a vec2 load with align_mul = 8 and
align_offset = 4 can straddle.

Fixes assertion failures when we stop pushing UBOs in the preamble on
a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3/cp: Fix inlining 32->16 const into meta instructions

We shouldn't return early here, because we still need to actually do the
conversion. Fixes an infinite loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3/cp: Add missing const promotion check

We need to check the source type for moves when the destination type is
u16, just like the f16 check above.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

radv: Do early and late tests for fast clears

We don't know some information regarding DCC image stores and therefore fast clears until we know the surface info.

We should work towards eliminating this, but the cases where this will hit on GFX10_3 is basically 0.

Finally fixes a perf regression in Doom Eternal.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13283>

radv: implement VK_KHR_format_feature_flags2

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>

radv: switch to VK_FORMAT_FEATURE_2_XXX/VkFormatProperties3KHR

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>

radv: remove duplicated code about NGG passthrough determination

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: do not initialize is_ngg_passthrough for geometry shaders

Geometry shaders can't be NGG passthrough at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

aco: cleanup setup_vs_output_info()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: stop gathering output GS info for vertex shaders

This has no effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: rename needs_multiview_view_index to uses_view_index

To avoid confusion with radv_pipeline_key::has_multiview_view_index.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: remove no-op about the view index in the shader info pass

The view index is always lowered to map the layer ID for fragment
shaders. This was never reached.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv,aco: remove nir_intrinsic_load_layer_id

This was never used because the layer ID isn't a system value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: Handle copying zero queries.

Looks like this is allowed.

Fixes: 8475a14302e ("radv: Implement pipeline statistics queries.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12907>

docs/panfrost: Fix link to use rst syntax

Currently the link uses markdown syntax to direct users to IRC, switch
to IRC to render this correctly.

Fixes: e39929663bb ("docs/panfrost: Add web chat link")

Signed-Off by: Esme Xuan Lim <esmethedev@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13296>

freedreno: Add valgrind dependency.

Fix a build error.

In file included from ../src/util/u_queue.h:38,
                 from ../src/freedreno/drm/freedreno_ringbuffer.h:33,
                 from ../src/freedreno/ds/fd_pps_driver.h:13,
                 from ../src/freedreno/ds/fd_pps_driver.cc:7:
../src/util/simple_mtx.h:35:12: fatal error: valgrind.h: No such file or directory
   35 | #  include <valgrind.h>
      |            ^~~~~~~~~~~~

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13280>

vulkan: Generate defines for aliases of promoted enums

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13264>

vulkan: fix handling of aliases in enum members

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13264>

ir3/ra: Use killed sources in register eviction

Let's assume we have a vec2 collect instruction with killed sources that
are non-contiguous and the entire rest of the register file is blocked,
which can happen when our register target is very tight. It's impossible
to just insert move instructions to resolve this, but we can make space
by swapping one of the killed sources with the value next to the other,
assuming it's also scalar.

This commit implements that idea, preventing us from falling back to the
terrible shuffle-everything approach in this case.

total instructions in shared programs: 1566648 -> 1565117 (-0.10%)
instructions in affected programs: 13332 -> 11801 (-11.48%)
helped: 30
HURT: 5
helped stats (abs) min: 6 max: 535 x̄: 51.77 x̃: 25
helped stats (rel) min: 2.67% max: 33.63% x̄: 12.28% x̃: 9.58%
HURT stats (abs)   min: 1 max: 6 x̄: 4.40 x̃: 6
HURT stats (rel)   min: 0.18% max: 5.13% x̄: 2.41% x̃: 2.13%
95% mean confidence interval for instructions value: -75.05 -12.43
95% mean confidence interval for instructions %-change: -13.18% -7.18%
Instructions are helped.

total mov in shared programs: 77336 -> 76683 (-0.84%)
mov in affected programs: 2135 -> 1482 (-30.59%)
helped: 29
HURT: 5
helped stats (abs) min: 2 max: 227 x̄: 23.31 x̃: 10
helped stats (rel) min: 6.06% max: 72.73% x̄: 31.83% x̃: 30.00%
HURT stats (abs)   min: 2 max: 9 x̄: 4.60 x̃: 4
HURT stats (rel)   min: 14.29% max: 69.23% x̄: 34.00% x̃: 27.78%
95% mean confidence interval for mov value: -33.21 -5.20
95% mean confidence interval for mov %-change: -32.94% -11.35%
Mov are helped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>

ir3/ra: Don't reset round-robin start for each block

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>

ir3: Initialize local size earlier

We need the local size in RA for occupancy calculations. Not
initializing these had the unfortunate consequence of
ir3_get_reg_independent_max_waves() returning 0 for compute shaders with
shared variables, disabling the register limiting logic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>

anv: implement VK_KHR_format_feature_flags2

v2: fix SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR (Ivan)

v3: Fixup VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR setting (Ivan)
    Add missing drm-modifiers/android bits (Lionel)

v4: Avoid duplicating get_ahw_buffer_format_properties() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: start computing KHR_format_features2 flags for storage images

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: Flip around the way we reason about storage image lowering

There are roughly two cases when it comes to storage images.  In the
easy case, we have full hardware support and we can just emit a typed
read/write message in the shader and we're done.  In the more complex
cases, we may need to fall back to a typed read with a different format
or even to a raw (SSBO) read.

The hardware has always had basically full support for typed writes all
the way back to Ivy Bridge but typed reads have been harder to come by.
Starting with Skylake, we finally have enough that we at least have a
format of the right bit size but not necessarily the right format so we
can use a typed read but may still have to do an int->unorm or similar
cast in the shader.

Previously, in ANV, we treated lowered images as the default and write-
only as a special case that we can optimize.  This flips everything
around and treats the cases where we don't need to do any lowering as
the default "vanilla" case and treats the lowered case as special.
Importantly, this means that read-write access to surfaces where the
native format handles typed writes now use the same surface state as
write-only access and the only thing that uses the lowered surface state
is access read-write access with a format that doesn't support typed
reads.  This has the added benefit that now, if someone does a read
without specifying a format, we can default to the vanilla surface and
it will work as long as it's a format that supports typed reads.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

intel/nir: allow unknown format in lowering of storage images

We're about to allow unknown format for specific formats in Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: switch to use VkFormatFeatureFlags2KHR internally

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: Use the common wrapper for GetPhysicalDeviceFormatProperties

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

vulkan: Generate #defines with every bit in a given bitfield

This is useful when trying to restrict from VkFoo2 to VkFoo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

vulkan: Generate flag #defines based on bitwidth

Instead of basing it on a fixed list, just generate #defines for every
bitfield that's 64-bit.  As part of this refactor, we rework things a
bit to record all bitfields and just not do anything with them if
they're not 64-bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

radv: store the post-processed shader binary config to the cache

This will allow us to reduce the size of radv_shader_info which is
stored in the cache entry.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12992>

radv: move ac_shader_config to radv_shader_binary instead of legacy

This will allow us to avoid postprocessing binaries when they are
loaded from the shaders cache.

LLVM binaries already contain the shader config as part of the ELF,
so it's duplicated and increase the cache entry by 48 bytes. Though,
I don't think that should matter for LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12992>

ac/surface: Expose modifiers capable of DCC image stores first

These also have a higher compressed block size.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

radv: Respect max extent for modifiers

Some of our modifiers only support upto a certain range, expose this in ImageFormatProperties.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

radeonsi: Check if modifier supports the image extent

DCN only supports an extent < 4K on !64B && 128B.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

ac/surface: Add ac_modifier_max_extent

Currently, we aren't checking if the modifier supports the extent of the image.

DCN only works with !64B && 128B on extents < 4K.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

tu: Expose VK_KHR_shader_subgroup_extended_types

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13271>

ir3: Skip src size validation for cat1

They are already handled below, like cat6. The default rules won't work
for the READ_* macros once they have 16-bit sources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13271>

ir3/lower_subgroups: Support 16-bit READ_* sources

With VK_EXT_shader_subgroup_extended_types these will have 16-bit
sources that need to be expanded to 32-bit (and then narrowed again).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13271>

anv: fix potential integer overflow

Description by Coverity:
"Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression 1 << b with type int
(32 bits, signed) is evaluated using 32-bit arithmetic, and then used in
a context that expects an expression of type VkAccessFlags2KHR (64 bits,
unsigned)"

CID: 1492745
CID: 1492748

Fixes: b996fa8efaa ("anv: implement VK_KHR_synchronization2")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13284>

radv: use nir_ssa_undef() for unused image components in meta shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: use get_global_ids() to compute coordinates in meta shaders

This was duplicated everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: remove few useless nir_channels() in meta shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: remove useless coordinate computation in the compute clear path

Global Z is always 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: use nir_image_deref_{load,store} in the DCC retile compute path

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: advertise VK_KHR_maintenance4

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>

radv: implement vkGetDeviceImageSparseMemoryRequirementsKHR()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>