Brian Paul [Thu, 15 Sep 2016 21:13:07 +0000 (15:13 -0600)]
st/mesa: only enable MSAA coverage options when we have a MSAA buffer
Regardless of whether GL_MULTISAMPLE is enabled (it's enabled by default)
we should not set the alpha_to_coverage or alpha_to_one flags if the
current drawing buffer does not do MSAA.
This fixes the new piglit gl-1.3-alpha_to_coverage_nop test.
ETQW is a game that enables GL_SAMPLE_ALPHA_TO_COVERAGE without MSAA.
Shrubs along the side of roads were invisible because fragments with
alpha < 0.5 were being discarded (zero coverage).
v2: remove ctx->DrawBuffer != NULL check.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Thu, 15 Sep 2016 01:08:28 +0000 (02:08 +0100)]
spirv: use subpass image type (v1.1)
This adds support for the input attachments subpass type
to the SPIRV->NIR pass.
v1.1: drop handling from vtn_handle_texture
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 15 Sep 2016 01:08:12 +0000 (02:08 +0100)]
glsl: add subpass image type (v2)
SPIR-V/Vulkan have a special image type for input attachments
called the subpass type. It has different characteristics than
other images types.
The main one being it can only be an input image to fragment
shaders and loads from it are relative to the frag coord.
This adds support for it to the GLSL types. Unfortunately
we've run out of space in the sampler dim in types, so we
need to use another bit.
v2: Fixup subpass input name (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Fri, 26 Aug 2016 20:01:13 +0000 (13:01 -0700)]
isl: Finish tiling filtering for Gen6.
Gen6 only has one additional restriction over Gen7+, so we just add it
to the existing gen7 function (which actually covers later gens too).
This should stop FINISHME spew when running GL on Sandybridge.
v2: Fix bytes per block vs. bits per block confusion (Jason) and
rename function to gen6_filter_tiling (Jason and Chad).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Sun, 28 Aug 2016 23:55:05 +0000 (19:55 -0400)]
i965: enable ARB_ES3_2_compatibility on gen8+
Note that ASTC support is not actually mandated for this extension to be
exposed.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 14 Sep 2016 17:42:42 +0000 (10:42 -0700)]
i965/nir: Roll set_default_interpolation into lower_fs_inputs
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 14 Sep 2016 17:39:52 +0000 (10:39 -0700)]
i965/fs: Use NIR for handling forced per-sample interpolation
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 14 Sep 2016 17:29:38 +0000 (10:29 -0700)]
nir: Add a flag to lower_io to force "sample" interpolation
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Wed, 14 Sep 2016 17:04:47 +0000 (10:04 -0700)]
i965/fs: Use sample interpolation for interpolateAtCentroid in persample mode
From the ARB_gpu_shader5 spec:
The built-in functions interpolateAtCentroid() and interpolateAtSample()
will sample variables as though they were declared with the "centroid"
or "sample" qualifiers, respectively.
When running with persample dispatch forced by the API, we interpolate
anything that isn't flat as if it's qualified by "sample". In order to
keep interpolateAtCentroid() consistent with the "centroid" qualifier, we
need to make interpolateAtCentroid() do sample interpolation instead.
Nothing in the GLSL spec guarantees that the result of
interpolateAtCentroid is uniform across samples in any way, so this is a
perfectly fine thing to do.
Fixes 8 of the new dEQP-VK.pipeline.multisample_interpolation.* Vulkan CTS
tests that specifically validate consistency between the "sample" qualifier
and interpolateAtSample()
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Brian Paul [Wed, 14 Sep 2016 18:16:18 +0000 (12:16 -0600)]
mesa: check for no matrix change in _mesa_LoadMatrixf()
Some apps issue redundant glLoadMatrixf() calls with the same matrix.
Try to avoid setting dirty state in that situation.
This reduces the number of constant buffer updates by about half in
ET Quake Wars.
Tested with Piglit, ETQW, Sauerbraten, Google Earth, etc.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jon Turney [Mon, 11 Jul 2016 20:38:16 +0000 (21:38 +0100)]
direct-to-native-GL for GLX clients on Cygwin ("Windows-DRI")
Structurally, this is very similar to the existing Apple-DRI code, except I
have chosen to implement this using the __GLXDRIdisplay, etc. vtables (as
suggested originally in [1]), rather than a maze of ifdefs. This also means
that LIBGL_ALWAYS_SOFTWARE and LIBGL_ALWAYS_INDIRECT work as expected.
[1] https://lists.freedesktop.org/archives/mesa-dev/2010-May/000756.html
This adds:
* the Windows-DRI extension protocol headers and the windowsdriproto.pc
file, for use in building the Windows-DRI extension for the X server
* a Windows-DRI extension helper client library
* a Windows-specific DRI implementation for GLX clients
The server is queried for Windows-DRI extension support on the screen before
using it (to detect the case where WGL is disabled or can't be activated).
The server is queried for fbconfigID to pixelformatindex mapping, which is
used to augment glx_config.
The server is queried for a native handle for the drawable (which is of a
different type for windows, pixmaps and pbuffers), which is used to augment
__GLXDRIdrawable.
Various GLX extensions are enabled depending on if the equivalent WGL
extension is available.
Emil Velikov [Thu, 15 Sep 2016 10:31:06 +0000 (11:31 +0100)]
docs: add news item and link release notes for 12.0.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 15 Sep 2016 10:29:24 +0000 (11:29 +0100)]
docs: add sha256 checksums for 12.0.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
09460b8cf7ddac4abb46eb6439314b29954c76a6)
Emil Velikov [Thu, 15 Sep 2016 09:18:54 +0000 (10:18 +0100)]
docs: add release notes for 12.0.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
d79b2e7bf30ad6d1fa43f30940a64ed9fd0aa9c0)
Kenneth Graunke [Sat, 3 Sep 2016 05:54:25 +0000 (22:54 -0700)]
mesa: Expose RESET_NOTIFICATION_STRATEGY with KHR_robustness.
This is supposed to be exposed with the GL_KHR_robustness extension,
which we support on ES 2.0 and later. On desktop GL, it's also exposed
by GL_ARB_robustness, which is supported by all drivers ("dummy_true").
so we also allow desktop GL.
Fixes:
- ES32-CTS.robust.robustness.noResetNotification
- ES32-CTS.robust.robustness.loseContextOnReset
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Jason Ekstrand [Mon, 12 Sep 2016 19:58:38 +0000 (12:58 -0700)]
anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW
Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.
Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of
the dEQP-VK.image.atomic_operations.* tests on HSW
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Mon, 12 Sep 2016 22:50:05 +0000 (15:50 -0700)]
intel/blorp: Stop setting 3DSTATE_DRAWING_RECTANGLE
The Vulkan driver sets 3DSTATE_DRAWING_RECTANGLE once to MAX_INT x MAX_INT
at the GPU initialization time and never sets it again. The GL driver sets
it every time the framebuffer changes. Originally, blorp set it to the
size of the drawing area but meant we had to set it back in the Vulkan
driver. Instead, we can easily just do that in the GL driver's blorp_exec
implementation and not set it in blorp core.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Mon, 12 Sep 2016 22:50:04 +0000 (15:50 -0700)]
intel/blorp: Emit 3DSTATE_MULTISAMPLE directly
Previously, we relied on a driver hook for 3DSTATE_MULTISAMPLE. However,
now that Vulkan and GL use the same sample positions, we can set up
3DSTATE_MULTISAMPLE directly in blorp and delete the driver hook.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Mon, 12 Sep 2016 22:50:03 +0000 (15:50 -0700)]
intel: Move Vulkan sample positions to common code
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Marek Olšák [Wed, 14 Sep 2016 22:46:26 +0000 (00:46 +0200)]
Revert "tgsi/scan: don't set interp flags for inputs only used by INTERP instructions"
This reverts commit
524fd55d2d973f50a5d8bc2255684610f5faae32.
Reason: https://bugs.freedesktop.org/show_bug.cgi?id=97808
Francisco Jerez [Fri, 2 Sep 2016 05:37:57 +0000 (22:37 -0700)]
i965/vec4: Assert that pull constant load offsets are 16B-aligned.
Non-16B-aligned pull constant loads are unlikely to be particularly
useful given that you can get roughly the same effect by using
swizzles on the result.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:39:00 +0000 (22:39 -0700)]
i965/vec4: Assert that ATTR regions are register-aligned.
It might be useful to actually handle this once copy propagation
becomes smarter about register-misaligned offsets.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:36:15 +0000 (22:36 -0700)]
i965/vec4: Don't spill non-GRF-aligned register regions.
A better fix would be to do something along the lines of the FS
back-end spilling code and emit a scratch read before any instruction
that overwrites the register to spill partially due to a non-zero
sub-register offset. In the meantime mark registers used with a
non-zero sub-register offset as no-spill to prevent the spilling code
from miscompiling the program.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:31:43 +0000 (22:31 -0700)]
i965/vec4: Fix copy propagation for non-register-aligned regions.
This prevents it from trying to propagate a copy through a
register-misaligned region. MOV instructions with a misaligned
destination shouldn't be treated as a direct GRF copy, because they
only define the destination GRFs partially. Also fix the interference
check implemented with is_channel_updated() to consider overlapping
regions with different register offset to interfere, since the
writemask check implemented in the function is only valid under the
assumption that the source and destination regions are aligned
component by component.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:26:59 +0000 (22:26 -0700)]
i965/vec4: Compare full register offsets in cmod propagation.
Cmod propagation would misoptimize the program if the destination
offset of the generating instruction wasn't exactly the same as the
source region offset of the copy instruction. In preparation for
adding support for sub-GRF offsets to the VEC4 IR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:12:04 +0000 (22:12 -0700)]
i965/vec4: Assign correct destination offset to rewritten instruction in register coalesce.
Because the pass already checks that the destination offset of each
'scan_inst' that needs to be rewritten matches 'inst->src[0].offset'
exactly, the final offset of the rewritten instruction is just the
original destination offset of the copy. This is in preparation for
adding support for sub-GRF offsets to the VEC4 IR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:08:29 +0000 (22:08 -0700)]
i965/vec4: Don't coalesce registers with overlapping writes not matching the MOV source.
In preparation for adding support for sub-GRF offsets to the VEC4 IR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:04:02 +0000 (22:04 -0700)]
i965/vec4: Compare full register offsets in opt_register_coalesce nop move check.
In preparation for adding support for sub-GRF offsets to the VEC4 IR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 05:02:00 +0000 (22:02 -0700)]
i965/vec4: Check that the write offsets match when setting dependency controls.
For simplicity just assume that two writes to the same GRF with
different sub-GRF offsets will potentially interfere and break the
dependency control chain. This is in preparation for adding sub-GRF
offset support to the VEC4 IR.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:51:07 +0000 (21:51 -0700)]
i965/vec4: Change opt_vector_float to keep track of the last offset seen in bytes.
This simplifies things slightly and makes the pass more correct in
presence of sub-GRF offsets.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 9 Sep 2016 01:00:11 +0000 (18:00 -0700)]
i965/vec4: Simplify src/dst_reg to brw_reg conversion by using byte_offset().
This should also have the side effect of fixing convert_to_hw_regs()
to handle sub-GRF register offsets.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 20:53:13 +0000 (13:53 -0700)]
i965/ir: Update several stale comments.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 03:42:24 +0000 (20:42 -0700)]
i965/ir: Don't print ARF subnr values twice.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 20:52:54 +0000 (13:52 -0700)]
i965/vec4: Print src/dst_reg::offset field consistently for all register files.
C.f. 'i965/fs: Print fs_reg::offset field consistently for all
register files.'.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 03:31:47 +0000 (20:31 -0700)]
i965/fs: Print fs_reg::offset field consistently for all register files.
The offset printing code in fs_visitor::dump_instruction() was doing
things differently for sources and destinations and for each register
file -- In some cases it would be added to the base register number
fs_reg::nr, in other cases it would follow the base register separated
with a plus sign, in other cases (uniforms) it would do both (!). The
sub-register offset was also being printed or not rather
inconsistently. Fix it.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:19:29 +0000 (21:19 -0700)]
i965/fs: Misc simplification.
Get rid of some leftover redundant arithmetic introduced during the
conversion to byte offsets and sizes that can be simplified easily.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 07:35:03 +0000 (00:35 -0700)]
i965/fs: Get rid of fs_inst::set_smear().
component() was generally a better alternative because of several
issues set_smear() had:
- It wouldn't take the original stride and offset of the register
into account, which means that set_smear() on the result of
e.g. another set_smear() call or an offset() call would give a
bogus region as result.
- It was an inherently destructive operation. See the
'nir_intrinsic_shader_clock' hunk below for how this could lead to
subtle bugs in cases where set_smear() was called multiple times on
the same register like 'r.set_smear(0), r.set_smear(1)' with the
expectation that each call would return a separate value instead of
a reference to the same subsequently mutated object.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 03:06:40 +0000 (20:06 -0700)]
i965/fs: Use region_contained_in() in compute-to-mrf coalescing pass.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 03:03:44 +0000 (20:03 -0700)]
i965/fs: Move region_contained_in to the IR header and fix for non-VGRF files.
Also changed the argument names since 'src' and 'dst' don't make that
much sense outside of the context of copy propagation.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:47:56 +0000 (19:47 -0700)]
i965/fs: Change region_contained_in() to use byte units.
This makes the function less annoying to use and more accurate -- We
shouldn't propagate a copy into a register region that wasn't fully
contained in the destination of the copy (IOW, a source region that
wasn't fully defined by the copy) just because the number of registers
written and read by each instruction happened to get rounded up to the
same GRF multiple.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:22:03 +0000 (21:22 -0700)]
i965/fs: Simplify copy propagation LOAD_PAYLOAD ACP setup.
By keeping track of 'offset' in byte units.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 01:43:48 +0000 (18:43 -0700)]
i965/fs: Simplify a bunch of fs_inst::size_written calculations by using component_size().
Using component_size() is easier and generally more correct because it
takes into account the register type and stride for you.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 23:46:34 +0000 (16:46 -0700)]
i965/fs: Simplify result_live calculation in dead_code_eliminate().
No need to unroll the first iteration of the loop manually.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:16:01 +0000 (19:16 -0700)]
i965/fs: Simplify and fix buggy stride/offset calculations using subscript().
These were bashing the 'offset' and 'stride' values of several
registers without taking the previous value into account, which
probably didn't matter in practice for optimize_frontfacing_ternary()
because the 'tmp' register already had a known region, but it would
have given the wrong region as result in the other cases in
lower_integer_multiplication(). subscript(..., i) is a more
straightforward way to take the i-th field of a given type from each
channel of a register which should give the right answer as result
regardless of the original 'offset' and 'stride' parameters of the
register region.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:32:25 +0000 (13:32 -0700)]
i965/fs: Simplify get_fpu_lowered_simd_width() by using inequalities instead of rounding.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:27:12 +0000 (19:27 -0700)]
i965/fs: Simplify byte_offset().
In the most common case this can now be implemented as a simple
addition because the offset is already encoded as a single scalar
value in bytes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 8 Sep 2016 00:00:58 +0000 (17:00 -0700)]
i965/fs: Fix signedness of the return value of fs_inst::size_read().
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 22:21:26 +0000 (15:21 -0700)]
i965/fs: Switch mask_relative_to() used in compute-to-mrf to byte units.
This makes the helper function less annoying to use and somewhat more
accurate.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 20:14:28 +0000 (13:14 -0700)]
i965/fs: Fix bogus sub-MRF offset calculation in compute-to-mrf.
The 'scan_inst->dst.offset % REG_SIZE' term in the final
'scan_inst->dst.offset' calculation is obviously bogus. The offset
from the start of the copy destination register 'inst->dst' where the
destination of the generating instruction 'scan_inst' would be written
to (before compute-to-mrf runs) is just the offset of 'scan_inst->dst'
relative to the source of the copy instruction (AKA rel_offset in the
code below).
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 20:04:23 +0000 (13:04 -0700)]
i965/fs: Take into account copy register offset during compute-to-mrf.
This was dropping 'inst->dst.offset' on the floor. Nothing in the
code above seems to guarantee that it's zero and in that case the
offset of the register being coalesced into wouldn't be taken into
account while rewriting the generating instruction.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:42:40 +0000 (19:42 -0700)]
i965/vec4: Drop backend_reg::in_range() in favor of regions_overlap().
This makes sure that overlap checks are done correctly throughout the
back-end when the '*this' register starts before the register/size
pair provided as argument, and is actually less annoying to use than
in_range() at this point since regions_overlap() takes its size
arguments in bytes.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:38:36 +0000 (19:38 -0700)]
i965/vec4: Port regions_overlap() to the vec4 IR.
This is copy-pasted almost line by line from the FS back-end. The
only reason it cannot be implemented in terms of backend_reg is that
the backend_reg::nr field doesn't have the same meaning for uniforms
on both back-ends. It could be easily deduplicated by using a
template function.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:36:23 +0000 (19:36 -0700)]
i965/fs: Stop using fs_reg::in_range() in favor of regions_overlap().
Its only use left in the FS back-end should be using regions_overlap()
instead to avoid getting a false negative result in cases where source
and destination overlap but the former starts before the latter in the
VGRF file.
v2: Put back lost components factor (Iago).
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 02:34:18 +0000 (19:34 -0700)]
i965/fs: Drop fs_inst::overwrites_reg() in favor of regions_overlap().
fs_inst::overwrites_reg is rather easy to misuse because it cannot
tell how large the register region starting at 'reg' is, so in cases
where the destination region starts after 'reg' it may give a
misleading result. regions_overlap() is somewhat more verbose to use
but handles arbitrary overlap correctly so it should generally be used
instead.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:36:59 +0000 (21:36 -0700)]
i965/fs: Fix LOAD_PAYLOAD handling in register coalesce is_nop_mov().
is_nop_mov() was broken for LOAD_PAYLOAD instructions in two ways: On
the one hand the original destination register offset wasn't being
taken into account which would give incorrect results if it was
already non-zero, and on the other hand all source registers were
being treated as if they had a size of 32B, which is almost never the
case in SIMD16 programs for non-header sources.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:20:18 +0000 (21:20 -0700)]
i965/fs: Fix can_propagate_from() source/destination overlap check.
The previous overlap condition only made sure that the VGRF numbers or
GRF-aligned offsets were different without taking the amount of data
written and read by the instruction into consideration. Use the
regions_overlap() helper instead.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:16:14 +0000 (21:16 -0700)]
i965/fs: Compare full register offsets in cmod propagation pass.
This could potentially have misoptimized a program in cases where
inst->src[0] had a non-zero sub-GRF offset.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 02:32:37 +0000 (19:32 -0700)]
i965/fs: Don't consider LOAD_PAYLOAD with stride > 1 source to behave like a raw copy.
Noticed the problem by inspection while typing in the previous commit.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:05:51 +0000 (21:05 -0700)]
i965/fs: Don't consider LOAD_PAYLOAD with sub-GRF offset to behave like a raw copy.
This was likely the original intention, and at least register coalesce
relies on it.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 00:57:34 +0000 (17:57 -0700)]
i965/vec4: Take into account misalignment in regs_written() and regs_read().
Unlike the FS counterpart of this commit this was likely not (yet) a
bug, but let's fix it already in preparation for implementing support
for sub-GRF offsets in the VEC4 back-end.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 21:36:32 +0000 (14:36 -0700)]
i965/fs: Take into account misalignment in regs_written() and regs_read().
There was a workaround for this in fs_inst::size_read() for the
SHADER_OPCODE_MOV_INDIRECT instruction and FIXED_GRF register file
*only*. We should take this possibility into account for the sources
and destinations of all instructions on all optimization passes that
need to quantize dataflow in 32B increments by adding the amount of
misalignment to the size read or written from the regs_read() and
regs_written() helpers respectively.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 21:33:55 +0000 (14:33 -0700)]
i965/fs: Take into account trailing padding in regs_written() and regs_read().
This fixes regs_written() and regs_read() to return a more accurate
value when the padding left between components due to a stride value
greater than one causes the region bounds given by size_written or
size_read to overflow into the next register. This could become a
problem in optimization passes that keep track of dataflow using
fixed-size arrays with register granularity, because the overflow
register (not actually accessed by the region) may not have been
allocated at all which could lead to undefined memory access.
An alternative to this would be to subtract the trailing padding
already during the calculation of fs_inst::size_read and
::size_written, but that would break code that currently assumes that
::size_read and _written are whole multiples of the component size,
and would be hard to maintain looking forward because size_written is
assigned from a bunch of different places.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:41:08 +0000 (13:41 -0700)]
i965/fs: Handle fixed HW GRF subnr in reg_offset().
This will be useful later on when we start using reg_offset() on fixed
hardware registers.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 04:25:18 +0000 (21:25 -0700)]
i965/fs: Handle arbitrary offsets in brw_reg_from_fs_reg for MRF/VGRF registers.
This restriction seemed rather artificial... Removing it actually
simplifies things slightly.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:02:55 +0000 (13:02 -0700)]
i965/fs: Return more accurate read size for LINTERP from fs_inst::size_read.
The LINTERP virtual instruction only reads three scalar components
from the first 16B of the second source, we can now teach size_read()
about it since its return value is represented with byte granularity.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Fri, 2 Sep 2016 23:23:44 +0000 (16:23 -0700)]
i965/fs: Return more accurate read size from fs_inst::size_read for IMM and UNIFORM files.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 8 Sep 2016 00:00:30 +0000 (17:00 -0700)]
i965/vec4: Replace vec4_instruction::regs_read with ::size_read using byte units.
The previous regs_read value can be recovered by rewriting each
reference of regs_read() like 'x = i.regs_read(j)' to 'x =
DIV_ROUND_UP(i.size_read(j), reg_unit)'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 8 Sep 2016 00:00:07 +0000 (17:00 -0700)]
i965/fs: Replace fs_inst::regs_read with ::size_read using byte units.
The previous regs_read value can be recovered by rewriting each
reference of regs_read() like 'x = i.regs_read(j)' to 'x =
DIV_ROUND_UP(i.size_read(j), reg_unit)'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sun, 4 Sep 2016 01:19:59 +0000 (18:19 -0700)]
i965/ir: Drop backend_instruction::regs_written field.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Sat, 3 Sep 2016 01:00:21 +0000 (18:00 -0700)]
i965/vec4: Replace vec4_instruction::regs_written with ::size_written field in bytes.
The previous regs_written field can be recovered by rewriting each
rvalue reference of regs_written like 'x = i.regs_written' to 'x =
DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference
like 'i.regs_written = x' to 'i.size_written = x * reg_unit'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 20:38:20 +0000 (13:38 -0700)]
i965/fs: Replace fs_inst::regs_written with ::size_written field in bytes.
The previous regs_written field can be recovered by rewriting each
rvalue reference of regs_written like 'x = i.regs_written' to 'x =
DIV_ROUND_UP(i.size_written, reg_unit)', and each lvalue reference
like 'i.regs_written = x' to 'i.size_written = x * reg_unit'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 23:55:46 +0000 (16:55 -0700)]
i965/vec4: Add wrapper functions for vec4_instruction::regs_read and ::regs_written.
This is in preparation for dropping vec4_instruction::regs_read and
::regs_written in favor of more accurate alternatives expressed in
byte units. The main reason these wrappers are useful is that a
number of optimization passes implement dataflow analysis with
register granularity, so these helpers will come in handy once we've
switched register offsets and sizes to the byte representation. The
wrapper functions will also make sure that GRF misalignment (currently
neglected by most of the back-end) is taken into account correctly in
the calculation of regs_read and regs_written.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Wed, 7 Sep 2016 23:59:35 +0000 (16:59 -0700)]
i965/fs: Add wrapper functions for fs_inst::regs_read and ::regs_written.
This is in preparation for dropping fs_inst::regs_read and
::regs_written in favor of more accurate alternatives expressed in
byte units. The main reason these wrappers are useful is that a
number of optimization passes implement dataflow analysis with
register granularity, so these helpers will come in handy once we've
switched register offsets and sizes to the byte representation. The
wrapper functions will also make sure that GRF misalignment (currently
neglected by most of the back-end) is taken into account correctly in
the calculation of regs_read and regs_written.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 22:11:21 +0000 (15:11 -0700)]
i965/fs: Replace fs_reg::subreg_offset with fs_reg::offset expressed in bytes.
The fs_reg::subreg_offset and ::offset fields are now redundant, the
sub-GRF offset can just be added to the single ::offset field
expressed in byte units. The current subreg_offset value can be
recovered by applying the following rule: Replace each rvalue
reference of subreg_offset like 'x = r.subreg_offset' with 'x =
r.offset % reg_unit', and each lvalue reference like 'r.subreg_offset
= x' with 'r.offset = ROUND_DOWN_TO(r.offset, reg_unit) + x'.
For the same reason as in the previous patches, this doesn't attempt
to be particularly clever about simplifying the result in the interest
of keeping the rather lengthy patch as obvious as possible. I'll come
back later to clean up any ugliness introduced here.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 21:19:27 +0000 (14:19 -0700)]
i965/ir: Remove backend_reg::reg_offset.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 20:10:36 +0000 (13:10 -0700)]
i965/vec4: Replace dst/src_reg::reg_offset with dst/src_reg::offset expressed in bytes.
The dst/src_reg::offset field in byte units introduced in the previous
patch is a more straightforward alternative to an offset
representation split between ::reg_offset and ::subreg_offset fields.
The split representation makes it too easy to forget about one of the
offsets while dealing with the other, which has led to multiple FS
back-end bugs in the past. To make the matter worse the unit
reg_offset was expressed in was rather inconsistent, for uniforms it
would be expressed in either 4B or 16B units depending on the
back-end, and for most other things it would be expressed in 32B
units.
This encodes reg_offset as a new offset field expressed consistently
in byte units. Each rvalue reference of reg_offset in existing code
like 'x = r.reg_offset' is rewritten to 'x = r.offset / reg_unit', and
each lvalue reference like 'r.reg_offset = x' is rewritten to
'r.offset = r.offset % reg_unit + x * reg_unit'.
Because the change affects a lot of places and is rather non-trivial
to verify due to the inconsistent value of reg_unit, I've tried to
avoid making any additional changes other than applying the rewrite
rule above in order to keep the patch as simple as possible, sometimes
at the cost of introducing obvious stupidity (e.g. algebraic
expressions that could be simplified given some knowledge of the
context) -- I'll clean those up later on in a second pass.
v2: Fix division by the wrong reg_unit in the UNIFORM case of
convert_to_hw_regs(). (Iago)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Francisco Jerez [Thu, 1 Sep 2016 19:42:20 +0000 (12:42 -0700)]
i965/fs: Replace fs_reg::reg_offset with fs_reg::offset expressed in bytes.
The fs_reg::offset field in byte units introduced in this patch is a
more straightforward alternative to the current register offset
representation split between fs_reg::reg_offset and ::subreg_offset.
The split representation makes it too easy to forget about one of the
offsets while dealing with the other, which has led to multiple
back-end bugs in the past. To make the matter worse the unit
reg_offset was expressed in was rather inconsistent, for uniforms it
would be expressed in either 4B or 16B units depending on the
back-end, and for most other things it would be expressed in 32B
units.
This encodes reg_offset as a new offset field expressed consistently
in byte units. Each rvalue reference of reg_offset in existing code
like 'x = r.reg_offset' is rewritten to 'x = r.offset / reg_unit', and
each lvalue reference like 'r.reg_offset = x' is rewritten to
'r.offset = r.offset % reg_unit + x * reg_unit'.
Because the change affects a lot of places and is rather non-trivial
to verify due to the inconsistent value of reg_unit, I've tried to
avoid making any additional changes other than applying the rewrite
rule above in order to keep the patch as simple as possible, sometimes
at the cost of introducing obvious stupidity (e.g. algebraic
expressions that could be simplified given some knowledge of the
context) -- I'll clean those up later on in a second pass.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Eero Tamminen [Wed, 14 Sep 2016 14:28:28 +0000 (15:28 +0100)]
glsl: grammar fix
Signed-off-by: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Wed, 14 Sep 2016 19:43:16 +0000 (12:43 -0700)]
docs: Mention AEP in release notes
Kenneth Graunke [Wed, 14 Sep 2016 00:07:36 +0000 (17:07 -0700)]
i965: Enable ANDROID_extension_pack_es31a on Gen9+.
AEP requires ASTC, which is currently only enabled on Skylake and later.
(It may be possible to extend this to Cherryview/Braswell in the future,
but earlier hardware doesn't have ASTC support.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Tue, 13 Sep 2016 22:14:28 +0000 (15:14 -0700)]
nir: Report progress from nir_lower_phis_to_scalar.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 13 Sep 2016 22:14:28 +0000 (15:14 -0700)]
nir: Report progress from nir_lower_alu_to_scalar.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 13 Sep 2016 22:17:29 +0000 (15:17 -0700)]
nir: Call nir_metadata_preserve from nir_lower_alu_to_scalar().
This is mandatory.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 8 Sep 2016 19:49:49 +0000 (15:49 -0400)]
nir/lower_tex: fix typo with sample_dim
Numeric 2 is actually GLSL_SAMPLER_DIM_3D, which I don't think is what
was intended.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 8 Sep 2016 18:07:06 +0000 (14:07 -0400)]
nir: move tex_instr_remove_src
I want to re-use this in a different pass, so move to nir.h
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Rob Clark [Thu, 8 Sep 2016 18:05:39 +0000 (14:05 -0400)]
nir/lower_tex: remove tex_instr_find_src()
Turns out it already exists.. so don't duplicate it.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kyle Brenneman [Mon, 12 Sep 2016 20:15:10 +0000 (16:15 -0400)]
egl: Add storage for EGL_KHR_debug's state to EGL objects
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:46:04 +0000 (17:46 -0400)]
egl: Factor out _eglGetSyncAttribCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:44:36 +0000 (17:44 -0400)]
egl: Factor out _eglWaitSyncCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:40:29 +0000 (17:40 -0400)]
egl: Lock the display in _eglCreateSync's callers
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:38:13 +0000 (17:38 -0400)]
egl: Factor out _eglCreateImageCommon (v2)
v2:
- Pass disp to RETURN_EGL_ERROR so we unlock the display
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:35:22 +0000 (17:35 -0400)]
egl: Factor out _eglWaitClientCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:25:56 +0000 (17:25 -0400)]
egl: Use _eglCreatePixmapSurfaceCommon consistently
This moves the native pixmap fixup to a helper function so we don't
repeat ourselves.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:04:38 +0000 (17:04 -0400)]
egl: Use _eglCreateWindowSurfaceCommon consistently
This moves the native window fixup to a helper function so we don't
repeat ourselves.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 20:42:56 +0000 (16:42 -0400)]
egl: Factor out _eglGetPlatformDisplayCommon
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kyle Brenneman [Mon, 12 Sep 2016 21:12:52 +0000 (17:12 -0400)]
egl: Fix typo
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Adam Jackson [Fri, 9 Sep 2016 17:45:09 +0000 (13:45 -0400)]
egl: Tear down images and syncs at eglTerminate
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Kyle Brenneman [Wed, 6 Jul 2016 16:33:42 +0000 (10:33 -0600)]
egl: Update eglext.h (v2)
Updated eglext.h to revision 33111 from the Khronos repository.
v2:
- Don't (re)move extension includes from eglext.h (Emil Velikov)
- Bump to revision 33111 (Adam Jackson)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Brendan King [Tue, 13 Sep 2016 16:31:05 +0000 (17:31 +0100)]
configure.ac: fix the name of the Wayland Scanner pc file
The Wayland Scanner pkg-config file is called wayland-scanner.pc.
Fixes:
153539bd9d4445b50411 ("configure: rework wayland_scanner
handling (fix make distcheck)")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Signed-off-by: Brendan King <Brendan.King@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Tue, 13 Sep 2016 16:32:39 +0000 (17:32 +0100)]
gbm: remove left-over array
e7c8c85785b3a8f29e3f ("gbm: Removed unused function.") forgot to remove
the global array used only by that function.
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>