radeonsi: inline si_need_gfx_cs_space

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

winsys/amdgpu: clean up amdgpu_cs_check_space

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: simplify si_need_gfx_cs_space

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: inline remaining big functions in draw_vbo for better snx perf

This makes compilation slower, but the perf improvement is ~4%
with pipe_vertex_state.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: simplify memory usage checking by merging vram and gtt counters

no change in behavior

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: use memcmp and radeon_emit_array in radeon_opt_set_context_regn

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: stop using AC_EXP_PARAM_UNDEFINED because it's not useful

Just use AC_EXP_PARAM_DEFAULT_VAL_0000 to keep things simple.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: inline si_get_alpha_test_func

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: move as_ls/es/ngg setting out of si_shader_selector_key

Do it when we bind shaders.

The advantages are:
- no need to memset the fields when any shader variant state is changed
  (e.g. culling on/off)
- no need to recompute the fields every time that happens

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: move si_vgt_stages_key determination into si_update_vgt_shader_config

This simplifies si_update_shaders. It also makes it more obvious that
si_update_shaders could become a C++ template one day.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: remove stages_key parameter from si_shader_selector_key

no change in behavior

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: remove instancing support from the prim discard compute shader

It's not important for workstation apps on Vega.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

radeonsi: remove unused depth_clamp_any

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

mesa: skip draw calls with unaligned indices

GL doesn't say which error we should report. dEQP expects no error and
no crash and allows skipping the call. Some drivers can crash.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5227
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12533>

mesa: fix gl_DrawID with indirect multi draws using user indirect buffer

The code lowered the draws to direct ones but disregarded gl_DrawID.
We need to pass the draw ID to the driver manually.

gl_DrawID is the 3rd parameter of DrawGallium here.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5274
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12533>

mesa: remove unused indices parameter from validate functions

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12533>

lavapipe: VK_KHR_depth_stencil_resolve support

This adds support for depth stencil resolves to lavapipe.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

u_blitter: add support for sample0 only resolves.

This adds support for sample0 only resolves to support lavapipe

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

gallium: add a sample0 only option to blitter.

Vulkan depth/stencil resolves can ask for just sample 0 instead
of averaging. Just add a flag to the state to allow it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

llvmpipe: adjust scissor planes for multisample.

For the inclusive x0/y0 planes, add a half pixel adjustment

For the exclusive x1/y1 planes, remove a half pixel adjustment

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

llvmpipe/scissor: rewrite scissor planes interaction.

This just changes the calcs to be cleaner and easier to interpret.

Adjust the inclusive (x0/y0) by -1 like before, and then flip the
sign for the correct direction.

Add full pixel to the exclusive side after scaling, this is do
show that this value is incorrect and the next patch fixes that
taking multisample into account

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

llvmpipe: consolidate scissor plane code between line/tri

This code is pretty much the same in both, consolidate it.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

llvmpipe/fs: fix multisample depth/stencil fs writes.

The state wasn't storing the shader depth/stencil outputs
per-sample, so only the last sample emitted was being used
for the late depth test and stencil ref.

Noticed while trying to fix some vulkan depth stencil resolve
issues

Fixes: a0195240c44f ("llvmpipe: handle multisample early depth test/late depth write")

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12504>

vbo: check more GL errors when drawing via glCallList

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12265>

vbo: merge draws with GL_LINES regardless of line stippling

see the code comment

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12265>

util/cpu_detect: add/guess support for next Zen CPUs

so that we don't have to update this anymore

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12335>

util/cpu_detect: print num_L3_caches and num_cpu_mask_bits

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12335>

main: allow all external textures for BindImageTexture

According to OES_EGL_image_external_essl3:

  On p. 196 in the errors section for BindImageTexture, replace the
  last error with the following:

    "An INVALID_OPERATION error is generated if <texture> is neither the
     name of an immutable texture object, nor the name of an external
     texture object."

According to OES_EGL_image_external:

  The command

    void EGLImageTargetTexture2DOES(enum target, eglImageOES image);

  with <target> set to TEXTURE_EXTERNAL_OES defines the currently bound
  external texture object to be a target sibling of <image>.

  ...

  If <target> is not TEXTURE_EXTERNAL_OES, the error INVALID_ENUM is
  generated.  (Note: if GL_OES_EGL_image is supported then <target> may
  also be TEXTURE_2D).

Currently, mesa only allows GL_TEXTURE_EXTERNAL_OES textures to be bound
by glBindImageTexture. However, the language of the specification does not
appear to use "external" to refer to GL_TEXTURE_EXTERNAL_OES specifically,
since OES_EGL_image_external allows external eglImageOES to be attached
to GL_TEXTURE_2D in the presence of GL_OES_EGL_image. Thus, it should be
interpreted to refer to all types of external textures, including 2D
textures attached via glEGLImageTargetTexture2DOES.

Fixes: ed43dd62acc ("main: allow external textures for BindImageTexture")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12383>

venus: set maxMipLevels to 1 for ahb images

Fixes: dEQP-VK.api.external.memory.android_hardware_buffer.image_formats.*

Cc: 21.2.2 mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12639>

iris: Map scanout buffers WC instead of WB [v2]

The scanout engine is not coherent with rendering, so make sure
scanout buffers are mapped WC. This ensures that CPU rendering as done
by the Xserver gets flushed to the frame buffer immediately instead of
waiting for some future time.

v2:
    Also mark shared buffers to be allocated for scanout
    in case they are being used for scanout elsewhere.

Signed-off-by: Keith Packard <keithp@keithp.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5231
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12259>

venus: fix device group enumeration with unsupported devices

instance->physical_devices includes only supported devices, not all
devices.  One example is that it does not include 1.0 devices.  We need
to fix up VkPhysicalDeviceGroupProperties to exclude unsupported
devices.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12637>

venus: pre-initialize device groups

We don't need to worry about how vkEnumeratePhysicalDeviceGroups is
called (props is NULL, props is non-NULL but count is 0, etc.) this way.
It also allows us to fix up VkPhysicalDeviceGroupProperties easily.

v2: let the for-loop increment (Yiwei)

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org> (v1)
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12637>

venus: minor cleanup to physical device init loop

v2: let the for-loop increment (Yiwei)

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org> (v1)
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12637>

ir3/ra: Fix type mismatch when comparing intervals

This was once a physreg, back in the very beginning of the new RA, but
now the caller passes an unsigned int.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5163
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>

ir3: Make ir3_register::name 32-bits

It was overflowing with
dEQP-VK.spirv_assembly.instruction.compute.spirv_ids_abuse.lots_ids.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>

ir3: Make instruction IP 32 bits

a6xx supports shaders with more than 64k dwords, or at least the shader
size register has increased in size, and the matching name is gone so
there's no reason to be clever here. This doesn't fix anything at the
moment.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>

ir3: Remove ir3_instr::name

Unused since the switch to new RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12487>

nir_to_tgsi: Use explicit sizes of NIR variables for UBO declarations.

This fixes duplicate CB0 declarations, missing interface array
declarations, and too-low sizes of UBOs containing multiple nir_variables.

Closes: #4810
Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12175>

nir/nir_lower_uniforms_to_ubo: Set the explicit stride of the UBO 0 uniform.

Normal UBOs have explicit strides on them, make our lowered one behave the
same.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12175>

nir: Set .driver_location for GLSL UBO/SSBOs when we lower to block indices.

Without this, there's no way to match the UBO nir_variable declarations to
the load_ubo intrinsics referencing their data.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12175>

anv: Enable KHR_shader_integer_dot_product

For now, only mark the 4x8BitPacked variants as accelerated.

Applications are unlikely to use the "add with saturate" opcodes from
VK_INTEL_shader_integer_functions2, so, technically, all of the
AccumulatingSaturating variants "[provide] a performance advantage over
user-provided code composed from elementary instructions..." on all
Intel platforms.  If we encounter an application that cares, we can do
things differently then.  Ditto for the non-packed 8Bit, 4-element
vector variants.

v2: Don't memset props as this also zeros sType and pNext.  Noticed by
Georg Lehmann in !12617.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12624>

zink: ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

docs: mark off ES 3.2 for zink

blammo

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: enable fbfetch pipe cap

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: add a renderpass flag for input attachment layout handling

this has special requirements

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: update push descriptor set anytime fbfetch changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: add an input attachment to the gfx push set layout to handle fbfetch

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: fix lazy descriptor deinit

this used to be the right conditional, but it's not anymore

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: add an input attachment to the gfx push set layout to handle fbfetch

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: flag color attachment images as input attachments at creation

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: track fbfetch info on context, update as needed

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: refactor descriptor layout/template creation a little

make the push sets more flexible

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: add a compiler pass to translate fbfetch -> input attachments

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: emit fbfetch variables as ntv input attachments

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: add input attachment thingy for spirv builder

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12603>

zink: move alphaToOne warning to a dynamic warning

stop spamming these if they aren't even being used

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12647>

ci/llvmpipe: Add a fractional ASan run.

This reproduces #5254 and seems like a good idea to be checking normally.

I think running some desktop GL would also be useful here, but it turns
out that desktop glcts is pretty leaky/overflowy inside of deqp.

Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12493>

mesa: add environment variable MESA_NO_SHADER_REPLACEMENT

for performance comparisons

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12492>

meson: add missing custom target to generate shader_replacement.h

for custom shader replacements enabled by -Dcustom-shader-replacement=path.
process_shaders.py should generate shader_replacement.h, which should
contain shaders and their substitutions.

Loosely based on Pierre-Eric's commit.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12492>

virgl/ci: enable some traces that were previously crashing

Most of these are fixed in recent mesa and virglrenderer versions, but
some might still be flaky. We'll keep an eye on them and if they are
flaky we can disable them.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12643>

virgl/ci: stop overriding GL version when running traces

These environment variables make some traces that require higher GLSL
versions crash.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12643>

ci: Ensure the DRM device is open

... before changing the PM settings.

Otherwise, we hit a kernel warning in Qualcomm devices and the device is
left in a non-functional state.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12644>

aco: remove DPP when applying constants/literals/sgprs

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12601>

aco/tests: test copy propagation with DPP instructions

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12601>

aco: don't constant propagate to DPP instructions

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12601>

radeon/vcn: add a handling of error for incorrect reference lists

Use the first dpb buffer instead of the NULL pointer sent to hardware.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12610>

radeon/vcn: reuse the dpb buffers when with the same size.

To avoid allocate/deallocate frequently.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12610>

gallium: fix surface->destroy use-after-free

regen surface on every update framebuffer

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: liuyujun <liuyujun@uniontech.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12520>

intel/fs: fix framebuffer reads

We're missing some restrictions on those messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5292
Cc: mesa-stable
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12615>

meson: add crocus to default group of drivers for x86/x86_64

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12636>

radv/llvm: fix invalid IR when converting triangle strips to indices

Operand 0 of LLVMBuildSelect() should be i1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12616>

ac/llvm: fix huge alignment when loading from shared memory

LLVM doesn't support huge alignments, also it can optimize the shared
loads, so it's unecessary to emit better (but broken) LLVM IR.

Fixes a bunch of crashes with RADV_DEBUG=llvm,checkir.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12616>

ac/llvm: adjust assertion for nir_intrinsic_terminate

Fixes dEQP-VK.spirv_assembly.instruction.terminate*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12616>

meson: fix regression finding shm dep

Just copy the dep into both places.

Fixes: b5c390c113d3 ("vulkan/wsi: add support for detecting mit-shm pixmaps.")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12635>

zink: explicitly end renderpass before running dispatch

it's possible that nothing will end the renderpass otherwise

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12581>

freedreno/ci: Bring fd farm back online after move

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12608>

zink: use VK_WHOLE_SIZE for full-sized bufferviews

this works around most cts coverage which violates spec by creating a view
sized using a range that isn't a multiple of the format's blocksize

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12631>

zink: free local shader nirs on program free

leak--

Fixes: 61f2667cf5d ("zink: remove gfx program slot mapping")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12630>

intel/fs: Remove type-based restriction for cmod propagation to saturated operations

Previously, we misunderstood how conditional modifiers and saturate
interacted.  We thought the condition was evaulated before the saturate
was applied.  For the floating point cases, we went to some heroics to
modify the condition to maintain the same results.  For integer cases,
it was not clear that this could even work.  We had no use-cases and no
tests-cases, so we just disallowed everything.

Now we understand that the condition is evaluated after the saturate.
Earlier commits in this series removed the various floating point
heroics.  It is easier to just delete the code that prevents some cases
that just work.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: Remove after parameter from test_saturate_prop

Originally this was part of "intel/fs: Remove condition-based
restriction for cmod propagation to saturated operations".  With some
additional changes to that commit, it caused a lot of extra churn in the
unit tests.  I felt that made it harder to see the actual changes in the
unit tests, so I split it out.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: Remove condition-based restriction for cmod propagation to saturated operations

I don't know why the float_saturate_l_mov test was #if'ed out, but it
passes... so this commit enables it.

No shader-db or fossil-db changes.

In a previous iteration of this MR, this commit helped ~200 shaders in
shader-db.  Now all of those same shaders are helped by "intel/fs: cmod
propagate from MOV with any condition".  All of these shaders come from
Mad Max.  After initial translation from NIR to assembly, these shader
contain patterns like:

    mul(8)            g90<1>F       g88<8,8,1>F     0x40400000F  /* 3F */
    ...
    mov.sat(8)        g90<1>F       g90<8,8,1>F
    ...
    cmp.nz.f0(8)      null<1>F      g90<8,8,1>F     0 /* 0F */

An initial pass of cmod propagation converts this to

    mul(8)            g90<1>F       g88<8,8,1>F     0x40400000F  /* 3F */
    ...
    mov.sat.XX.f0(8)  g90<1>F       g90<8,8,1>F

Without this commit, XX is G.  With this commit, XX is NZ.  Saturate
propagation moves the saturate:

    mul.sat(8)        g90<1>F       g88<8,8,1>F     0x40400000F  /* 3F */
    ...
    mov.XX.f0(8)      g90<1>F       g90<8,8,1>F

Without this commit (but with "intel/fs: cmod propagate from MOV with
any condition"), the G gets propagated:

    mul.sat.g.f0(8)   g90<1>F       g88<8,8,1>F     0x40400000F  /* 3F */

With this commit (with or without "intel/fs: cmod propagate from MOV
with any condition"), the NZ gets propagated:

    mul.sat.nz.f0(8)  g90<1>F       g88<8,8,1>F     0x40400000F  /* 3F */

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: cmod propagate from MOV with any condition

There were tests related to propagating conditional modifiers from a MOV
to an instruction with a .SAT modifier for a very long time, but they
were #if'ed out.

There are restrictions later in the function that limit the kinds of MOV
instructions that can propagate.  This avoids the dangers of
type-converting MOVs that may generate flags in different ways.

v2: Update the added comment to look more like the existing comment.
That makes the small differences between the two cases more obvious.
Noticed by Marcin.

All Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 19827127 -> 19826924 (<.01%)
instructions in affected programs: 62024 -> 61821 (-0.33%)
helped: 201
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.01 x̃: 1
helped stats (rel) min: 0.13% max: 0.60% x̄: 0.35% x̃: 0.36%
95% mean confidence interval for instructions value: -1.02 -1.00
95% mean confidence interval for instructions %-change: -0.36% -0.34%
Instructions are helped.

total cycles in shared programs: 954655879 -> 954655356 (<.01%)
cycles in affected programs: 1212877 -> 1212354 (-0.04%)
helped: 155
HURT: 6
helped stats (abs) min: 1 max: 6 x̄: 3.65 x̃: 4
helped stats (rel) min: <.01% max: 0.17% x̄: 0.07% x̃: 0.07%
HURT stats (abs)   min: 2 max: 12 x̄: 7.00 x̃: 8
HURT stats (rel)   min: 0.04% max: 0.23% x̄: 0.14% x̃: 0.15%
95% mean confidence interval for cycles value: -3.60 -2.90
95% mean confidence interval for cycles %-change: -0.07% -0.05%
Cycles are helped.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/compiler: Move type_is_unsigned_int to brw_reg_type.h

...and rename it to brw_reg_type_is_unsigned_integer.  It is now next to
brw_reg_type_is_floating_point and brw_reg_type_is_integer.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: Fix a cmod prop bug when the source type of a mov doesn't match the dest type of scan_inst

We were previously operating with the mindset "a MOV is just a compare
with zero."  As a result, we were trying to share as much code between
the MOV path and the CMP path as possible.  However, MOV instructions
can perform type conversions that affect the result of the comparison.
There was some code added to better handle this for cases like

    and(16)         g31<1>UD       g20<8,8,1>UD   g22<8,8,1>UD
    mov.nz.f0(16)   null<1>F       g31<8,8,1>D

The flaw in these changed special cases is that it allowed things like

    or(8)           dest:D  src0:D  src1:D
    mov.nz(8)       null:D  dest:F

Because both destinations were integer types, the propagation was
allowed.  The source type of the MOV and the destination type of the OR
do not match, so type conversion rules have to be accounted for.

My solution was to just split the MOV and non-MOV paths with completely
separate checks.  The "else" path in this commit is basically the old
code with the BRW_OPCODE_MOV special case removed.

The new MOV code further splits into "destination of scan_inst is float"
and "destination of scan_inst is integer" paths.  For each case I
enumerate the rules that I belive apply.  For the integer path, only the
"Z or NZ" rules are listed as only NZ is currently allowed (hence the
conditional_mod assertion in that path).  A later commit relaxes this
and adds the rule.

The new rules slightly relax one of the previous rules.  Previously the
sizes of the MOV destination and the MOV source had to be the same.  In
some cases now the sizes can be different by the following conditions:

  - Floating point to integer conversion are not allowed.

  - If the conversion is integer to floating point, the size of the
    floating point value does not matter as it will not affect the
    comparison result.

  - If the conversion is float to float, the size of the destination
    must be greater than or equal to the size of the source.

  - If the conversion is integer to integer, the size of the destination
    must be greater than or equal to the size of the source.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: Add many cmod propagation tests involving MOV instructions

Of particular interest are the tests where the MOV performs a type
conversion.  If the restriction on conditional modifier for a MOV is
ever relaxed, some of these cases must still be disallowed.

v2: s/NZ/Z/ in one of the comments.  Notice by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: Remove redundant inst->opcode checks in cmod prop

This foreach_inst_in_block_reverse_starting_from loop only applies
CMP, MOV, and AND.  AND instructions break out of the loop before this
point.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

intel/fs: Refactor some cmod propagation tests

This will simplify some later changes to these tests.

v2: Combine test_positive_saturate_prop and test_negative_saturate_prop
into a single function.  Suggested by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12045>

radv: ignore dynamic line stipple if line stipple isn't enabled

==244108== Conditional jump or move depends on uninitialised value(s)
==244108==    at 0x48498D5: bcmp (vg_replace_strmem.c:1129)
==244108==    by 0x1C37B7DD: radv_bind_dynamic_state (radv_cmd_buffer.c:237)
==244108==    by 0x1C388027: radv_CmdBindPipeline (radv_cmd_buffer.c:4794)
==244108==    by 0x14E9C01E: bool update_gfx_pipeline<true>(zink_context*, zink_batch_state*, pipe_prim_type) (zink_draw.cpp:406)
==244108==    by 0x14E9AAB9: void zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)1, (zink_dynamic_state2)1, (zink_dynamic_vertex_input)1, true>(pipe_cont>
==244108==    by 0x14B017EB: tc_call_draw_single (u_threaded_context.c:3033)
==244108==    by 0x14AF9C0E: tc_batch_execute (u_threaded_context.c:190)
==244108==    by 0x14AFA24F: _tc_sync (u_threaded_context.c:341)
==244108==    by 0x14B006E7: tc_texture_subdata (u_threaded_context.c:2549)
==244108==    by 0x14238F8C: st_TexSubImage (st_cb_texture.c:2134)
==244108==    by 0x14239931: st_TexImage (st_cb_texture.c:2363)
==244108==    by 0x1453698A: teximage (teximage.c:3154)
==244108==    by 0x1453698A: teximage_err (teximage.c:3181)
==244108==    by 0x145388BD: _mesa_TexImage2D (teximage.c:3252)
==244108==    by 0x5E88D4: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5E9527: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5E9B72: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5F1092: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x5F10AC: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x48CC66: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x48DDC7: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x40D525: ??? (in /home/zmike/src/piglit/tesseract/bin_unix/linux_64_client)
==244108==    by 0x4FF7B74: (below main) (in /usr/lib64/libc-2.33.so)
==244108==  Uninitialised value was created by a stack allocation
==244108==    at 0x14ECDF55: zink_create_gfx_pipeline (zink_pipeline.c:53)

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12618>

radv: use pool stride when copying single query results

the specified stride is irrelevant for this case since there's only one
result to write

Cc: mesa-stable
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12619>

radv: advertise VK_EXT_primitive_topology_list_restart

Everything should be already supported, except patch list.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12611>

vulkan: Update the XML and headers to 1.2.190

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12611>

svga/drm: use pb_usage_flags instead of pipe_map_flags in vmw_svga_winsys_buffer_map

This patch basically maps pipe_map_flags to pb_flags. Since we are mapping it,
STATIC_ASSERTS won't be required.

Fixes: 00c30dad78b0 ("gallium: renumber PIPE_MAP_* enums to remove holes")

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12606>

radv: add support for clearing multi layers with normal gfx clear path

Allow to clear range of layers with vkCmdClear{Color,DepthStencil}Image().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12557>

ci: Fix a minor issue in prepare-artifacts.sh script

bash is whitespace sensitive.
https://github.com/koalaman/shellcheck/wiki/SC1020

This was noticed from the logs of a CI job
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/13158779
There was no fallout from this bug as not having this variable defined
leads to the right behavior, and defining it to 1 leads to a error
which consequently also leads to the right behaviour.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12562>

aco: include utility in isel

For std::exchange().

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: c1d11bb92c9 ("aco: Add loop creation helpers.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5301
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12614>

nir: Fix local_invocation_index upper bound for non-compute-like stages.

The lowered LS and NGG stages use local_invocation_index and they
can benefit from the unsigned upper bound because they can emit a
less expensive integer multiplication instruction.
This was working in the past, but accidentally borked by a refactor.

Fossil DB changes on Sienna Cichlid:

Totals from 956 (0.74% of 128647) affected shaders:
CodeSize: 2354172 -> 2344712 (-0.40%)
Instrs: 434359 -> 434327 (-0.01%)
Latency: 1883949 -> 1876814 (-0.38%)
InvThroughput: 762638 -> 757405 (-0.69%)

Fossil DB changes on Sienna Cichlid (with NGGC enabled):

Totals from 57873 (44.99% of 128647) affected shaders:
CodeSize: 155844192 -> 155607064 (-0.15%)
Instrs: 29799184 -> 29799152 (-0.00%)
Latency: 130959764 -> 130814224 (-0.11%); split: -0.11%, +0.00%
InvThroughput: 21100300 -> 20928635 (-0.81%); split: -0.81%, +0.00%

Fixes: 8af6766062044167fb3b61950ddbc7d67e4c3e48
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>

nir: Add unsigned upper bound for extract opcodes.

This helps with some cases of extract, such as:
- Emitting more optimal integer multiplications
- Better address calculation
- Possibly others

Fossil DB results on Sienna Cichlid:

Totals from 4064 (3.16% of 128647) affected shaders:
VGPRs: 262040 -> 262032 (-0.00%)
CodeSize: 28856648 -> 28811892 (-0.16%); split: -0.18%, +0.02%
Instrs: 5370279 -> 5367827 (-0.05%); split: -0.08%, +0.04%
Latency: 74230112 -> 74016671 (-0.29%); split: -0.29%, +0.01%
InvThroughput: 12082532 -> 12036365 (-0.38%); split: -0.39%, +0.01%
VClause: 108506 -> 108721 (+0.20%); split: -0.03%, +0.22%
SClause: 217731 -> 216602 (-0.52%); split: -0.67%, +0.15%
Copies: 265689 -> 270811 (+1.93%); split: -0.26%, +2.19%
PreSGPRs: 201982 -> 204907 (+1.45%); split: -0.01%, +1.46%
PreVGPRs: 236099 -> 236079 (-0.01%)

Fossil DB results on Sienna Cichlid with NGGC enabled:

Totals from 60375 (46.93% of 128647) affected shaders:
VGPRs: 2212576 -> 2212568 (-0.00%)
CodeSize: 180870420 -> 179684816 (-0.66%); split: -0.66%, +0.00%
Instrs: 34386715 -> 34213682 (-0.50%); split: -0.51%, +0.01%
Latency: 199676290 -> 198987998 (-0.34%); split: -0.35%, +0.00%
InvThroughput: 32288299 -> 31736433 (-1.71%); split: -1.71%, +0.00%
VClause: 621521 -> 621743 (+0.04%); split: -0.00%, +0.04%
SClause: 900447 -> 899392 (-0.12%); split: -0.16%, +0.04%
Copies: 3439529 -> 3445305 (+0.17%); split: -0.02%, +0.19%
PreSGPRs: 2216297 -> 2219220 (+0.13%); split: -0.00%, +0.13%
PreVGPRs: 1842887 -> 1842867 (-0.00%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>

aco: Unset 16 and 24-bit flags from operands in apply_extract.

Consider the following sequence in a shader:
b = p_extract a
c = v_mad_u32_u16 b, X, 0

The optimizer applies extract, resulting in:
c = v_mad_u32_u16 a, X, 0 (correct)

Then it mistakenly turns that into:
c = v_mul_u32_u24 a, X, 0 (incorrect)

In this case, the p_extract is applied to v_mad_u32_u16 by
apply_extract. After this, we can no longer be sure that
the operands are still 16 or 24-bit, so we have to remove
this flag.

No Fossil DB changes.

Fixes: 54292e99c7844500314bfd623469c65adef954c5
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12558>

zink: implement PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY when resizable bar not present

this helps in some cases to avoid allocating and mapping large staging resources

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12579>