panvk: Fixes -Werror,-Wunused-but-set-variable for clang-15 in panvk_descriptor_set.c

../../src/panfrost/vulkan/panvk_descriptor_set.c:67:13: error: variable 'dynoffset_idx' set but not used [-Werror,-Wunused-but-set-variable]
   unsigned dynoffset_idx = 0, img_idx = 0;
            ^

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19875>

loader: fixes -Werror,-Wdeprecated-non-prototype for clang-15 in pipe-loader

There are multiple error messages, show one of them:
../../src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c:219:54: error: passing arguments to a function without a prototype is deprecated in
all versions of C and is not supported in C2x [-Werror,-Wdeprecated-non-prototype]
         sdev->ws = sdev->dd->winsys[i].create_winsys(drisw_lf);
                                                     ^

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19875>

d3d12/ci: Update expectations

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

dzn: Swizzle SRV access to stencil

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

dzn: Pass input clip size to shader compilation

For cases where both clip and cull are used, and a shader has both
inputs and outputs that can contain them, we need metadata to tell
us where the clip array ends and the cull array begins, since they
get combined into CLIP location registers. For outputs, this is in
the nir info, but for input we pass it in a sideband channel.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

dzn: Don't add UAV flag to DSV textures

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

dzn: Use ResolveSubresourceRegion to support non-averaging resolve modes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

dzn: Use driver-implemented triangle fans if available

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

dzn: Get options15

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

microsoft/compiler: Handle cull distance starting fractional with no previous clip

This can happen if the clip distance was declared, but was discarded as an
unused variable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

microsoft/compiler: Sort all user varyings before any sysvals

User varyings are linked by both name and register. The name is based
on how many *variables* are before it in final driver_location sort
order, not necessarily how many registers are before it.

In some cases where clip/cull distance are involved, it's possible
for one shader to write into a part of the cull distance that's
ignored by a downstream shader, but because linking is done by
*whole* register locations, and clip/cull can be combined using
*fractional* register locations, this is hard to detect. Since no
non-sysvals end up using fractional locations, just put all non-sysvals
first so they always generate the same semantic names for the same
register locations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

microsoft/compiler: Make nir_var_to_dxil_sysvalue_type static

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

microsoft/compiler: Handle both input and output clip/cull distances

For clip/cull coming into a GS and being written, this pass was wrong
and would modify variable types incorrectly. Track both inputs and
outputs separately.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20346>

panfrost: Don't use texture format swizzles on v7

They're too restricted for AFBC. Fix up instead. There are two problems at play:

1. We can't just map the format swizzle to the pixel format ordering on v7,
   because the "reordered" values aren't allowed with compression.
2. We can't just compose the format swizzle with the API swizzle, because the
   composed swizzle is applied to the border colour, so we need to be able to
   apply an inverted swizzle to the border colour. That only works for bijective
   format swizzles.

Fortunately, there's a neat solution: decompose the format's swizzle into two
swizzles, the first mapping to a reordering that IS allowed for compression, and
the second a bijection. Then we use the allowed reordering when texturing, apply
the bijective swizzle to the API swizzle, and apply the inverse of the bijective
swizzle to the border colour. When we're sampling a border colour, what's now
happening mathematically is:

   (API swizzle o bijective swizzle)((bijective swizzle^-1)(border colour)) =
   (API swizzle o (bijective swizzle o bijective swizzle^-1))(border colour) =
   API swizzle(border colour)

which is exactly what we wanted.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

panfrost: Allow swizzled AFBC on v9+

On v6 and earlier, the hardware supports arbitrary format swizzles for AFBC, so
there's no restriction on AFBC. On v8 and newer, the format swizzle gets applied
to the *decompressed* interchange format, so we can effectively support BGRA of
AFBC images without any special handling. (Confirmed working on v9. Obviously I
can't test on v8 but the expression is cleaner if we assume optimistically it's
like v9. Without hardware, we get to make that assumption :-p)

That just leaves v7 as the only architecture where format swizzles are
restricted for compression but there are no plane descriptor. Don't apply the
restriction to the newer parts.

This gets us AFBC of window surfaces on v9+. As the limiting case, fullscreen
glmark2-es2-wayland -btexture (1080p) in sway on Mali-G57 from 1300fps to
2353fps.

45% reduction in frame time is nothing to sneeze at.

Achoo.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

panfrost: Introduce pan_afbc_mode

Introduce an enum to represent an AFBC compression mode. These modes are not
formats, on Valhall they are decoupled from the format. As such, it does not
make sense to use a pipe_format to represent them. Add an enum that we can use
in a straightforward way on Midgard and Bifrost to fallback for texture views,
and can map 1:1 to the Valhall hardware enum.

In addition to being less overloaded semantically, this lets -Wswitch kick in to
ensure that we handle all enums when translating. The straightforward
translation raises the following warnings:

../src/panfrost/lib/pan_cs.c:437:9: warning: enumeration value ‘PAN_AFBC_MODE_R5G5B5A1’ not handled in switch [-Wswitch]
  437 |         switch (panfrost_afbc_format(PAN_ARCH, format)) {
      |         ^~~~~~

...indicating that some formats were missed, leading to assertion fails "unknown
canonical AFBC format" when rendering RGB5A1, which dEQP-GLES31 does. Fixes
regressions in
dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.*
on Valhall.

Given how scarce v9 hardware is, that v10 isn't upstream yet, and the offending
code was merged a week ago, this should not have actually affected anyone. At
any rate, it's a good reminder we really do need CI for v9...

Fixes: 8e125b6c15b ("panfrost: Enable AFBC of more formats")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

panfrost: Luminance-alpha AFBC unsupported on v7+

The L8_UNORM, A8_UNORM, and L8A8_UNORM v7 formats do not support AFBC,
regardless of swizzling. We're about to lift the restrictions on swizzling with
AFBC on v7, so we'll need to handle these cases explicitly to avoid using AFBC
in these cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

panfrost: Align WSI strides for tiled AFBC

When calculating legacy WSI strides for tiled AFBC, we need to account for the
greater alignment requirement of tiled AFBC, or importing resources will fail
later.

Since tiled AFBC is only supported on v7 and later, and AFBC of window surfaces
isn't being used on Linux on v7 and later, this probably hasn't been hit in
practice. Probably.

We're about to fix AFBC of window surfaces so we need to fix this side first.

Fixes: 0255f554f39 ("panfrost: Advertise 16x16 tiled AFBC")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

panfrost: Remove panfrost_blit_format

Trivial.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

panfrost: Remove RGTC emulation relic

u_transfer_helper no longer emulates RGTC, so this code path is dead. RGTC
emulation now happens in the state tracker so the formats will work out
properly. (Similar to how other BCn formats are emulated in mesa/st.)

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

asahi: Remove agx_blit_format

Copied from panfrost, decopy the useless.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>

radv/ci: add yet another pipeline barrier test as flake

https://gitlab.freedesktop.org/mesa/mesa/-/jobs/33638274

Also add a few similar tests.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20359>

radv/gfx11: enable VK_AMD_shader_explicit_vertex_parameter

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20341>

ac/llvm/gfx11: implement load_input_vertex

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20341>

aco/gfx11: implement load_input_vertex

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20341>

OpenCL/draw module: Support linking with LLVM and clang 15 static libraries

Cc: mesa-stable
Closes: #7243

Closes: #7487

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19009>

radv: enable graphicsPipelineLibraryIndependentInterpolationDecoration

They don't need to match.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20202>

radv: enable graphicsPipelineLibraryFastLinking

I think fast-linking could be improved a lot but this allows to test
GPL with Zink (RADV_PERFTEST=gpl + ZINK_DEBUG=gpl).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20202>

radv: import compiled binaries from libraries only when fast-linking is enabled

When VK_PIPELINE_CREATE_LINK_TIME_OPTIMIZATION_BIT_EXT is used, the
pipeline includes a complete set of state specified entirely by
libraries. That means that we should skip using compiled binaries
(including PS epilogs) and we should create an optimized pipeline.

Found this with Zink because RADV was creating two pipelines with the
same PS epilog, while the optimized one shouldn't use any PS epilog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20202>

radv/gfx11: disable mesh shaders

Even if the perftest is used, these should be disabled on GFX11. We
don't implement it yet

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20358>

aco/gfx11: export mrtz in discard early exit for non-color shaders

If a shader doesn't export any color targets and instead only exports
mrtz, the discard early exit block should match.

Fixes artifacts on Lara in Rise of the Tomb Raider benchmark and hair in
The Witcher 3 (classic).

https://reviews.llvm.org/D128185

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: bc8da20dda6 ("aco: export MRT0 instead of NULL on GFX11")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20345>

zink: fix line-smooth interpolation

Extending the lines by half a pixel in each direction without doing
anything about the varyings makes the varyings interpolate over a
distance than intended. While this can be negligeble for long lines,
it can lead to big error for short lines.

Let's instead add extra geometry for each of the line-caps, so we can
make sure the varyings stay constant for the whole cap, and interpolate
over the intended distance instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19847>

zink: lower smooth-lines if not supported

This implements line-smoothing the same way as the draw-module does,
except using a geometry shader instead of a CPU pass.

Ideally, this should be enabled either by checking for the various
smooth-line caps, or by a DRIconf setting.

Unfortunately, RADV doesn't support he smooth-lines features, and we
don't want to force it down a pessimistic shader-key code-path. So that
plan is out the window for now.

While DRIconf is also neat, it's a bit of work to wire up, and we don't
really know of any real-world applications who would need this yet. So,
for now, let's just unconditionally enable is on the IMG proprietary
driver, which is going to need this for sure.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19847>

zink: add line-smooth lowering passes

These passes implements basically the same logic as draw_pipe_aaline.c
does, but using geometry shaders instead of doing it CPU-side.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19847>

zink: fix line-stipple varying allocation

This was really derpy. There's two things wrong; first of all, we should
pick at LEAST VARYING_SLOT_VAR0, second, util_last_bit64 returns one
more than the index of the bit already, so we don't want to add twice
here.

Fixes: 4b17c099ca4 ("zink: add line-stippling lowering passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19847>

r600/sfn: Check possibility of channel switching also for trans-slot

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7878

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20355>

r600: don't try to serialized shaders translated from TGSI

TTN seems to have a problem encoding vec4[4] correctly, so that
serialization might fail.

Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7891

Fixes: 5b205ef (r600: Store nir shaders serialized to save memory)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20355>

ci: allow omitting of --rev for ci_run_n_monitor.py

When --rev is omitted, try to get revision automatically.

Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20271>

ci: ci_run_n_monitor fix Unicode log parsing

Fixes issues as  `...truncated \ xXX escape` while parsing the log.

Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20271>

v3dv: be more careful when restoring dirty state after meta operations

So far we have been only restoring dirty dynamic states used by meta
pipelines however, static state from meta pipelines will also clear
dirty flags, preventing follow-up draw calls in the command buffer
to honor these if they are flagged as dynamic states in their
pipelines. Fix this by always resetting all dirty state flags after
a meta operation so we re-emit all the state we need with the next draw
call.

Fixes:
dEQP-VK.dynamic_state.monolithic.image.clear

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20356>

v3dv: pipeline creation feedback may not request all stages

Nothing in the spec seems to require that the number of stages for
which creation feedback is requested must match the number of stages
available in the pipeline. In fact, the spec explicitly mentions
that this number could be 0:

   "If pipelineStageCreationFeedbackCount is not 0,
    pPipelineStageCreationFeedbacks must be a valid pointer to an
    array of pipelineStageCreationFeedbackCount
    VkPipelineCreationFeedback structures"

Fixes an assert crash in:
dEQP-VK.pipeline.monolithic.creation_feedback.graphics_tests.vertex_stage_fragment_stage_no_cache_zero_out_feedback_cout

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20352>

egl/wayland: Prefer back buffer with minimum buffer age

This may allow applications making use of buffer age to save some effort
in some cases.

v2: (Simon Ser)
* Add space between struct member and "<" operator.
* Remove break statement which prevented the change from working as
  intended in swrast_update_buffers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18269>

loader/dri3: Simplify new buffer allocation in dri3_find_back

We can find the idle buffer with lowest buffer age or the first
unallocated slot in the same loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18269>

loader/dri3: Find idle buffer with minimum buffer age in dri3_find_back

This may allow applications making use of buffer age to save some effort
in some cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18269>

loader/dri3: Clean up dri3_find_back logic

No need to go through the loop again for allocating a new buffer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18269>

zink: lower mem_global to scalar

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20106>

nir_lower_io_to_scalar: handle load/store_global

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20106>

nir_lower_io_to_scalar: make use of nir_get_io_offset_src

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20106>

v3dv: honor render area in subpass resolve fallback

When falling back to handling subpass resolves via separate
image resolves we were resolving the entire attachment instead
of limiting the resolve to the render area defined for the render
pass.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>

v3dv: handle depth/stencil resolves we can't implement via TLB

If we can't use the TLB to do a subpass resolve we have a fallaback
that emits separate image resolves, but this fallback was only
handling color resolves. This adds depth/stencil as well.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>

v3dv: don't resolve by averaging samples on depth/stencil resolves

For these we always want to use sample_0, averaging is reserved for
color formats. We were already doing this correctly for depth/stencil
resolved in render passes, but not for those happening through
vkCmdResolveImage.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>

v3dv: always store/restore attachment state during meta operations

attachment state is only relevant during render passes, however,
there is a corner case: if we can't resolve an attachment in a
subpass using the hardware, we emit a manual image resolve in the
driver which can trigger a meta operation via blit. In this case,
we pretend we are not in a render pass (since vulkan disallows
blits/resolves in a render pass) but we really want to keep the
attachment state after the meta operation.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>

anv: Use vma_heap for descriptor pool host allocation

Pre-patch, anv_descriptor_pool used a free list for host allocations
that never merged adjacent free blocks.  If the pool only allocated
fixed-sized blocks, then this would not be a problem. But the pool
allocations are variable-sized, and this caused over half of the pool's
memory to be consumed by unusable free blocks in some workloads, causing
unnecessary memory footprint.

Replacing the free list with util_vma_heap, which does merge adjacent
free blocks, fixes the memory explosion in the target workload.

Disdavantges of util_vma_heap compared to the free list:
  - The heap calls malloc() when a new hole is created.
  - The heap calls free() when a hole disappears or is merged with an
    adjacent hole.
  - The Vulkan spec expects descriptor set creation/destruction to be
    thread-local lockless in the common case. For workloads that
    create/destroy with high frequency, malloc/free may cause overhead.
    Profiling is needed.

Tested with a ChromeOS internal TensorFlow benchmark, provided by
package 'tensorflow', running with its OpenCL backend on clvk.

  cmdline: benchmark_model --graph=mn2.tflite --use_gpu=true --min_secs=60
  gpu: adl
  memory footprint from start of benchmark:
    before: init=132.691MB max=227.684MB
    after:  init=134.988MB max=134.988MB

Reported-by: Romaric Jodin <rjodin@google.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20289>

util/vma: Track size of free memory in heap

This allows users to detect fragmentation on allocation failure.
If heap allocation fails but the allocation size is not larger than the
total free size, then the allocation failed due to fragmentation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20289>

Revert "anv: Refactor anv_pipeline to use the anv_pipeline_type"

This reverts commit b1126abb38a5ff4a10c4c3240d01c22c1fb90c1b.

This breaks all hell at least on DG2, as there are several cases left
where current_pipeline gets checked against GPGPU to decide what to do,
and the value doesn't match that of ANV_HW_PIPELINE_STATE_COMPUTE.
On top of that, it also misses checking for
ANV_HW_PIPELINE_STATE_RAYTRACING.

Then there's the fact that in some cases, current_pipeline will be
UINT32_MAX, because it's the original undefined state and also used
after executing a secondary command buffer because we are not tracking
on which pipeline did the secondary left us.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7910
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20349>

iris: Don't reject CPU access for non-invalidating buffer write maps

Buffer maps that don't invalidate their destination range work better
as direct CPU maps than staging blits.  The application may write only
part of the range, effectively combining the new data with existing
data.  So even if the map would stall, the staging blit path won't help
us, as we have to read the existing data to populate the staging buffer
before returning it.  This incurs a stall anyway - plus a read and copy.

In contrast, a direct map doesn't need to read any data - it can just
write the destination and the existing data will still be there.

Fixes excessive blits for stalling buffer writes that don't invalidate
the buffer since my recent map heuristic rework.

Fixes: bec68a85a2d ("iris: Improve direct CPU map heuristics")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7895
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20330>

anv: remove some gen8 specifics handled now in hasvk

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20342>

ci: restore reliable Alpine 3.16

Alpine 3.17 suffered random freezes.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20294>

iris: Check for zero in clear color compatibility fn

Both formats may interpret the clear color as zero.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20320>

d3d12: Add ASSERTED to variables only used in debug builds to fix build MSVC with C4189 errors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20340>

intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>

intel/dev: Enable AUX map on MTL

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>

intel/aux_map: Ignore format bits when using tile-4

Based on Jianxun's ("iris: don't get format bits in AUX tables").

With gfx12.5+, the compression format is once again coming from the
surface state programming. MTL once again uses an aux-map, but it
ignores the format bits within the the aux-map metadata.

Ref: Bspec 44930: "Compression format from AUX page walk is ignored.
Instead compression format from Surface State is used."

gfx12.5+ also uses tile-4 rather than y-tiling, so if we don't see
y-tiling, we can return 0 from intel_aux_map_format_bits() for the
ignored format bits.

Rework:
 * Just return 0 if not using y-tiling as suggested by Nanley.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>

iris/resource: Check devinfo::has_local_mem before using BO_ALLOC_LMEM

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>

iris: Nuke dead IRIS_CONTEXT* macros

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19650>

iris: Nuke flags from iris_bufmgr that can read from devinfo

Now that devinfo is stored in iris_bufmgr we can nuke this duplicated
flags.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19650>

iris: Only fetch intel_device_info once per bufmgr

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19650>

iris: Store intel_device_info in iris_bufmgr

We can have multiple pipe_screen but only one iris_bufmgr per device.
So better to store intel_device_info into the shared iris_bufmgr and
save some memory.
Also in future patches iris_bufmgr will make more use of
intel_device_info.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19650>

anv: fixup another dirty issue with gpu_memcpy

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20335>

panfrost: fix memory leak related to disk cache

Direct leak of 3912 byte(s) in 2 object(s) allocated from:
    #0 0x7fbd4641b0 in __interceptor_malloc (/usr/lib64/libasan.so.6+0xa41b0)
    #1 0x7f74413518 in parse_and_validate_cache_item ../src/util/disk_cache_os.c:549
    #2 0x7f74414b84 in disk_cache_load_item ../src/util/disk_cache_os.c:599
    #3 0x7f74410364 in disk_cache_get ../src/util/disk_cache.c:551
    #4 0x7f775695ac in panfrost_disk_cache_retrieve ../src/gallium/drivers/panfrost/pan_disk_cache.c:125

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20336>

anv: Refactor anv_pipeline to use the anv_pipeline_type

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20316>

radv/rra: Fix leaf node id order

Leaf nodes aren't stored in build order so we have to account for that
when dumping leaf node ids.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20184>

radv/rra: Validate geometry_id

The following patch will use geometry_id so make sure that it's in
bounds.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20184>

radv/rra: Refactor resource management during dumping

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20184>

radv/rra: Emit leaf node ids for leaf nodes instead of internal nodes

Fixes: e4283d8 ("radv/rra: Handle box16 nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20184>

ac/sqtt: bump the maximum number of traces to 6 for GFX11

GFX11 can have more than 4 SEs. I think it would be better to allocate
an array but that's for later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20337>

ac/rgp: add missing GFX11 bits for RGP

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20337>

ac/nir: remove num_es_threads_var

A bit count of es_accepted works for both when ngg is and isn't
dynamically enabled. Unlike the other sequence, this should only be a
single SALU instruction.

fossil-db (gfx1100, nggc):
Totals from 41388 (30.75% of 134574) affected shaders:
Instrs: 25783544 -> 25432959 (-1.36%); split: -1.36%, +0.00%
CodeSize: 127281160 -> 125878820 (-1.10%); split: -1.10%, +0.00%
Latency: 92849566 -> 92723047 (-0.14%); split: -0.14%, +0.00%
InvThroughput: 9542194 -> 9485012 (-0.60%); split: -0.60%, +0.00%
Copies: 2031074 -> 1928796 (-5.04%); split: -5.04%, +0.00%
Branches: 642407 -> 642409 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20321>

ac/nir: fix ngg culling on gfx11

This subtraction can underflow.

If subgroup_id*wave_size is larger than num_live_vertices_in_workgroup,
num_es_threads_var should be zero.

fossil-db (gfx1100, nggc):
Totals from 41388 (30.75% of 134574) affected shaders:
Instrs: 25700772 -> 25783544 (+0.32%)
CodeSize: 126950072 -> 127281160 (+0.26%)
Latency: 92809233 -> 92849566 (+0.04%); split: -0.00%, +0.04%
InvThroughput: 9526675 -> 9542194 (+0.16%)
Copies: 2031078 -> 2031074 (-0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20321>

vc4: replace open-coded F_DUPFD_CLOEXEC with os_dupfd_cloexec()

Just like 12 lines above.

Split out of !20180

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20313>

intel/common/intel_genX_state.h: Add intel_set_ps_dispatch_state()

This replaces brw_fs_get_dispatch_enables(), which was added in
b9403b1c477 ("intel: factor out dispatch PS enabling logic"), but this
function will not work well for future changes to 3DSTATE_PS.

So, instead, this moves the related code into a "genX" file which can
directly update 3DSTATE_PS for the given platform.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20329>

intel/common: Add intel_genX_state.h

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20329>

radv/ci: add lists for GFX1100

0 failures, call it a win (the RT ones are CTS bugs).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20315>

st/mesa: Enable Alpha writes when writing RGB faked as RGBA

Some GPUs are able to render more efficiently when all channels of a
color attachment are written, since whole pixels are being overwritten,
rather than hitting a read-modify-write cycle where newly written data
has to be combined with existing unmodified image data.

When faking GL_RGB as RGBA (in case RGB/RGBX isn't color renderable),
we introduce an extra channel that doesn't exist from the application
point of view.  With such a format, a color mask of 0x7 (RGB) would mean
to write all channels.  But because we've added an alpha channel behind
their back, this becomes a partial write.  We are free to write whatever
garbage we want to the alpha channel, however.  So we can enable alpha
writes, making this a more efficient full pixel write again.

This is done unconditionally as it's expected to address a problem
common to many drivers and isn't expected to be harmful, even on GPUs
where it may not help much.

Improves WebGL Aquarium performance on Alderlake GT1 by around 2.4x, in
the Chromium, using Wayland (the --enable-features=UseOzonePlatform and
--ozone-platform=wayland flags).

v2: Don't require PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND (Marek)
v3: Fix independent blending enables (Emma) - now set when needed,
    skipped when not needed, and PIPE_CAP_INDEP_BLEND_ENABLE is no
    longer a requirement.  We just optimize where we can.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7864
Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Marek Olšák <marek.olsak@amd.com> [v2]
Reviewed-by: Emma Anholt <emma@anholt.net> [v3]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20290>

docs: update calendar and link releases notes for 22.3.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20328>

docs: add release notes for 22.3.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20328>

panfrost: Add tool to print supported texture formats

While all Panfrost-supported Mali GPUs support all the compressed texture
formats architecturally, the system integrator decides which formats will
actually be wired up in the production system-on-chip. In the past there may
have been legal considerations, I'm neither a lawyer nor a system integrator so
couldn't say.

It's useful for users to know which compressed texture formats are supported by
their hardware, to understand its performance characteristics (and perhaps to
buy systems that support their needs, especially if they need BCn formats which
are omitted in many Mali implementations).

To help with that, this commit adds a small standalone tool that prints which
formats are supported. It is tested so far on Mali-T860 and Mali-G57.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Chris Healy <healych@amazon.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20086>

ci/nouveau: Add a bunch of the top hits of gk20a flakes.

A bit of categorization in the process.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20326>

ci/nouveau: Sort some uncategorized gk20a flakes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20326>

nir: Allow more than just ALU instructions in 'weak' GVN

This removes the ALU-only restriction on the "weak" GVN introduced by
the previous commit.  This makes it slightly more aggressive, allowing
it to coalesce things like UBO loads (still within sister then/else
blocks).  This also can have surprisingly large cascading effects.

I was concerned that this might increase register pressure, but
shader-db and fossil-db show effectively no change in spills/fills,
so it seems to be fine.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19823>

nir: Perform 'weak' global value numbering in all GCM passes

Full global value numbering (GVN) can be pretty aggressive, moving
values far away from their original locations, even out of loops,
and can extend their live ranges a lot.  So we've left it disabled.

This patch introduces a weaker form of GVN: we only allow coalescing
identical values when they appear on either side of the same if/else
construct.  For now, we also only allow ALU instructions.

This allows nir_opt_gcm to clean up identical instructions appearing
on both sides of if/then/else control flow.  But it avoids aggressively
combining every other occurrence of a value in the program.

This can still have surprisingly large cascading effects, as simple
constructs are cleaned up, leading to more opportunities to do the
same clean up, up a chain of nested ifs.  It also enables greater use
of the select peephole as ifs are cleaned up.

shader-db and fossil-db results show a reduction in spills/fills on
Icelake, so it doesn't seem to be hurting register pressure.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19823>

anv: remove anv_reloc_list->array_length

This is another field that, after the recent commits, became unused.
It's either zero-initialized (by the memset) or copy-initialized
(which means it's also zero). And it never even gets used anywhere
anyway, so even if the value was non-zero it wouldn't matter.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20309>

anv: remove anv_reloc_list->reloc_bos

As a consequence of the last two commits, reloc_bos is always NULL and
never used anywhere, so remove it.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20309>

anv: remove anv_reloc_list_grow()

The last commit made it clear that anv_reloc_list_grow() only ever
gets called with zero as num_additional_relocs, which means it will
always immediately return VK_SUCCESS without doing anything. That
means we can remove it.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20309>

anv: remove anv_reloc_list->num_relocs

There are only a few places in the code where num_relocs gets set:

  - During anv_reloc_list_init() where it gets memset() to 0.
  - At anv_reloc_list_init_clone() where it gets set with the value of
    another anv_reloc_list->num_relocs.
  - During anv_reloc_list_clear(), where it gets set to 0.
  - During anv_reloc_list_append(), where it gets added with the value
    of another anv_reloc_list->num_relocs.

As you can see, either we explicitly set the value to 0 or we copy the
value that's present in another anv_reloc_list, which should be 0. The
one place where we used to increment num_relocs was in
anv_reloc_list_add(), but that was deleted by:

  7b7381e8d7a5 ("anv: Delete anv_reloc_list_add()")

So in this commit we delete the num_relocs field from struct
anv_reloc_list and we also delete some lines where, if the value is 0,
nothing will happen.

There's more we could be deleting here, but I wanted this commit to be
minimal so it's very clear that num_relocs can't be non-zero. We were
having some speculation that anv_reloc_list may still be important for
actually adding BOs to the batch and building the validation list, so
let's go slowly with the removal to make everything more easily
reviewable.

The one possibility I could be missing here is another situation like
the memset() we have at anv_reloc_list_init() or some other crazy
indirect overwrite, but as far as I have checked, that is not the
case.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20309>

anv: remove anv_execbuf->surface_states_relocs

Now that we removed relocations, this is not being used anywhere.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20309>

intel/common: clean up AUX macros

The hardcoded is either replaced with new interfaces or relocated
to C file if it is private.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20259>

intel/vulkan: replace AUX macros with interfaces

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20259>

intel/isl: Support 1MB alignment for AUX mapping

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20259>

intel/common: Support 1MB granularity AUX mapping format (Bspec 44930)

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20259>