review.tizen.org Git - platform/upstream/mesa.git/log

ci/vs2019: Clear CI_COMMIT_MESSAGE and CI_COMMIT_DESCRIPTION for please meson

Fixes https://gitlab.freedesktop.org/lygstate/mesa/-/jobs/23444155/raw
https://gist.github.com/lygstate/201dd9d2db3d411668f7bbdc17daf74a

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16825>

venus: Add driconf option to enable implicit fencing

Signed-off-by: Renato Pereyra <renatopereyra@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16735>

mesa: throw a log warning any time a fallback texture is used

this generally means an app is broken in some way, so throw a log
message to be helpful

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16821>

pan/bi: Rework Valhall register alignment

Because we lower SPLIT and COLLECT before RA, we need to consider offsets when
determining the dimensions of vectors, in order to align properly. Lowering
COLLECT post-RA would avoid this special case.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>

pan/bi: Align 64-bit register sources

Similar idea to aligning staging register sources.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>

pan/bi: Allow vec6 for collects

Hit for some Valhall texturing instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>

pan/bi: Use nodearrays for linear constraints

Speeds up compiling shaders/skia/781.shader_test in shader-db by 8x
(Icecream95).

...At least it did before I extended to support register allocation of vec8. On
Valhall, texture instructions require up to 8 consecutive registers. To handle
this, provide for vec8 register allocation. Liveness was already (accidentally?)
vec8. The increased memory requirement is acceptable given that the interference
matrix is now stored sparsely (Alyssa).

Icecream95 reports the vec8 changes hurt RA performance by about 1% on average.
I consider this acceptable for now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>

pan/bi: Add nodearray datastructure

This is an array which can either be sparse or dense, and was designed
to be used to track liveness and interference information.

Either a sparse array with sorted indices or dense array is used.
Other data structures were tried, such as red-black trees or hash
tables, but they were slower. When used for storing constraints, the
indices do not have to be sorted as duplicating elements is okay, but
the speedup from that was not enough to justify the extra complexity.

v2: Add a comment about how to potentially speed it up. But it seems
  fast enough even without this change.
v3: Use a custom struct rather than relying on util_dynarray.
v4: Split out functions only used for liveness analysis, rather than the simpler
  data structure needed for the register interference matrix. If we need to
  optimize liveness, that can follow on after. Also make it for vec8 (Alyssa).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>

pan/bi: Reverse linear constraint bits

This will make it simpler to implement parallel RA where multiple
possible registers for a node are tested at once.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16780>

d3d12: Align output buffer offset access to D3D12_FEATURE_DATA_VIDEO_ENCODER_RESOURCE_REQUIREMENTS.CompressedBitstreamBufferAccessAlignment

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16644>

tu: Enable shaderTessellationAndGeometryPointSize

This already works and AFAICT there was no reason to disable it other
than that the blob does.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16830>

tu: Fix D32S8 resolves into D32 or S8 in sysmem mode

Fixes CTS tests in sysmem mode:
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_depth
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16834>

radv/ci: update list of failures for Pitcairn

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16836>

radv,aco: disable shader cache when ACO debug options are used

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14594>

nir: xfb_buffer_info::stride is in bytes

For the NIR XFB gathering as well as all the Vulkan drivers, buffer
strides in nir_xfb_info are in bytes.  When Marek started using
nir_xfb_info for GLSL on radeonsi, he copied directly from the GLSL
struct which has strides in dwords.  This inconsistency didn't show up
until I went through and started us using the NIR passes for GL drivers
directly without going through the GLSL structs.  We could change the
nir_xfb_buffer_info field to be in dwords to be consistent with
shader_info but that would mean changing all the Vulkan drivers but, for
now, it's easier to always use bytes in nir_xfb_info.

Fixes: 2a22885a457e ("st,nir: Use nir_shader::xfb_info in nir_lower_io_passes")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16819>

nir/glsl: Use rzalloc for nir_xfb_info

A lot of the fields get fully overwritten but outputs/buffers_written
are both bitfields that we set one bit at a time.

Fixes: 7c5dc0b11a11 ("glsl/nir: Populate nir_shader::xfb_info after linking varyings")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16819>

lavapipe: fix dynamic patchControlPoints

the dynamic state value is independent of whether tesselation is used

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16824>

include: drop c11_compat.h

We now require C11, and C++ supports static_assert just fine, which is
the only thing this header ever added support for. So let's get rid of
this needless header.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

include: drop c99_math.h

Since we now depend on C11, we know that we have support for the C99
math functionality. So let's drop the c99_math.h compatibility wrapper,
and just include <math.h> directly.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

vulkan/device_select: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

intel/isl: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

include: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

gallium: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

mapi: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

gallium/util: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

egl: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

util: remove needless c99_compat.h includes

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

util: add missing c99_compat.h includes

These headers use the "restrict" keyword, so they need to include
c99_compat.h in case they get included from C++.

Right now, we include c99_compat.h in many needless places, which saves
us. But we're about to stop doing that.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

c99_compat.h: remove inline and __func__ shims

We're requiring C11 now, and both "inline" and __func__ is supported
in C++ code as well. So no need for these compatibility-shims anymore.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

meson: modernize win_flex stdint.h logic

Since this logic was written, we've moved to require C11, so this can
now be simplified. First of all, we no longer need to set
__STDC_VERSION__ for C code at all, because the issue that MSVC doesn't
set __STDC_VERSION__ for C99 is longer a concern. Second, we can make
the C++ check unconditional.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>

intel: remove stale makefile

When this landed, the Autotools build system was already removed. Why
was this file added in the first place? Probably a rebase-mistake...

Fixes: 134e750e16b ("i965: extract performance query metrics")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16790>

freedreno: remove stale makefile

We don't use this makefile, so there's no point in keeping it in the
repo. It's also a generated one, so it contains a lot of... mess.

Fixes: 536f43cb96b ("freedreno: slurp in afuc")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16790>

radeonsi: port amdgcn_glslc build to meson

Seems nice to reduce the number of old-fashioned build systems we have
in-tree.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16789>

radv/ci: try to guess failure expectations for Fiji/Raven/Navi14/Navi22

The guesses are based on other gpus from the same gfx version. We will
need actual runs on the GPUs to confirm this.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>

radv/ci: remove an expected fail from all families

dEQP-VK.glsl.builtin.precision_double.determinant.compute.mat3 was
failing because of a CTS bug, which got fixed in the latest update for
all our CI machines.

This commit assumes this got fixed for all families, even the ones we
did not try to run on.

Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>

radv/ci: update the vkcts expectations for the CI machines

Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>

radv/ci: bump the timeout of vangogh/renoir

The execution time of vkcts has drastically changed with the latest
update, especially for APUs. This commit bumps the timeout to give
them a chance to finish.

Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>

radv: fix lowering GS intrinsics if NGG is disabled per pipeline

If NGG is disabled per pipeline for extreme (or suboptimal) geometry
or with transform feedback, make sure to not lower GS intrinsics that
are only needed for NGG GS. This means we have to lower GS intrinsics
later in the compilation process to effectively know if the pipeline
uses NGG.

fossils-db (Navi21):
Totals from 8 (0.01% of 134913) affected shaders:
VGPRs: 512 -> 520 (+1.56%)
CodeSize: 58180 -> 65080 (+11.86%); split: -0.04%, +11.90%
MaxWaves: 128 -> 126 (-1.56%)
Instrs: 10525 -> 11779 (+11.91%); split: -0.05%, +11.96%
Latency: 62941 -> 49428 (-21.47%); split: -21.59%, +0.12%
InvThroughput: 16121 -> 12950 (-19.67%); split: -19.96%, +0.29%
VClause: 122 -> 123 (+0.82%); split: -0.82%, +1.64%
SClause: 130 -> 143 (+10.00%)
Copies: 566 -> 596 (+5.30%); split: -0.35%, +5.65%
Branches: 200 -> 208 (+4.00%)
PreSGPRs: 424 -> 422 (-0.47%)
PreVGPRs: 430 -> 424 (-1.40%); split: -1.63%, +0.23%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15885>

docs: update calendar and link releases notes for 22.0.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>

docs: update sha256 for 22.0.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>

docs: add release notes for 22.0.5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>

docs: update calendar and link releases notes for 22.1.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>

docs: Add sh256sums for 22.1.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>

docs: add release notes for 22.1.1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16828>

wgl, d3d12: Handle front buffer writes for double-buffered MSAA surfaces backed by swapchains

We don't need to go as far as the fake front thing when MSAA is being used, because the
swapchain (single-sampled) is already decoupled from the app render buffers. But we do
need to direct the frontbuffer flush to the single-sampled back buffer, and then present
the back buffer. We also need to swap the buffers when we do this, so the next blit
targets the former front buffer.

Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16227>

freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts.

Shaves 5 instructions off of one manhattan31 shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

freedreno/ir3: Fix validation of half-precision image store values.

ce1a381e57d2 ("turnip: enable VK_KHR_16bit_storage on A650") determined
that the type of the instr decided the type of the value being stored in
the ".b" case. But it would be surprising if image stores had the type
determine the coordinates' precision instead of the value's, and once we
turned on image instruction precision lowering we ran into asserts.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

freedreno/ir3: Pass 16-bit sampler coordinates when possible.

shader-db highlights from Rob's android shaders:

total instructions in shared programs: 769641 -> 767536 (-0.27%)
instructions in affected programs: 151139 -> 149034 (-1.39%)
total last-baryf in shared programs: 55908 -> 55607 (-0.54%)
last-baryf in affected programs: 35219 -> 34918 (-0.85%)
total sstall in shared programs: 67074 -> 65767 (-1.95%)
total full in shared programs: 36115 -> 36080 (-0.10%)
full in affected programs: 203 -> 168 (-17.24%)
sstall in affected programs: 9510 -> 8203 (-13.74%)
total (ss) in shared programs: 14380 -> 14239 (-0.98%)
(ss) in affected programs: 2965 -> 2824 (-4.76%)
total systall in shared programs: 92425 -> 91522 (-0.98%)
systall in affected programs: 13146 -> 12243 (-6.87%)
total (sy) in shared programs: 4330 -> 4314 (-0.37%)
(sy) in affected programs: 167 -> 151 (-9.58%)
total waves in shared programs: 71580 -> 71584 (<.01%)
waves in affected programs: 12 -> 16 (33.33%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

freedreno/ir3: Make the types of tex coord padding match.

Required for lowering of coords to be 16-bit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

freedreno/ir3: Move the texture array coord fixup to nir

We're going to optimize sampler coordinates to FP16, so we'll need to
add the appropriately typed 0.5. Move this to NIR where that information
is readily available.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

freedreno/ir3: Enable load/store vectorization for SSBO access, too.

Saves a few ldib/stib instructions in gfxbench vk-5-normal compute shaders
by grouping vec4 accesses together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

nir_lower_mediump: Drop assertion about not containing movs.

A 1D texture operation may need to do a mov to turn a reference to a
channel of an SSA value into a scalar value to be passed as the texture
coordinate (since texture srcs can't do swizzles). Seen in
amnesia-the-dark-descent/low/46.shader_test() for example, where a 1D
texture is used to remap each of r,g,b from a previous texture result.

Besides, the nir_op_is_vec() case will (perhaps surprisingly) look through
a mov, anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

ci/turnip: Add missing xfails for a618 full VK run

Fixes: 836ce97f5ea8 ("ci: bump VK-GL-CTS to 1.3.2.0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>

venus: resolve AHARDWAREBUFFER_FORMAT_Y8Cb8Cr8_420 to external format

This is to work around ANGLE yuv support.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16759>

pan/bi: Respect swizzles in nir_op_pack_64_2x32_split

Triggered a BIR validation error, which made debugging a breeze. That validation
pass (dimensionality checks) gets a lot of use, it seems :-)

Fixes:

dEQP-VK.ssbo.layout.2_level_array.std430.row_major_mat4x2_comp_access_store_cols

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>

panvk: Use vk_image_subresource_*_count for clears

This handles VK_REMAINING_* for us, instead of underflowing and clearing no
levels/layers.

Fixes dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.*

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>

panfrost: Allow 2D AFBC on Valhall

2D AFBC should be working now, flip the switch. 3D AFBC needs more research to
get right, honestly it's not clear how 3D AFBC on Bifrost is working...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>

panfrost: Handle texturing from AFBC on Valhall

We need to pack special AFBC-specific plane descriptors instead of the generic
plane descriptor. Nothing too fancy here, though.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>

panfrost: Support rendering to AFBC on Valhall

Add the required handling when packing render target and depth buffer
descriptors on Valhall. This is mostly equivalent to Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>

panfrost: Add pan_afbc_compression_mode on Valhall

Map a canonical format (a hardware-independent pipe_format) to a compression
mode (Valhall-specific hardware enum defined in GenXML). To be used for packing
plane descriptors and render target descriptors when AFBC is in use on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>

panfrost: Pass arch instead of dev into afbc_format

For callers that have a device object, it's easy to pass dev->arch instead of
dev. But this requires callers to have a reference to the device, which is
tricky for callers that only have the arch via PAN_ARCH. Pass dev->arch instead
of dev to accommodate them.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>

panfrost: Fix XML for AFBC header on v9

Misnamed field due to copy/paste fail from Bifrost.

Fixes: c011ea6c265 ("panfrost: Shuffle render target AFBC for Valhall")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>

pan/mdg: Print outmods when printing IR

In particular, this lets us distinguish mul_high from regular mul.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Distinguish SSA vs reg when printing IR

This makes it easy to match the printed IR with the indices in the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Only print 1 source for moves

This makes the printed IR easier to read at a glance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Only print 2 sources for ALU

..and assert the other sources are null. The one place this might fail in the
future is for real FMA, but we don't support that for GL.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Only print masked components of swizzle

This matches the IR printer with the disassembler, making the output of the IR
printer much easier to parse at a glance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Use "<<" instead of "lsl"

Easier to read and consistent with C code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Remove uppercase write masks

These do not convey any additional information, and fail to account for
shrinking. In particular, a 64-bit writemask with .keephi would fail to
disassemble and instead trip the assertion, since that would be the ZW
components. Just delete the broken code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

pan/mdg: Scalarize with 64-bit sources

Otherwise, we can get vec3 with u2u32 with 64-bit sources which we need lowered.
Since our current approach is "scalarize all 64-bit ops", we need to check for
conversions too.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>

radv, aco: Packed usub_sat/isub_sat.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

radv: Enable VK_INTEL_shader_integer_functions2.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

radv: Lower 8bit isub_sat/usub_sat.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

radv: Lower hadd/hradd.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

radv: Lower mul_32x16.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

nir: Add optional lowering for mul_32x16.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

ac/llvm: Implement uclz.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

ac/llvm: Implement usub_sat and isub_sat.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

aco: Implement isub_sat.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

aco: Implement usub_sat.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

aco: Implement uclz.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

ir3: Force late-z if FS has global store/atomic

No known tests are fixed.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16816>

pan/bi: Use flow control lowering on Valhall

Logically at the same part of the compile pipeline as clause scheduling on
Bifrost. Lots of similarities, too. Now that we generate flow control only as a
late pass, various hacks in the compiler are no longer necessary and are
dropped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Unit test flow control merging

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Unit test flow control insertion

Test that we correctly track the scoreboard, helper invocations, reconvergence,
and ends and insert NOPs to effect this expected flow control.

As the pass inserts NOPs but does not otherwise modify the shader, this is easy
to test with well-defined behaviour of the pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Respect assigned slots

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Assign slots roundrobin

This should reduce false dependencies with asynchronous instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Add flow control merging pass

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Terminate helper threads

On Bifrost, to terminate helper threads we set the td bit on the clause. On
Valhall, we need to use the .discard flow control. Extend the flow control NOP
insertion to insert NOP.discard where necessary to terminate helper threads.
This should reduce wasted work in fragment shaders.

This requires fairly involved data flow analysis, but the handling here should
be optimal.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Do scoreboard analysis

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/va: Add pass to insert flow control

To set flow control modifiers correctly and efficiently, we need a pass that
runs after register allocation and scheduling, but before packing. Add such a
pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Print flow control on instructions

This helps debug the flow control lowering passes on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Export helper termination analysis

The current helper termination analysis code is hardwired for clauses, so it
won't work for Valhall. However, the bulk of it is dataflow analysis which is
portable between Bifrost and Valhall. Export the interesting bits so we can
reuse them on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Export bi_block_add_successor

For use in unit tests that need to create blocks.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Extract bit_block helper

Convenience for unit tests which need to create multiple blocks, to test global
passes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Add a trivial ctx->inputs for unit tests

So we can unit test the flow control insertion which needs to gate some
behaviour on not being in a blend shader.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Add ASSERT_SHADER_EQUAL macro

Useful for whole-program unit tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>

pan/bi: Preserve flow control for non-psiz variant

Otherwise we will get INSTR_INVALID_ENC faults when deleting the final STORE.end
instruction, after we rework our flow control code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>