Kumar Gala [Fri, 4 Feb 2011 06:43:34 +0000 (00:43 -0600)]
powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in
config_mpc85xx.h for those parts with a Frame Manager.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Priyanka Jain [Tue, 8 Feb 2011 10:15:25 +0000 (15:45 +0530)]
powerpc/85xx: Corrected sdhc clock value for P1010
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Sun, 6 Feb 2011 06:01:44 +0000 (11:31 +0530)]
powerpc/85xx: Adds some P1010/P1014 SoC configuration defines
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR
and SDHC erratum.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 5 Feb 2011 19:45:07 +0000 (13:45 -0600)]
powerpc/85xx: Support for Freescale P1024/P1025 processor
Add Support for Freescale P1024/P1025 (dual core) and
P1015/P1016 (single core) processors.
P1024 is a variant of P1020 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1025 is a variant of P1021 processor with a core frequency from
400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA
P1015 is a variant of P1024 processor with single core and P1016 is a
variant of P1025 processor with single core.
Added comments in config_mpc85xx.h to denote single core versions of
processors.
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Zhao Chenhui [Sun, 13 Mar 2011 15:00:40 +0000 (10:00 -0500)]
echi: add ULI1575 PCI ID
Add ULI1575 EHCI controller to the list of the supported devices.
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Acked-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Haiying Wang [Mon, 7 Feb 2011 21:14:15 +0000 (16:14 -0500)]
powerpc/85xx: load ucode from nand flash before qe_init
In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Mon, 7 Feb 2011 09:39:51 +0000 (15:09 +0530)]
fsl_ddr: Adds 16 bit DDR Data width option
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal [Mon, 7 Feb 2011 09:38:29 +0000 (15:08 +0530)]
powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Fri, 4 Feb 2011 21:58:00 +0000 (13:58 -0800)]
powerpc/8xxx: Display DIMM model
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Fri, 4 Feb 2011 21:57:59 +0000 (13:57 -0800)]
powerpc/85xx: Update fixed DDR3 timing table for P4080DS
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 3 Feb 2011 15:02:13 +0000 (09:02 -0600)]
powerpc/8xxx: Fix LAW init to respect pre-initialized entries
If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW
entries consider them good and mark them used.
In the NAND SPL case we skip re-initializing based on the law_table
since the SPL phase already did that.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Prabhakar Kushwaha [Fri, 4 Feb 2011 03:30:43 +0000 (09:00 +0530)]
fsl_pci: Add support for FSL PCIe controllers v2.x
FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.x
Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status register
Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.
To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Haiying Wang [Thu, 20 Jan 2011 22:26:31 +0000 (22:26 +0000)]
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs
There are some differences between CoreNet (P2040, P3041, P5020, P4080)
and and non-CoreNet (P1017, P1023) based SoCs in what features exist and
the memory maps.
* Rename various immap defines to remove _CORENET_ if they are shared
* Added P1023/P1017 specific memory offsets
* Only setup LIODNs or LIODN related code on CORENET based SoCs
(features doesn't exist on P1023/P1017)
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Roy Zang [Fri, 4 Feb 2011 04:14:19 +0000 (22:14 -0600)]
powerpc/85xx: Add support for Freescale P1023/P1017 Processors
Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 4 Feb 2011 02:21:42 +0000 (20:21 -0600)]
powerpc/85xx: Don't build read_tlbcam_entry for CONFIG_NAND_SPL
Slim down NAND SPL build a bit as we don't need read_tlbcam_entry.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 2 Feb 2011 17:23:50 +0000 (11:23 -0600)]
powerpc: Add cpu_secondary_init_r to allow for initialization post env setup
We can simplify some cpu/SoC level initialization by moving it to be
after the environment and non-volatile storage is setup as there might
be dependancies on such things in various boot configurations.
For example for FSL SoC's with QE if we boot from NAND we need it setup
to extra the ucode image to initialize the QE. If we always do this
after environment & non-volatile storage is working we can have the code
be the same regardless of NOR, NAND, SPI, MMC boot.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 1 Feb 2011 05:09:25 +0000 (23:09 -0600)]
powerpc/85xx: Cleanup some QE related defines
Move some processor specific QE defines into config_mpc85xx.h and use
QE_MURAM_SIZE to cleanup some ifdef mess in the QE immap struct.
Also fixed up some comment style issues in immap_qe.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 1 Feb 2011 04:18:47 +0000 (22:18 -0600)]
powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 1 Feb 2011 02:36:02 +0000 (20:36 -0600)]
powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Mon, 31 Jan 2011 21:57:01 +0000 (15:57 -0600)]
powerpc/85xx: Remove config.mk for nand linker script
Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Mon, 31 Jan 2011 21:51:20 +0000 (15:51 -0600)]
powerpc: Move cpu specific lmb reserve to arch_lmb_reserve
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Li Yang [Mon, 24 Jan 2011 17:09:52 +0000 (17:09 +0000)]
powerpc/85xx: Update P2020DS default env settings
Read MAC address from EEPROM. Add hwconfig settings.
Modified the default othbootargs to include the cache-sram-size
parameter. This parameter is needed as the L2 as SRAM is ON by
default in the P2020RDB kernel and used by the Gianfar driver.
Also cleanup some of the boot commands.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang [Mon, 24 Jan 2011 17:09:53 +0000 (17:09 +0000)]
powerpc/85xx: Add eSDHC support on P2020DS
We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9
respectively).
We enable EXT2, FAT, and parition support for both MMC & USB configs.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 25 Jan 2011 18:42:32 +0000 (12:42 -0600)]
powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020
Specify the number of DDR controllers, number of frame managers, number
of 1g and 10g ports.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Pankaj Chauhan [Tue, 25 Jan 2011 09:14:57 +0000 (14:44 +0530)]
powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl,etsec2"
In a manner similar to passing ethernet stashing parameters into device
tree for "gianfar", extend the support to the "fsl,etsec2" as well.
Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com>
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 25 Jan 2011 07:48:03 +0000 (01:48 -0600)]
powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>
Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 25 Jan 2011 05:36:17 +0000 (23:36 -0600)]
powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init
Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.
Based on patch from Poonam Aggrwal.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Fri, 21 Jan 2011 22:03:57 +0000 (16:03 -0600)]
p1022ds: allow for board-specific ngPIXIS functions
The ngPIXIS is an FPGA used on the reference boards of most Freescale PowerPC
SOCs. Although programming the ngPIXIS is mostly standard on all boards that
have it, the P1022DS is unique in that the ngPIXIS needs to be programmed in
"indirect" mode whenever the video display (DIU) is active.
To support indirect mode, and to make it easier to support other quirks on
future reference boards, the low-level ngPIXIS functions are all marked as
weak, so that board-specific code can override any of them. We take advantage
of this feature on the P1022DS, so that we can properly reset the board when
the DIU is active.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Dipen Dudhat [Thu, 20 Jan 2011 10:59:35 +0000 (16:29 +0530)]
powerpc/85xx: Add support for Integrated Flash Controller (IFC)
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.
Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
configurable
page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
availble at
boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
e.g. SRAM, ROM
- External clock is supported with programmable division
ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
on I/O bus
- 32 bit I/O: AD
- 16 bit I/O: AADD
- 8 bit I/O :
AAAADDDD
- Configurable Even/Odd Parity on Address/Data bus
supported
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Prabhakar Kushwaha [Thu, 20 Jan 2011 11:04:41 +0000 (16:34 +0530)]
powerpc/85xx: Add SERDES support for P1010/P1014
Add the ability to determine if a given IP block connected on SERDES is
configured. This is useful for things like PCIe and SRIO since they are only
ever connected on SERDES.
Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:58 +0000 (18:33 +0200)]
MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectory
Au1x00 is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Thomas Lange <thomas@corelatus.se>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:57 +0000 (18:33 +0200)]
MIPS: IncaIP: Move all IncaIP specific code to separate subdirectory
IncaIP is a SoC and its specific code should reside in an own
SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:56 +0000 (18:33 +0200)]
MIPS: Optimize the setup of CPU optimization flags
The current MIPS CPU config.mk code always expects a MIPS 4kc
core. This is not appropiate for other CPUs and SoCs.
Replace the current MIPSFLAGS code by cc-option macro and use
-march=mips32r2 as default optimization level for all MIPS32 CPUs.
Note: Since commit
f62fb99941c625605aa16a0097b396a5c16d2c88 all
toolchains with binutils prior to v2.16 are not working anymore.
As agreed with Shinya Kuribayashi the support for those toolchains
will be dropped officially with this patch.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:55 +0000 (18:33 +0200)]
MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32
All current CPUs and SoCs are based on MIPS32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other MIPS architectures like MIPS64 or Octeon should
be supported in the future.
To achieve this the current CPU code is moved to its own mips32
subdirectory. All MIPS32 boards have to use mips32 as config switch
in board.cfg.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Cc: Vlad Lungu <vlad.lungu@windriver.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Daniel Schwierzeck [Mon, 28 Mar 2011 16:33:54 +0000 (18:33 +0200)]
MIPS: Purple: Remove Purple support
The Purple SoC and eval board are not actively maintained since years.
This patch removes the support completely as aggreed with Wolfgang Denk.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Trübenbach, Ralf [Thu, 31 Mar 2011 16:46:47 +0000 (16:46 +0000)]
ehci-pci: Add PCI EHCI controller
This patch adds support for the PI7C9X442SL PCIe EHCI host controller
from Pericom.
Tested at P4080DS eval board from Freescale.
Signed-off-by: Ralf Trübenbach <ralf.truebenbach@men.de>
Cc: Remy Bohmer <linux@bohmer.net>
Erik Hansen [Thu, 24 Mar 2011 09:15:37 +0000 (10:15 +0100)]
fat32 root directory handling
Fat directory handling didn't check reaching the end of the root directory. It
relied on a stop condition based on a directory entry with a name starting with
a '\0' character. This check in itself is wrong ('\0' indicates free entry, not
end_of_directory) but outside the scope of this fix. For FAT32, the end of the
rootdir is reached when the end of the cluster chain is reached. The code didn't
check this condition and started to read an incorrect cluster. This caused a
subsequent read request of a sector outside the range of the usb stick in
use. On its turn, the usb stick protested with a stall handshake.
Both FAT32 and non-FAT32 (FAT16/FAT12) end or rootdir checks have been put in.
Signed-off-by: Erik Hansen <erik@makarta.com>
Erik Hansen [Thu, 24 Mar 2011 14:06:24 +0000 (15:06 +0100)]
Remove unnecessary reset in usb_stor_get_info
The reset request in usb_stor_get_info is causing issues with some usb
sticks. Some of these sticks vendor_id/product_id have been hardcoded to
not reset but better is to remove the reset altogether. It is not needed.
Signed-off-by: Erik Hansen <erik@makarta.com>
Mike Frysinger [Thu, 17 Mar 2011 21:35:01 +0000 (17:35 -0400)]
usb: musb: blackfin: check anomaly workarounds at runtime too
The anomaly workarounds we need for older silicon might break things
if used on newer versions where the anomalies don't exist. So check
the silicon rev at runtime too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger [Thu, 17 Mar 2011 21:35:00 +0000 (17:35 -0400)]
usb: musb: blackfin: make clkin configurable
Not everyone has a 24MHz clkin to the USB, so let board porters override.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
michael [Mon, 14 Mar 2011 21:16:38 +0000 (21:16 +0000)]
atmel_nand: don't require CONFIG_SYS_NAND_ENABLE_PIN
If NCE is hooked up to NCS3, we don't need to (and can't)
explicitly set the state of the NCE pin. Instead, the
controller asserts it automatically as part of a
command/data access. Only "CE don't care"-type NAND chips
can be used in this manner.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Reinhard Meyer <u-boot@emk-elektronik.de>
Florian Fainelli [Fri, 25 Feb 2011 00:01:34 +0000 (00:01 +0000)]
NAND: add support for reading ONFI page table
This patch adds support for reading an ONFI page parameter from a NAND
device supporting it. If this is the case, struct nand_chip onfi_version
member contains the supported ONFI version, 0 otherwise.
This allows NAND drivers past nand_scan_ident to set the best timings for the
NAND chip.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Haiying Wang [Thu, 27 Jan 2011 14:44:59 +0000 (09:44 -0500)]
Fix NAND_SPL and ONENAND_IPL in Makefile
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Scott Wood [Thu, 3 Feb 2011 00:15:57 +0000 (18:15 -0600)]
NAND: add more watchdog resets
Poke the watchdog in a variety of looping constructs, which could take
a long time to complete.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Wolfgang Denk [Thu, 31 Mar 2011 21:45:36 +0000 (23:45 +0200)]
Prepare v2011.03
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Thu, 31 Mar 2011 21:26:29 +0000 (16:26 -0500)]
Fix build issues cause by LDFLAGS_FINAL changes
Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a
number of Makefiles in a way that broke out-of-tree builds. The
problem was that $(nandobj) was used before it got defined.
Fix this.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Wolfgang Denk [Thu, 31 Mar 2011 07:01:36 +0000 (09:01 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Wolfgang Denk [Thu, 31 Mar 2011 06:59:32 +0000 (08:59 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash
Wolfgang Denk [Tue, 29 Mar 2011 12:34:50 +0000 (14:34 +0200)]
Fix build problems caused by "_end" -> "__bss_end__" rename
Commit 44c6e65 "rename _end to __bss_end__ broke building of a large
number of systems (at least all PowerPC?):
libstubs.o: In function `app_startup':
examples/standalone/stubs.c:197: undefined reference to `__bss_end__'
The rename should not be done for the files in the
examples/standalone/ directory, as these are not using the code from
start.S, but do their own BSS clearing, and either use their own
linker scripts or the ones provided by the compilers.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Prabhakar Kushwaha [Tue, 1 Feb 2011 15:55:58 +0000 (15:55 +0000)]
powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Martin Krause [Mon, 21 Mar 2011 17:07:56 +0000 (18:07 +0100)]
cfi_flash: fix bug with flash banks with different sector numbers
The function find_sector() does not take into account if the flash bank
has changed since the last call. This could lead to illegal accesses inside
and beyond the flash_info_t info strcture. For example if the current
flash bank has less sectors than the last used flash bank.
This patch adds two cheks. One that insures, that the current sector does
not exceed the allowed maximum (which is always a good idea). And one that
checks if the current access is to the same flash bank as the last access.
If not, the search loop will start with sector 0.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Jiang Yutang [Sun, 30 Jan 2011 23:06:20 +0000 (17:06 -0600)]
powerpc/85xx: Enable various errata on P1022/P1013 SoCs
Enable workaround for errata ELBC A001, ESDHC 111 & SATA A001 on
P1022/P1013 SoCs.
Also updated P1022DS config to properly enable CONFIG_FSL_SATA_V2.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Wolfgang Denk [Sun, 27 Mar 2011 19:50:07 +0000 (21:50 +0200)]
Prepare v
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Sun, 27 Mar 2011 19:48:08 +0000 (21:48 +0200)]
Coding Style cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk [Sun, 27 Mar 2011 19:20:29 +0000 (21:20 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-arm
Tom Warren [Wed, 23 Feb 2011 09:54:31 +0000 (09:54 +0000)]
arm: Tegra2: Change mach-type to MACH_TYPE_SEABOARD due to mach-types.h update
Signed-off-by: Tom Warren <twarren@nvidia.com>
Chander Kashyap [Tue, 22 Mar 2011 01:40:50 +0000 (01:40 +0000)]
S5P: mmc: Resolved interrupt error during mmc_init
Blocksize was hardcoded to 512 bytes. But the blocksize varies
depeding on various mmc subsystem commands (between 8 and 512).
This hardcoding was resulting in interrupt error during data
transfer.
It is now calculated based upon the request sent by mmc subsystem.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Chander Kashyap [Tue, 22 Mar 2011 01:29:38 +0000 (01:29 +0000)]
ARMV7: S5P: Fixed register offset in mmc.h
The MMC registers are accessed through struct s5p_mmc member
variables. MMC controller "control4" register offset is set
to 0x8C as per data sheet. The size of struct s5p_mmc is also
corrected.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Wed, 16 Mar 2011 11:09:20 +0000 (20:09 +0900)]
S5P: timer: replace bss variable by gd
Use the global data instead of bss variable, replace as follow.
count_value -> removed
timestamp -> tbl
lastdec -> lastinc
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Albert ARIBAUD <albert.aribaud@free.fr>
Minkyu Kang [Thu, 10 Mar 2011 11:10:38 +0000 (20:10 +0900)]
S5P: universal: Enable the pwm driver
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Thu, 10 Mar 2011 11:10:19 +0000 (20:10 +0900)]
S5P: goni: Enable the pwm driver
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Thu, 10 Mar 2011 11:09:43 +0000 (20:09 +0900)]
S5P: smdkc100: Enable the pwm driver
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Thu, 10 Mar 2011 11:05:58 +0000 (20:05 +0900)]
S5P: timer: Use pwm functions
Use pwm functions for timer that is PWM timer 4.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Donghwa Lee [Mon, 7 Mar 2011 21:11:42 +0000 (21:11 +0000)]
ARM: S5P: pwm driver support
This is common pwm driver of S5P.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:14 +0000 (10:06 +0000)]
SMDK6400: Fixup dram_init for relocation support
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:13 +0000 (10:06 +0000)]
SMDK6400: Disable LED function in start.s on the nand booting
Since nand boot have some limit for the first 4KB, We only
disable the LED function to reduce the code space. At the
same time, Fix the compile error for LED function undefined
in the compile time of nand_spl.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:12 +0000 (10:06 +0000)]
SMDK6400: Add some labels to u-boot.lds to support nand_spl
In the nand_spl feature of SMDK6400. Add some relocation symbols to
nand_spl/board/samsung/smdk6400/u-boot.lds to fix the compile error.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:11 +0000 (10:06 +0000)]
SMDK6400: Fix the mutiple link error
The first, the cpu_init.o have already been link for cmd_link_o_target
atfer compile, But, The link script re-link the point file. So the link
machine will generate multiple definition error information.
The second, Since the first 4kB of nand boot featue code move to nand_spl,
So It is not necessary to force the cpu_init.o in non-nand boot.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:10 +0000 (10:06 +0000)]
SMDK6400: Fix some label undefined in build error
Modify Makefile for cpu_init.c and Start.s use some label,this defined
u-boot.lds of arch/arm/cpu/arm1176. But SMDK6400 use the link script
board/samsung/smdk6400/u-boot-nand.lds. So add some label form u-boot.lds
to u-boot-nand.lds
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
seedshope [Sat, 22 Jan 2011 10:06:09 +0000 (10:06 +0000)]
SMDK6400: Fix CONFIG_SYS_INIT_SP_ADDR undefined
Fix CONFIG_SYS_INIT_SP_ADDR undefined issue.
Signed-off-by: Zhong Hongbo <bocui107@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Po-Yu Chuang [Tue, 1 Mar 2011 23:02:04 +0000 (23:02 +0000)]
arm: fix incorrect monitor protection region in FLASH
Monitor protection region in FLASH did not cover .rel.dyn
and .dynsym sections, because it uses __bss_start to compute
monitor_flash_len. Use _end instead.
Add _end to linker scripts for end of u-boot image
Add _end_ofs to all the start.S.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Po-Yu Chuang [Tue, 1 Mar 2011 22:59:59 +0000 (22:59 +0000)]
rename _end to __bss_end__
Currently, _end is used for end of BSS section. We want _end to mean
end of u-boot image, so we rename _end to __bss_end__ first.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Prabhakar Kushwaha [Wed, 23 Mar 2011 09:21:13 +0000 (04:21 -0500)]
powerpc/85xx: Fix PCI memory map setup on P1_P2_RDB
Update the PCIe address map to match standard FSL memory map.
Additionally, fix the TLBs so the cover the PCIe address space properly
so cards plugged in like an e1000 work correctly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 17 Mar 2011 18:18:13 +0000 (11:18 -0700)]
powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134
The fix for errata workaround is to avoid covering physical address
0xff000000 to 0xffffffff during the implementation.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 17 Mar 2011 18:18:12 +0000 (11:18 -0700)]
powerpc/mpc8xxx: disable rcw_en bit for non-DDR3
rcw_en bit is only available for DDR3 controllers. It is a reserved bit on
DDR1 and DDR2 controllers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 17 Mar 2011 18:18:11 +0000 (11:18 -0700)]
powerpc/mpc8572ds: revise board specific timing for dual-rank DIMMs
Tested all possible values for clk_adjust and write_data_delay for dual
rank UDIMM and RDIMM to revise the tables.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Thu, 17 Mar 2011 18:18:10 +0000 (11:18 -0700)]
powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address Parity
To recognize DIMMs with ECC capability by testing ECC bit only. Not to be
confused by Address Parity bit.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ed Swarthout [Sat, 5 Mar 2011 16:28:17 +0000 (10:28 -0600)]
strmhz: Make hz unsigned to support greater than 2146 MHz clock
For example, an input of 0x80000000 should print:
2147.484 instead of -2147.-483.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Haiying Wang [Tue, 22 Feb 2011 21:38:05 +0000 (16:38 -0500)]
Introduce a new linker flag LDFLAGS_FINAL
commit
8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --gc-sections to each uboot image.
To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace
PLATFORM_LDFLAGS in the Makefile of each nand_spl board.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Peter Barada [Mon, 21 Mar 2011 23:05:20 +0000 (19:05 -0400)]
Fix hash table deletion to prevent lost entries
Use negative used value to mark deleted entry. Search keeps probing
past deleted entries. Adding an entry uses first deleted entry when
it hits end of probe chain.
Initially found that "ramdiskimage" and "preboot" collide modulus 347,
causing "preboot" to be inserted at idx 190, "ramdiskimage" at idx 191.
Previous to this fix when "preboot" is deleted, "ramdiskimage" is
orphaned.
Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Tested-by: Wolfgang Denk <wd@denx.de>
Joakim Tjernlund [Mon, 17 Jan 2011 22:39:26 +0000 (23:39 +0100)]
Top config.mk: add include/config.mk
Seems to me that the top level config.mk should include
the auto generated include/config.mk so that all Makefile's
pickup those definitions.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Po-Yu Chuang [Fri, 21 Jan 2011 07:51:25 +0000 (15:51 +0800)]
net: ftmac100: update get_timer() usages
Use get_timer() the same way as drivers/net/ftgmac100.c
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Reviewed-by: Macpaul Lin <macpaul@gmail.com>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Po-Yu Chuang [Fri, 21 Jan 2011 07:50:37 +0000 (15:50 +0800)]
net: ftmac100: remove unnecessary volatiles
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Reviewed-by: Macpaul Lin <macpaul@gmail.com>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Heiko Schocher [Fri, 21 Jan 2011 06:23:35 +0000 (07:23 +0100)]
mpc52xx, digsy_mtc_rev5: Fix Linux crash, if no Flash in bank 2
If no Flash is connected to cs1, Linux crashes, because
reg entries are not correct adapted.
Following fix is needed:
- swap base addresses in CONFIG_SYS_FLASH_BANKS_LIST, as
flash bank 1 is on chipselect 0 and flash bank 2 on
chipselect 1
- call fdt_fixup_nor_flash_size() from ft_board_setup()
Signed-off-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <hs@denx.de>
cc: Werner Pfister <Pfister_Werner@intercontrol.de>
cc: Detlev Zundel <dzu@denx.de>
Wolfgang Denk [Mon, 21 Mar 2011 20:40:15 +0000 (21:40 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-ubi
Wolfgang Denk [Mon, 21 Mar 2011 20:38:29 +0000 (21:38 +0100)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
Stefan Roese [Mon, 14 Mar 2011 13:34:21 +0000 (14:34 +0100)]
UBI: Fix error code handling in ubi commands
Some ubi commands returned negative error codes, resulting in
the following error message on the prompt:
"exit not allowed from main input shell."
Negative error codes are not allowed.
This patch now changes the UBI code to return positive error codes.
Additionally "better" error codes are used, for example "ENOMEM" when
no memory is available for the UBI volume creation any more.
Also the output of some commands is enhanced:
Before:
=> ubi read 100000 testvol 100000
Volume testvol found at volume id 0
read 1048576 bytes from volume 0 to 100000(buf address)
=> ubi write 100000 testvol 1000
Volume testvol found at volume id 0
After:
=> ubi read 100000 testvol 100000
Read 1048576 bytes from volume testvol to
00100000
=> ubi write 100000 testvol 1000
4096 bytes written to volume testvol
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Nobuhiro Iwamatsu [Mon, 7 Mar 2011 07:36:21 +0000 (16:36 +0900)]
sh: Add KEEP order to start.o section
The start.o section is changed by --gc-section option of ld.
Of this using KEEP order, therefore, evade this problem.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Mon, 7 Mar 2011 02:21:40 +0000 (11:21 +0900)]
sh: Add handling of CONFIG_SYS_NO_FLASH for board.c
Some board of SH does not have flash memoy.
This revises it to initialize Flash when CONFIG_SYS_NO_FLASH is not
defined.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Yoshihiro Shimoda [Tue, 18 Jan 2011 08:53:45 +0000 (17:53 +0900)]
net: sh_eth: add support for SH7757's ETHER
SH7757 has ETHER and GETHER. This patch supports EHTER only.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Kumar Gala [Sun, 13 Mar 2011 15:55:53 +0000 (10:55 -0500)]
powerpc/85xx: Fix synchronization of timebase on MP boot
There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0. We can simply just read back the value to
synchronizatize the write, before we set TB to 0.
Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
John Schmoller [Thu, 10 Mar 2011 22:09:26 +0000 (16:09 -0600)]
mpc8[5/6]xx: Ensure POST word does not get reset
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors. When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word. To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Priyanka Jain [Thu, 3 Mar 2011 03:48:56 +0000 (09:18 +0530)]
fsl_esdhc: Correcting esdhc timeout counter calculation
- Timeout counter value is set as DTOCV bits in SYSCTL register
For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should
cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Matthew McClintock [Fri, 25 Feb 2011 22:20:11 +0000 (16:20 -0600)]
powerpc/85xx: Fix pixis_reset altbank mask on MPC8536DS
Currently, pixis_reset altbank does not work properly. This patch
uses the correct mask to boot into the alternate bank.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Ed Swarthout [Fri, 4 Mar 2011 00:28:14 +0000 (18:28 -0600)]
powerpc/85xx: Fix plat_mp_up() disabling of BPTR for CoreNet Platforms
Copying directly from ECM/PQ3 is not correct for how CoreNet based
platforms handle boot page translation.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Wed, 2 Mar 2011 22:24:12 +0000 (14:24 -0800)]
powerpc/corenet_ds: revise platform dependent parameters
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun [Wed, 19 Jan 2011 23:37:33 +0000 (15:37 -0800)]
corenet_ds: pick the middle value for all tested timing parameters
For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.
Signed-off-by: York Sun <yorksun@freescale.com>
York Sun [Wed, 2 Mar 2011 22:24:11 +0000 (14:24 -0800)]
powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 12 Feb 2011 21:34:08 +0000 (15:34 -0600)]
fsl_law: Fix LAW printing function
We had an extra '0x' in the output of the LAWAR header that would cause
output like:
LAWBAR11: 0x00000000 LAWAR0x11: 0x80f0001d
intead of:
LAWBAR11: 0x00000000 LAWAR11: 0x80f0001d
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Sandeep Paulraj [Wed, 16 Feb 2011 11:15:45 +0000 (11:15 +0000)]
ARM: Update mach-types
This commit updates the mach-types based on the latest
in linus's head
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>