pan/bi: Introduce TEXC_DUAL psuedoinstruction

There are two "shapes" of TEXC in the IR:

* Regular texturing. This TEXC writes a single set of staging registers.
* Dual texturing. This TEXC writes two sets of staging registers.

Currently we model both with a 2-destination TEXC, with a null second
destination for the usual case where dual texturing isn't used. This is awkward.
To make the "shapes" of instructions more predictable, make TEXC only write a
single set of staging registers (like the hardware instruction) and split off a
TEXC_DUAL pseudoinstruction for the second case, lowered late.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use bi_emit_split_i32 for trimming vecs

This ensures the shape of the split is correct (no nulls in the destination).
This should not affect the register allocation, though it does "cost" extra
variable names.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Don't remove dests in DCE

Removing dests without removing instructions only makes sense for certain
pseudo-instructions, but it makes the IR needlessly complicated for all
instructions. There's no real reason to do so, we can signal this in a different
way instead.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Register allocate BLEND dest on Valhall

On Bifrost, BLEND writes to the link register, acting like a function call. On
Valhall, BLEND does not write anything. But the BLEND instruction in our IR is a
pseudo-instruction with Bifrost semantics, expanding to a multi-instruction
sequence on Valhall. So it's not worth special casing Valhall in instruction
selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Improve register printing

Use "r0" style to denote machine registers, consistent with the assembly. Use
instead "nr0" for NIR registers so they don't collide. This reduces noise for
the average case (either register allocated or almost SSA).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Clean up destination printing

Now we can trust in I->nr_dests, avoiding a bunch of special cases and incorrect
printing for instructions without a destination. To compensate for those
instructions being hard to scan now, indent.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Remove trivial dest[0] = bi_null()

It's already NULL and will interfere with the more comprehensive src/dest
overwork we're doing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Add validation for nr_srcs/nr_dests

Now that we set nr_srcs/nr_dests accurately, assert as much in the validator.
This pass will be deleted later in the series, but having it here is expected to
be useful for bisection, in case there are cases missed. Certainly running the
CTS at this point in the series is helpful to prove completeness of the
beginning of this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Use nr_{srcs,dests} in bi_foreach_{src,dest}

This avoids crawling sources that must be null.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Consider nr_srcs/dests in CSE

Now that these are meaningful for COLLECT and SPLIT.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Model 3rd source for ATEST

ATEST on Valhall takes atest-param as an explicit encoded source. The source
also exists on Bifrost, but it's implied in the encoding. Rather than treating
it as a "ghost" source, model it in the IR explicitly so the count is correct.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Set I->nr_dests, I->nr_srcs

The builder is the primary producer of instructions, and generally the shape of
an instruction is fixed at build-time. It must set nr_dests/nr_srcs
appropriately. Likewise, when we modify sources later, we need to update
nr_srcs/nr_dests to keep everything consistent (and keep the tests passing).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/va: Split out compare instructions

The different combine modes form different instructions from each other and in
particular from the two-source version on Bifrost. Model them as such so we can
represent the relevant Valhall-specific lowering/optimizations accurately in the
compiler.

This requires updating the unit tests to use the new names since there's not
much point keeping around the aliases.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Model [IF]CMP_{OR,AND,MULTI} ops

Valhall-style comparisons are 3-source, allowing multiple comparisons to be
combined without bitwise arithmetic. For example, the sequence

   FCMP.f32.eq t, z, w
   FCMP_AND.f32.eq dest, x, y, t

calculates (z == w) && (y == t) in 2 instructions (would be 3 on Bifrost).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Consider all dests in helper_block_update

If an instruction has multiple destinations and *any* of them are needed by
helper invocations, we should keep helper invocations alive. This is a bug fix.
Consider the GLSL:

   first = texture(sampler, ...);
   float res = texture(sampler, vec2(first.y)).x + first.x;

Corresponding to the IR:

   first = ...
   x, y, z, w = SPLIT first
   second = TEX y, y
   x', y', z', w' = SPLIT second
   FADD res, x, x'

Here, x is not required by helper invocations (the coordinates to TEX) while y
is required. If we only look at only the first destinations, we incorrectly
decide that first is not required and fail to set the .skip bit, leading to
incorrect results.

Fixes: 5febeae58e0 ("pan/bi: Emit collect and split")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

pan/bi: Fix out-of-bounds write in va_lower_split_64bit

...with dual source blending. Fixes shaders/dolphin/smg.1.shader_test

There are more IR sources than Valhall machine sources here.

Fixes: b48933d6411 ("pan/va: Include BLEND for va_swap_12")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>

gallium/hud: Fixes compile error in hud/hud_context.c:

../../src/gallium/auxiliary/hud/hud_context.c:1017:1: error: static declaration of 'access' follows non-static declaration
These error will shown when any header #include <io.h>

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18333>

r600: fix warnings for missing-braces on clang

[2624/3754] Compiling C++ object src/gallium/drivers/r600/sfn/tests/libr600_test.a.p/sfn_test_shaders.cpp.o
../src/gallium/drivers/r600/sfn/tests/sfn_test_shaders.cpp:3066:27: warning: suggest braces around initialization of subobject [-Wmissing-braces]
   r600_shader_key key = {0};
                          ^
                          {}
1 warning generated.
[2711/3754] Compiling C++ object src/gallium/drivers/r600/libr600.a.p/sfn_sfn_nir_lower_64bit.cpp.o
../src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp:910:33: warning: suggest braces around initialization of subobject [-Wmissing-braces]
      nir_const_value val[4] = {0};
                                ^
                                {}
../src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp:1328:38: warning: suggest braces around initialization of subobject [-Wmissing-braces]
      nir_ssa_scalar channels[4] = { 0 };
                                     ^
                                     {}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18307>

d3d12: fix warnings for missing-braces on clang

[3485/3754] Compiling C++ object src/gallium/drivers/d3d12/libd3d12.a.p/d3d12_screen.cpp.o
../src/gallium/drivers/d3d12/d3d12_screen.cpp:56:65: warning: suggest braces around initialization of subobject [-Wmissing-braces]
static GUID OpenGLOn12CreatorID = { 0x6bb3cd34, 0x0d19, 0x45ab, 0x97, 0xed, 0xd7, 0x20, 0xba, 0x3d, 0xfc, 0x80 };
                                                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                                {                                             }

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18307>

llvmpipe: don't assume pipe_context is always available in flush_frontbuffer

Fixes: 91dcadf9569 ("llvmpipe: finish rendering before flushing frontbuffer resources.")

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18392>

pan/bi: Fix dual texturing with uniforms

The GLSL code sequence:

   texture2D(tex0, u_coords) + texture2D(tex1, u_coords)

will be optimized to

   TEXC_DUAL tex0/tex1, u_coords, #texture_descriptor

If this optimization happens after lowering FAU, the resulting TEXC instruction
is unschedulable: both the uniform and the constant descriptor fight for the
same FAU slot.

However, if this optimization happens before lowering FAU, then the FAU lowering
will move the descriptor into a register, complicating the dual texturing fixup
in RA.

To fix this interaction, fuse dual texturing before lowering FAU and keep
texture descriptors as constants when lowering FAU of TEXC.

Fixes scheduling failure in piglit drawoverhead -test 3 with uniform reordering.

Fixes: a4d3a296477 ("pan/bi: Enable dual texture fusing pass")
Fixes: 6b2eda6b729 ("pan/bi: Reorder pushed uniforms to avoid moves")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18378>

mesa/st: do not blit when using compressed fallback

If we're using the blit-path, we don't update the compressed image, which
will be needed if an application try to download the texture-image again
afterwards.

I previously fixed this for the memcpy-codepath, but we actually need to
fall back for the blit code-path as well. So let's move this early-out
earlier to catch both.

Fixes: 8f446322e1b ("mesa/st: do not use memcpy when using compressed fallback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18342>

anv/hasvk: tweak loading failure messages

We don't want to print out too many :

  MESA: error: ../src/intel/vulkan/anv_device.c:769: anv does not support Intel(R) HD Graphics (HSW GT1); use hasvk (VK_ERROR_INCOMPATIBLE_DRIVER)

whenever anv is not able to load on a HSW device. Similarly hasvk
should not print error on anything gfx9+.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Remove anv_batch_emit_reloc and just open-code it

We don't need the relocation offsets anymore, and just want to pin the
BO, and combine the address into a uint64_t.  We can just open code
those two things; it's actually less code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Inline write_reloc into the only remaining caller

This is writing an address and clflushing, but it's not really about
execbuf relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Drop offset from anv_reloc_list_append

No longer used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Make a helper function for pinning a state pool's BOs

A bit less duplicated code, though with all the success checking, it
doesn't actually save us a whole lot.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete has_bindless_images and has_bindless_samples flags

These are always true now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete has_a64_buffer_access flag

It's always true.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete relocation support from batch submission

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete wrapper BOs for relocations

These were only used in the non-softpin case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete anv_reloc_list_add()

We don't need the offset to write a relocation at any longer, so all
it does is call anv_reloc_list_add_bo() at this point.  Just use that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete softpin checks

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete use_relocations flag

There are no relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Drop state pool relocation munging

Now that the state pool's center is always 0, this is not needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete "back" allocation from anv_block_pool

This was only used with relocations.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete relocation support from anv_block_pool

We no longer use relocations.

v2: silence fedora builder warning

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete "back" allocation from state pool

This was only used with relocations, which no longer happen.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv/tests: Don't use relocations in a test case

We won't support relocations shortly.

v2: Deal with softpin padding requirement (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv/tests: remove back allocation tests

We'll remove driver code for this in the following commits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete shader constants UBO from descriptor sets

We now always softpin and use the load_global_constant case, so there's
no need to set up a UBO for NIR constants.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete batch buffer growing code.

This was only needed on Haswell and older due to the kernel command
parser not allowing us to chain batches.  anv no longer support this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Delete image param support.

This was only used prior to Skylake, which anv no longer supports.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Drop checks for version 8 or 9

anv no longer supports versions below this.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: Fail to create a device on ver < 9

These are now only supported by hasvk.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: remove unused gfx7 code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: remove support for gfx7/8

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

anv: silence fedora build warning

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove mesh code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove ray tracing code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove acceleration structure code

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: stop advertising Vk 1.3 on non-softpin

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

hasvk: remove entrypoints for gfx9+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

intel: add a hasvk vulkan driver

This new driver is a copy of the current Anv code, it will only load
on gfx7/8 platforms though.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>

pvr: remove image pointer from image view struct

A pointer is also stored in the base vk_image_view struct, so we can use this
one instead.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18373>

intel/pci_ids: Add dg2 0x5698 pci-id

This motherboard-down pci-id was added in kernel commit 8618b8489ba6
("drm/i915: DG2 and ATS-M device ID updates").

Ref: bspec 44477
Ref: https://patchwork.freedesktop.org/patch/msgid/20220701152231.529511-2-matthew.d.roper@intel.com
Fixes: ad565f6b70d ("intel/dev: Enable first set of DG2 PCI IDs")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18385>

radeonsi/ci: trigger radeonsi-raven-skqp for any RADV changes

Otherwise SKQP VK won't be run.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7120
Co-authored-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18316>

intel/pci_ids: Update DG2 device names

Ref: bspec 44477
Ref: https://www.intel.com/content/www/us/en/products/details/discrete-gpus/arc/arc-a-series.html
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18303>

intel/pci_ids: Update ATS-M device names

Ref: bspec 44477
Ref: https://www.intel.com/content/www/us/en/products/details/discrete-gpus/data-center-gpu/flex-series/products.html
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18303>

meson: Only draw with llvm depends on native directly
Tests, softpipe or AMD drivers don't depend on it directly

Fixes: 3955dd07 ("meson/gallium: Add an option to not use LLVM for gallium draw module")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6817

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17675>

ci/fedora: Re-enable vulkan-layers=device-select,overlay

Fixes: ace13203f30 ("ci: remove broken device-select-layer from build")

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: Add debian-clang-release build pipeline

As the default build type is debug according to
.gitlab-ci/meson/build.sh, the specified line is:
-D buildtype=${BUILDTYPE:-debug}

So we use release for building optimized version for testing
if the compiler optimization are fine.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: Enable all possible meson build options for clang

By doing this to makes more code be compiled with clang and guarded by bot

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: Enable GALLIUM_DUMP_CPU=true only in the clang job

This is used to show the cpu caps when running unit tests.
As clang have optimization bug about util_get_cpu_caps before, so
we monitor it by using GALLIUM_DUMP_CPU=true

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

ci: EXTRA_OPTIONS -> EXTRA_OPTION for debian-clang

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18044>

util: Add macro util_get_cpu_caps in u_cpu_detect.c for avoid accidentally call it in u_cpu_detect.c

Signed-off-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

docs: document LP_NATIVE_VECTOR_WIDTH GALLIUM_OVERRIDE_CPU_CAPS GALLIUM_NOSSE LP_FORCE_SSE2

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

llvmpipe: Enable avx512 support in llvm

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

llvmpipe: Always using util_get_cpu_caps to get cpu caps for llvm on x86

As we can override cpu features with environment variables, so always using util_get_cpu_caps
instead llvm::sys::getHostCPUFeatures to get cpu features is a better option

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

util: add support for detecting avx512 vector bit size

Default to 256 until we're confident llvmpipe with 512 is
as correct and not slower than 256

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

util: Move the detect of max_vector_bits into u_cpu_detect.c

has_avx2 implies has_avx, so have no need check then both

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

util: Add ssse3 and avx cpu caps override option

llvmpipe can use these options to testing ssse3 and avx on cpus that support for avx512

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

util: Refactoring check_cpu_caps_override out

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

meson: bump the minimal required llvm version to 5.0.0

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

llvmpipe: Remove llvm version guard LLVM_VERSION_MAJOR <=> 4

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17813>

venus: Fix dEQP-VK.pipeline.timestamp.calibrated.host_domain_test failure

The current implementation is getting its clock value from the host
and this value is not guaranteed to be the same as the VM guest.

This commit implements the CLOCK_MONOTONIC[_RAW] natively.

Signed-off-by: Igor Torrente <igor.torrente@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18281>

radv: anv: Use the new vk_clock_gettime and vk_time_max_deviation
functions

Removes the duplicated code and start using the new common
code.

v2: split anv/radv parts to separate commits

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Signed-off-by: Igor Torrente <igor.torrente@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18281>

vulkan: Add vk_clock_gettime and vk_time_max_deviation

These two new function are based on {anv,radv}_clock_gettime
and some other common code between radv and anv.

These new functions allow these drivers to share code and
more drivers can use it in the future.

v2: Drop the anv/radv changes in this commit (Yiwei Zhang)
v3: Add #ifndef _WIN32

Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Signed-off-by: Igor Torrente <igor.torrente@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18281>

freedreno: get cpu timestamp again after FD_TIMESTAMP

Same as commit 91a0411d2ab ("turnip: improve perfetto sync_timestamp"),
but for freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18379>

vulkan: initialize a variable

../src/vulkan/runtime/vk_fence.c: In function ‘vk_common_CreateFence’:
../src/vulkan/runtime/vk_fence.c:160:12: warning: ‘fence’ may be used uninitialized [-Wmaybe-uninitialized]
  160 |    *pFence = vk_fence_to_handle(fence);
      |    ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/vulkan/runtime/vk_fence.c:154:21: note: ‘fence’ was declared here
  154 |    struct vk_fence *fence;

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18119>

zink: don't emit illegal interpolation

this is not valid for vertex inputs or fragment outputs

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18365>

zink: don't set MUTABLE by default

this is only used by texture views, so use the same mechanism as STORAGE
to add the flag only as-needed

the mutable flag must be set before create_ivci is called for the imageview,
so zink_resource_object_init_mutable() is moved out to the callers of
zink_get_surface instead of being conveniently located in that function

fixes #7174

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>

zink: avoid needing mutable for z/s sampling

the aspect flags should be sufficient to determine which component the
imageview is created for, which means this can avoid changing the format
here to retain the immutable format

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>

zink: only add srgb mutable for images with modifiers

these are supposed to be for dmabuf handling, so checking for mutable
swapchain is both pointless and wrong

Fixes: 28ee911ad67 ("zink: handle mutable swapchain images with dmabuf")

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>

zink: store VkImageViewUsageCreateInfo for surface creation

this otherwise breaks surface rebinds if used since the pointer
will be a garbage stack value

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>

zink: explicitly use unsigned types for bit shifts

fixes some ubsan errors

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18358>

turnip: Enable lowering of mediump temps/CS shared to 16-bit.

In Aztec Ruins, we end up storing some big shared-mem arrays as 16-bit,
cutting shared mem size in half across many shaders while also reducing
conversions.  gfxbench vk-5-normal perf +0.364983% +/- 0.189764% (n=4).

fossil-db:
Totals from 448 (2.99% of 14988) affected shaders:
MaxWaves: 6154 -> 6390 (+3.83%); split: +3.96%, -0.13%
Instrs: 174554 -> 165045 (-5.45%); split: -6.45%, +1.01%
CodeSize: 364224 -> 345558 (-5.12%); split: -6.03%, +0.90%
NOPs: 48224 -> 48024 (-0.41%); split: -3.33%, +2.91%
MOVs: 6985 -> 6104 (-12.61%); split: -19.11%, +6.50%
Full: 4577 -> 4101 (-10.40%); split: -11.08%, +0.68%
(ss): 3428 -> 3335 (-2.71%); split: -4.17%, +1.46%
(sy): 1250 -> 1205 (-3.60%); split: -4.72%, +1.12%
(ss)-stall: 14695 -> 14528 (-1.14%); split: -2.25%, +1.12%
(sy)-stall: 19565 -> 17998 (-8.01%); split: -9.55%, +1.54%
STPs: 1086 -> 870 (-19.89%)
LDPs: 162 -> 108 (-33.33%)
Cat0: 51400 -> 51120 (-0.54%); split: -3.31%, +2.76%
Cat1: 16861 -> 14688 (-12.89%); split: -18.18%, +5.30%
Cat2: 71161 -> 68454 (-3.80%); split: -4.52%, +0.72%
Cat3: 29572 -> 25306 (-14.43%); split: -14.49%, +0.06%
Cat4: 3128 -> 3131 (+0.10%)
Cat5: 1502 -> 1506 (+0.27%)
Cat6: 840 -> 750 (-10.71%)

aztec ruins is a big winner with the ldp/stp reductions.  summoners_war
racks up an astounding 41% reduction in instructions and +15% max_waves.
Most affected apps show a minor win in instrs, with
fallout_shelter_online, and aztec ruins on ANGLE taking minor hits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>

spirv: Mark phis as mediump instead of directly lowering them to 16 bit.

This reverts commit 6f25d45877a1e1a7ac6250a7d051d33485e0cba7, replacing it
with GLSL_PRECISION_MEDIUM.  The previous commit ended up not being the
right approach, as it affected only nir vars for spirv phis and not other
nir vars, and we want a tool that does both.  The new
nir_lower_mediump_vars pass can do that for you.

No fossil-db change for my angle fossils run on radv.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>

nir: Add a pass to lower mediump temps and shared mem.

SPIRV and GLSL are reasonable at converting ALU ops to mediump, but
variable storage would be wrapped in a 2f32/2mp on store/load, and if
nir_vars_to_ssa doesn't make that storage go away then you'd have extra
conversions.  For compute shader shared mem, you'd waste memory too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18259>

ail: Add unit tests for miptree layouts

The equations for calculating miptree offsets are complicated,
nonobvious, and full of subtle footguns. Worse, the driver doesn't
control the offsets -- it must simply agree with the offsets
implicitly calculated in the hardware. The CTS doesn't adequately
exercise all the corner cases. Make sure we have unit tests that do.

The tests themselves are generated by instrumenting agxdecode to scan
GPU memory after uploading test patterns in a variety of layout with a
Metal application.

Thank you to Asahi Lina and Dougall Johnson for the reverse-engineering
that led to this. The tests selected here are a subset of those used for
the reverse-engineering. The full set may be found in Lina's tilecalc
repo:

   https://github.com/asahilina/tilecalc

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Rename our fake twiddled DRM modifier

To account for non-64x64 tile sizes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Advertise ASTC formats

Now that we have layout and tiling code that can handle block-compressed
formats, including the non-square blocks found with some ASTC formats,
we can advertise ASTC formats. Passes dEQP-GLES3.*astc* which
exercises everything here. (These tests passed before by decompressing
the textures to RGBA8 UNORM in the frontend, but it's much more
efficient to use real ASTC textures as done here.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Advertise ETC1

ETC2 is backwards compatible with ETC1, we just need to declare the
format mapping.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Fix is_format_supported returns

Gallium can test multiple binds at once, we need to return the logical
AND, not the OR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Handle 2-channel sRGB textures

I'm not sure why we need to set this magic bit, but this fixes the
non-depth_component portion of
dEQP-GLES3.functional.texture.format.sized.*, e.g

dEQP-GLES3.functional.texture.format.sized.cube.srgb_rg8_pot

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

ail: Rewrite tiled memcpy for correctness

Move tiling.c into ail, using ail data structures and helpers to manage
the tiling. This fixes a staggering number of issues with the tiling
routines:

* NPOT block sizes defeatured. The hardware only supports POT block
  sizes. There's no need to handle anything else.

* Use ail to determine tile sizes, instead of the broken
  agx_select_tile_shift routine that didn't work for non-square tile
  sizes (for instance).

* Handle up to 128x128 tiles, as required by 8bpp textures.

* Handle non-square tiles. If the block size is not a multiple of 4, the
  tile size will be of the form 2n x n. This is easy with the ail_tile
  data structure, but not possible architecturally with
  agx_select_tile_shift. This is required for 16bpp and 64bpp textures.

* Express in terms of elements instead of pixels, using unit
  suffixes to make the dimensional analysis obvious. In particular this
  handles tiling of block-compressed textures by tiling the blocks
  themselves. This is required for block-compressed textures (internally handled
  like smaller 64bpp textures).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

ail: Introduce image layout module

Introduce ail, a small library for working with the image (and buffer)
layouts encountered with AGX hardware. Its design is inspired by isl. In
particular, ail strives to use isl unit suffixes and to represent
quantities in a canonical, API-agnostic fashion [1].

ail replaces the old miptree code (based on some ad hoc heuristics that
passed a few dEQP tests). It is based on a thorough reverse-engineering
of AGX's twiddled format, courtesy of Asahi Lina, Dougall Johnson, and
me. This corrects our handling of many common cases that were totally
wrong in the old code, leading to GPU faults.

Unlike the code, ail differentiates between pixels and elements
consistently, allowing block-compressed formats like ETC2 to be
supported correctly. These formats will be enabled later in the series.

This commit fixes Inochi2D, glmark2 -brefract and -bterrain, and who
knows what else.

ail stands for { Asahi, AGX } Image { Layout, Library } at your
convenience. ail is best served warm.

Liberal use of ail is recommended. Yum!

[1] https://docs.mesa3d.org/isl/units.html

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Fix ASTC enums

The ASTC enum only encodes the block width/height. By contrast the
LDR/HDR/sRGB distinction is encoded as UNORM/Float and via the sRGB bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Fix bind sizes

Otherwise we get a nonsensical count of 129 in one Metal sample. Exact
size still not known but this bounds somewhat.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>

asahi: Add XML for multisampled textures

Metal supports MSAA 2x and MSAA 4x, neither at the same time as
mipmapping. That matches the GL spec requirement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>