Daniel Stone [Fri, 8 Sep 2023 11:17:37 +0000 (12:17 +0100)]
ci: Declare stages before jobs
It looks like GitLab 16.x requires us to declare the stages before we
declare any jobs, else it falls down resolving 'needs' with 'job is not
in any earlier stage'.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25149>
Alba Mendez [Sun, 27 Aug 2023 14:35:17 +0000 (16:35 +0200)]
meson: support installation tags
the only thing missing is to tag custom install targets, namely:
- ICDs (vulkan, glvnd, OpenCL, VA-API, VDPAU)
- Vulkan layers
- custom install script for megadrivers
- drirc file
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24911>
Iago Toral Quiroga [Thu, 7 Sep 2023 09:12:13 +0000 (11:12 +0200)]
v3dv: expand sampling from linear image hack to support multi-planar images
Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25048>
Iago Toral Quiroga [Thu, 31 Aug 2023 11:14:19 +0000 (13:14 +0200)]
v3dv: add support for sampling simple 2D linear textures
V3D can't sample linear images (other than 1D), however, some applications
will require this to work. Particularly, our swapchain images may need to be
linear (for display), so sampling from them won't work.
This change detects the case where we are binding a descriptor which attempts
to sample from a simple 2D linear texture, transparently creates a tiled
copy of the image and rewrites the descriptor to refer to the tiled image
instead. This will be slow but will allow some applications that require this
to work (i.e. some aspects of Android's user interface).
As of this patch, this only supports sampling linear images with a single
miplevel and layer from single-plane images in non-arrayed descriptors. We
could handle other cases too with a bit more work though.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9712
Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25048>
Sergi Blanch Torne [Mon, 11 Sep 2023 07:51:36 +0000 (09:51 +0200)]
Revert "ci: disable Collabora's LAVA lab for maintance"
This reverts commit https://gitlab.freedesktop.org/mesa/mesa/-/commit/
c558c4955053eeb9476acefa148d414ff71cb47d
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25143>
Roman Stratiienko [Sun, 10 Sep 2023 10:19:54 +0000 (13:19 +0300)]
v3dv: Rely on the internal tiled flag instead of the common vk structure
Common vk.tiling can have 3 states:
VK_IMAGE_TILING_OPTIMAL = 0,
VK_IMAGE_TILING_LINEAR = 1,
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT =
1000158000,
The latter is checked by [1]
In this case, actual tiling can be either linear or tiled;
therefore, logic in v3dv_meta_copy will not work correctly.
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/blob/
39fca243bb914cea853e9d3502f1f38e6bf96ad4/src/vulkan/runtime/vk_image.c#L158
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25139>
Connor Abbott [Wed, 17 May 2023 14:07:45 +0000 (16:07 +0200)]
tu: Split program draw state into per-shader states
This completely rewrites how uploading variants and emitting the program
state works, which will make fast linking significantly faster and lays
some of the groundwork for EXT_shader_objects. Variants are now
compiled and uploaded as part of creating a tu_shader, and a
a per-stage draw state is also created that contains all registers that
are only set based on one stage. The program state is split into
per-stage states, which come from the shaders, and VPC state which is
emitted at linking time. Pipelines now contain shaders, and importing
shaders from libraries when fast-linking just involves taking a
reference on the shader. While the command buffer code still uses the
old pipeline structures, the plan is to switch more and more things to
directly use the shaders or derived state from the shaders that gets set
by the pipeline, so that we can eliminate pipeline usage from
tu_cmd_buffer.cc to enable ESO.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Wed, 17 May 2023 13:02:09 +0000 (15:02 +0200)]
ir3: Add helper to determine when variant exceeds safe constlen
This will help us not compile extra variants as often in the unlinked
case, which will become the only case on turnip.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Wed, 17 May 2023 13:00:46 +0000 (15:00 +0200)]
freedreno, ir3, tu: Constify various uses of ir3_shader_variant
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Thu, 11 May 2023 11:33:16 +0000 (13:33 +0200)]
tu: Split up tu6_emit_vpc()
This started out as a place to set linkage-related registers, but it
gradually became a grab-bag of different things. In the future each
stage will have its own draw state, so we split out the parts that only
depend on a single stage into separate functions. Each piece of state we
can split out is another piece of state that won't have to be emitted
while fast-linking.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Thu, 11 May 2023 11:28:55 +0000 (13:28 +0200)]
ir3: Add ir3_find_input_loc() helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 18:22:55 +0000 (20:22 +0200)]
tu: Pull entangled shader state into program config
There are a few cross-stage states that we absolutely have to wait to
emit until we know more than one stage. Pull these into the program
config draw state, so that we can split up the program draw state into a
per-stage draw state. For VK_EXT_shader_object, these will have to
emitted at draw time.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 17:59:54 +0000 (19:59 +0200)]
tu, freedreno/a6xx: Don't use VS for PrimID passthru state
Emit the registers solely based on whether FS reads PrimID, and assume
the HW will do the right thing and disable PrimID passthru when GS is
enabled. This untangles these registers so we can set them from the FS
draw state in the future.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 17:37:21 +0000 (19:37 +0200)]
tu: Rename PrimID-related registers
It turns out that the hardware automatically selects whether PrimID
passthrough needs to happen based on whether GS is enabled, which means
that it's safe to always set these registers based whether PrimID is
read by the FS and the hardware will ignore them when GS is enabled. Use
the real names for these registers to make it less confusing when we
start to do that.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 15:29:57 +0000 (17:29 +0200)]
tu: Merge depth/stencil draw states
This removes more draw states that are commonly set together. We still
have a separate draw state for RB_DEPTH_CNTL, because it depends on
other things like the attachment state and depth clamp and it would be
more difficult for layers like zink to use a combined depth/stencil
state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 14:04:08 +0000 (16:04 +0200)]
tu: Stop reusing base Vulkan dynamic state enums
We're about to remove the 1:1 correspondance between base Vulkan 1.0
dynamic states and draw states.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 13:49:34 +0000 (15:49 +0200)]
tu: Merge PC_RASTER_CNTL into RAST draw state
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 13:31:35 +0000 (15:31 +0200)]
tu: Merge SAMPLE_LOCATIONS and SAMPLE_LOCATIONS_ENABLE draw states
There's no need to separate them except that it was easier before, no
one will enable the second without also enabling the first. Now that
mesa will merge the states for us we can go ahead and merge them.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Connor Abbott [Tue, 9 May 2023 13:16:17 +0000 (15:16 +0200)]
tu: Remove MSAA draw state
We only need to emit MSAA state once per subpass at most, unless the
pipeline switches primitive types or for framebuffer-less subpasses
(which always use sysmem anyway). Therefore it seems like draw state
skipping isn't going to bring much benefit here, and having it as a draw
state in the first place is a remnant of how this used to be part of the
pipeline state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>
Iván Briano [Sat, 9 Sep 2023 01:46:29 +0000 (18:46 -0700)]
anv: tell blorp to do mesh stuff only if it's enabled
Otherwise blorp operations will set dirty bits for mesh that we don't
expect at pipeline state emission time.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Iván Briano [Sat, 9 Sep 2023 00:04:29 +0000 (17:04 -0700)]
anv: ensure pipelines have all state
While we don't need to emit all of the unused mesh/task states when mesh
is disabled, if we don't have them we fail some assertions in the
difference checks due to the corresponding state being empty.
This may happen when going from a mesh pipeline to a non-mesh one, or
one that uses task shaders to one that doesn't.
It may be possible to avoid having to do this, but I'd rather start from
a working state and optimize it later.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Iván Briano [Sat, 9 Sep 2023 00:11:29 +0000 (17:11 -0700)]
anv: fix missing 3DSTATE_SBE_CLIP emission
Fixes:
50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Lionel Landwerlin [Fri, 8 Sep 2023 06:46:29 +0000 (09:46 +0300)]
anv: fix missing 3DSTATE_SBE_MESH emission
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Lionel Landwerlin [Fri, 8 Sep 2023 06:38:32 +0000 (09:38 +0300)]
anv: ensure partially packed instructions are emitted in the pipeline
Any partially packed instructions should always be pre-packed by
genX_pipeline.c
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Lionel Landwerlin [Fri, 8 Sep 2023 06:37:12 +0000 (09:37 +0300)]
anv: ensure mesh pipeline have all pre-rasterization stages disabled
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
44656f98d5 ("anv: split pipeline programming into instructions")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Lionel Landwerlin [Fri, 8 Sep 2023 06:09:50 +0000 (09:09 +0300)]
anv: emit 3DSTATE_URB_ALLOC_(MESH|TASK) only when mesh shaders are enabled
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Lionel Landwerlin [Fri, 8 Sep 2023 06:08:21 +0000 (09:08 +0300)]
anv: fix 3DSTATE_VFG emission
3DSTATE_VFG was moved into a section that only gets emitted for legacy
pipelines, not mesh pipelines.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
0ce772bd19 ("anv: split 3DSTATE_VFG emission")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>
Ganesh Belgur Ramachandra [Wed, 16 Aug 2023 12:03:38 +0000 (07:03 -0500)]
radeonsi: sets OPTIMAL_BIN_SELECTION to 0 if using bottom_edge_rule
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24725>
Ganesh Belgur Ramachandra [Wed, 16 Aug 2023 12:01:12 +0000 (07:01 -0500)]
radeonsi: stores bottom_edge_rule option in the rasterizer state
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24725>
Corentin Noël [Mon, 11 Sep 2023 07:15:45 +0000 (09:15 +0200)]
ci: disable Collabora's LAVA lab for maintenance
This is to inform you of some planned downtime in the LAVA lab as follows:
* Start: 2023-09-11 08:00 BST (UTC+1)
* End: 2023-09-11 12:00 BST (UTC+1)
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25141>
Samuel Pitoiset [Fri, 8 Sep 2023 16:56:14 +0000 (18:56 +0200)]
radv: fix enabling DGCC
This was broken if only DGC (graphics) is enabled.
Fixes:
559da067559 ("radv: implement NV_device_generated_commands_compute")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25126>
Dave Airlie [Fri, 25 Aug 2023 02:43:44 +0000 (12:43 +1000)]
clover/llvm: move to modern pass manager.
This seems like it should work, but I haven't tested it yet.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24879>
Erico Nunes [Sun, 3 Sep 2023 21:45:01 +0000 (23:45 +0200)]
lima: fix plbu block stride calculation
For some specific texture sizes, notably some texture sizes with width
4096, block stride calculation could end up calculating stride 256 which
is an invalid value.
In those specific cases, this could cause rendering artifacts or
application/driver crashes.
Cc: mesa-stable
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25084>
Konstantin Seurer [Fri, 8 Sep 2023 06:47:00 +0000 (08:47 +0200)]
radv/rt: Enable monolithic pipelines
Store can_inline inside the stages to avoid rerunning the analysis pass
for library stages.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>
Konstantin Seurer [Mon, 21 Aug 2023 11:32:53 +0000 (13:32 +0200)]
radv/rt: Add monolithic raygen lowering
Ray traversal is inlined to allow for constant folding and avoid
spilling.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>
Konstantin Seurer [Sat, 24 Jun 2023 13:46:51 +0000 (15:46 +0200)]
radv/rt: Store NIR shaders separately
In order to compile monolithic shaders with pipeline libraries, we need
to keep the NIR around for inlining recursive stages.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>
Mike Blumenkrantz [Tue, 5 Sep 2023 16:37:29 +0000 (12:37 -0400)]
nir/inline_uniforms: fix oob access with nir_find_inlinable_uniforms
the array dimensionality needs to match nir_add_inlinable_uniforms even if
only the first member is used
Fixes:
0c0fb216dd6 ("nir/inline_uniforms: Allow possibility of more than one UBO")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25063>
Mike Blumenkrantz [Thu, 10 Aug 2023 14:05:36 +0000 (10:05 -0400)]
zink: delete all psiz=1.0 stores if maintenance5 is present
this frees up an output location woooo
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24782>
Mike Blumenkrantz [Thu, 10 Aug 2023 13:53:01 +0000 (09:53 -0400)]
zink: slightly refactor psiz deletion during linking
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24782>
Eric Engestrom [Fri, 8 Sep 2023 08:54:32 +0000 (09:54 +0100)]
Revert "ci: taking igalia farm offline"
This reverts commit
a69ffbd08a44032d0f12c5739382cefc8a5d7f50.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25136>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:09:47 +0000 (11:09 -0400)]
zink: use HIC for image subdata when possible
this has a lot of caveats:
* extension must be supported
* resource must have usage bit set
* resource must not have any pending batch usage
* resource must be in supported layout
if all of these conditionals pass, then HIC can be used for direct image subdata
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:08:59 +0000 (11:08 -0400)]
zink: check/use suboptimal HIC during ici init
this allows implicit use of HIC where possible while rejecting it when
it would cause performance loss
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Mon, 21 Aug 2023 13:30:17 +0000 (09:30 -0400)]
zink: use some return codes for check_ici errors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Mon, 21 Aug 2023 13:24:27 +0000 (09:24 -0400)]
zink: fix some off-by-one indentation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:06:49 +0000 (11:06 -0400)]
zink: add a fixup method for extra driver props
some extensions have "extra" props which need the get_count -> get_prop_array
dance, and codegen is too stupid to figure this out (and probably always will be)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 25 Aug 2023 16:55:43 +0000 (12:55 -0400)]
zink: disable HIC without resizable BAR
this otherwise ooms the system
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 25 Aug 2023 16:54:19 +0000 (12:54 -0400)]
zink: move mem type detection up in file
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:04:30 +0000 (11:04 -0400)]
zink: hook up VK_EXT_host_image_copy
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Wed, 23 Aug 2023 20:02:08 +0000 (16:02 -0400)]
lavapipe: don't advertise UNDEFINED layout for HIC
this is illegal
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 14:07:37 +0000 (10:07 -0400)]
lavapipe: handle VkHostImageCopyDevicePerformanceQueryEXT
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 13:39:58 +0000 (09:39 -0400)]
zink: use VkFormatProperties3
but wrap it in a smaller type to save some space
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Wed, 16 Aug 2023 10:58:22 +0000 (06:58 -0400)]
zink: simplify redundant is_buffer check
it's in the params
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Tue, 29 Aug 2023 11:23:21 +0000 (07:23 -0400)]
ci: bump VVL to 1.3.263
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24925>
Jordan Justen [Wed, 6 Sep 2023 06:26:22 +0000 (23:26 -0700)]
intel/dev: Update device string for MTL PCI ID 0x7d55
Ref: bspec 55420
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25073>
Faith Ekstrand [Fri, 8 Sep 2023 23:18:52 +0000 (18:18 -0500)]
nvk: Invalidate the texture cache in PipelineBarrier
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>
Faith Ekstrand [Fri, 8 Sep 2023 23:05:01 +0000 (18:05 -0500)]
nvk: Set the discard bit for Z/S self-deps
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>
Faith Ekstrand [Fri, 8 Sep 2023 22:29:47 +0000 (17:29 -0500)]
nvk: Don't add a dummy attachment when gl_SampleMask is written
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>
Ian Romanick [Thu, 18 May 2023 22:14:16 +0000 (15:14 -0700)]
intel/compiler: Don't evict for workgroup-scope fences
Flushing and invalidating caches isn't necessary for workgroup scope
fences. In fact, the DP_FLUSH_TYPE docs (BSpec 54041) say:
"If the fence scope is Local or Threadgroup, HW ignores the flush
type and operates as if it was set to None(no flush)"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Ian Romanick [Tue, 16 May 2023 19:21:52 +0000 (12:21 -0700)]
intel/compiler: Combine control barriers with identical memory semantics
This prevents the second barrier generating a spurious, identical fence
message as the first barrier.
fossil-db stats on Alchemist:
Totals:
Instrs:
196513342 ->
196512777 (-0.00%); split: -0.00%, +0.00%
Cycles:
14271426028 ->
14271404569 (-0.00%); split: -0.00%, +0.00%
Send messages: 8021892 -> 8021770 (-0.00%)
Totals from 46 (0.01% of 653252) affected shaders:
Instrs: 76761 -> 76196 (-0.74%); split: -0.75%, +0.01%
Cycles: 2027946 -> 2006487 (-1.06%); split: -1.45%, +0.39%
Send messages: 7589 -> 7467 (-1.61%)
Nothing in shader-db was affected.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 17:40:40 +0000 (10:40 -0700)]
anv: Use nir_opt_barrier_modes() to drop unnecessary barriers
fossil-db stats on Alchemist:
Totals:
Instrs:
196514947 ->
196513342 (-0.00%); split: -0.00%, +0.00%
Cycles:
14271450761 ->
14271426028 (-0.00%); split: -0.00%, +0.00%
Send messages: 8022316 -> 8021892 (-0.01%)
Totals from 43 (0.01% of 653252) affected shaders:
Instrs: 98558 -> 96953 (-1.63%); split: -1.63%, +0.00%
Cycles:
15867801 ->
15843068 (-0.16%); split: -0.17%, +0.02%
Send messages: 8997 -> 8573 (-4.71%)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 17:38:55 +0000 (10:38 -0700)]
glsl: Use nir_opt_barrier_modes() to drop unnecessary barriers
iris shader-db stats on Alchemist:
total instructions in shared programs:
23150249 ->
23142733 (-0.03%)
instructions in affected programs: 157322 -> 149806 (-4.78%)
helped: 105
HURT: 2
helped stats (abs) min: 2 max: 821 x̄: 71.61 x̃: 15
helped stats (rel) min: 0.13% max: 27.56% x̄: 6.21% x̃: 2.35%
HURT stats (abs) min: 1 max: 2 x̄: 1.50 x̃: 1
HURT stats (rel) min: 0.18% max: 0.23% x̄: 0.20% x̃: 0.20%
95% mean confidence interval for instructions value: -101.99 -38.50
95% mean confidence interval for instructions %-change: -7.59% -4.58%
Instructions are helped.
total sends in shared programs: 1036916 -> 1035366 (-0.15%)
sends in affected programs: 15274 -> 13724 (-10.15%)
helped: 108 / HURT: 0
helped stats (abs) min: 1 max: 162 x̄: 14.35 x̃: 3
helped stats (rel) min: 0.88% max: 33.83% x̄: 9.81% x̃: 5.05%
95% mean confidence interval for sends value: -20.79 -7.92
95% mean confidence interval for sends %-change: -11.66% -7.95%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Fri, 8 Sep 2023 23:17:30 +0000 (16:17 -0700)]
dxil: Set UAV_FENCE_THREAD_GROUP any time global isn't required
With the new nir_opt_barrier_modes() pass, we may encounter control
barriers with no memory modes set, such as:
@barrier () (execution_scope=WORKGROUP, memory_scope=WORKGROUP, mem_semantics=ACQ|REL, mem_modes=0)
The DXIL validator documentation [1] mentions an
INSTR.BARRIERMODENOMEMORY validation rule:
"sync must include some form of memory barrier - _u (UAV) and/or
_g (Thread Group Shared Memory). Only _t (thread group sync) is
optional."
We were generating a dx.op.barrier instruction with only one flag,
DXIL_BARRIER_MODE_SYNC_THREAD_GROUP. This seems to run afoul of the
above validator rule. So, this patch adjusts the code generator to
set DXIL_BARRIER_MODE_UAV_FENCE_THREAD_GROUP too, whenever
UAV_FENCE_GLOBAL isn't required.
[1] https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/DXIL.rst
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Wed, 6 Sep 2023 22:38:58 +0000 (15:38 -0700)]
virgl, nir_to_tgsi: Add a hack for promoting partial memory barriers
Most drivers will want nir_opt_barrier_modes() to optimize out
unnecessary memory barrier modes. However, virgl has to translate
back to GLSL, which means it can really only handle partial memory
barriers in compute shaders today, because there isn't a proper
way to express them otherwise. Just ask nir_to_tgsi to promote
these back to full barriers as a workaround.
See KHR-GL43.shader_storage_buffer_object.advanced-readWrite-case1
on virpipe-on-gl as a case where this hack is needed.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Thu, 31 Aug 2023 22:29:54 +0000 (15:29 -0700)]
lavapipe: Don't delete control barriers
Control barriers still need to do synchronization even if there are no
associated memory barrier modes.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 01:55:13 +0000 (18:55 -0700)]
nir: Reduce the scope of shared memory barriers
Originally written by Ian Romanick for the Intel backend, but ported
to the new nir_opt_barrier_modes() common optimization pass. Ian's
original explanation and commit message follows:
Shared memory only exists within a workgroup, so synchronizing it beyond
workgroup scope is nonsense.
Basically every SPIR-V compiler generates operations like
OpMemoryBarrier(/*Memory*/Device,
/*Semantics*/AcquireRelease | WorkgroupMemory)
This is suggested in numerous places, including
https://github.com/KhronosGroup/GLSL/blob/master/extensions/khr/GL_KHR_vulkan_glsl.txt.
Even Mesa's glsl_to_nir pass does this. This advice, which has been
copy-and-pasted everywhere, is contrary to issue 13 in the original
GL_ARB_compute_shader spec:
"Since shared memory is only accessible to threads within a single
work group, memoryBarrierShared() also only requires synchronization
with other threads in the same work group."
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 01:53:20 +0000 (18:53 -0700)]
nir: Add an optimization pass to reduce barrier modes
Many shaders issue full memory barriers, which may need to synchronize
access to images, SSBOs, shared local memory, or global memory.
However, many of them only use a subset of those memory types - say,
only SSBOs.
Shaders may also have patterns such as:
1. shared local memory access
2. barrier with full variable modes
3. more shared local memory access
4. image access
In this case, the barrier is needed to ensure synchronization between
the various shared memory operations. Image reads and writes do also
exist, but they are all on one side of the barrier, so it is a no-op for
image access. We can drop the image mode from the barrier here too.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Mon, 21 Aug 2023 19:44:20 +0000 (12:44 -0700)]
nir: Fix function parameter indentation in nir_opt_barriers.c
The first parameter should be on the first line, and any subsequent
lines should line up.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Mike Blumenkrantz [Tue, 29 Aug 2023 15:20:27 +0000 (11:20 -0400)]
zink: re-rework i/o variable handling to make having variables entirely optional
old variables are now only used for copying names if possible, which should
make it possible for zink to process shaders which have no variables at all
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Fri, 8 Sep 2023 17:12:26 +0000 (13:12 -0400)]
zink: use right function to get src_type in eliminate_io_wrmasks
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Thu, 7 Sep 2023 16:46:01 +0000 (12:46 -0400)]
zink: add a new linker pass to handle mismatched i/o components
this is the inverted version of rewrite_read_as_0 which tests for mismatched
component i/o on a given location and rewrites the inputs to zero if the
producer shader didn't write to the component
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 15:20:02 +0000 (11:20 -0400)]
zink: create new vars without copying existing ones
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Wed, 30 Aug 2023 15:55:05 +0000 (11:55 -0400)]
zink: use explicit sizing for builtins when creating variables
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 15:14:02 +0000 (11:14 -0400)]
zink: use MAX_PATCH_VERTICES directly for arrayed io var sizing
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 14:54:39 +0000 (10:54 -0400)]
zink: use explicit stride from types instead of copying old_var stride
should be no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 14:54:15 +0000 (10:54 -0400)]
zink: simplify an arrayed io check during variable creation
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:52:40 +0000 (09:52 -0400)]
zink: use nir_io_semantics::num_slots for indirect var creation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:49:58 +0000 (09:49 -0400)]
zink: delete some bindless io lowering code
now that variables are pre-converted this is no longer necessary
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:47:46 +0000 (09:47 -0400)]
zink: fix typing on bindless io lowering
with lowered io this should always be an ivec2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:47:30 +0000 (09:47 -0400)]
zink: reorder bindless io lowering
should be no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:41:36 +0000 (09:41 -0400)]
zink: set is_xfb=false for all i/o variables
this can affect streamout generation, even though it so far hasn't
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Fri, 8 Sep 2023 23:12:13 +0000 (19:12 -0400)]
zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 17:27:32 +0000 (13:27 -0400)]
zink: handle multi-plane implicit sync
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:55:30 +0000 (12:55 -0400)]
zink: handle implicit sync for dmabufs
this adds explicit queue transitions to FOREIGN at the end of the batch
for all written-to dmabufs, then also adds signal/wait semaphores
using the dmabuf fds
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:52:07 +0000 (12:52 -0400)]
zink: hook up cached fd semaphore usage for batch signal/waits
not yet used, matches handling of normal semaphores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:13:33 +0000 (16:13 -0400)]
zink: add a util for getting cached fd semaphores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:09:54 +0000 (16:09 -0400)]
zink: add a screen cache for fd semaphores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:07:02 +0000 (16:07 -0400)]
zink: add another submitinfo for fd semaphore waits
these are semaphores created with VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
and can't be cached with the others
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:05:31 +0000 (16:05 -0400)]
zink: make submitinfo handling easier to manage with enum
this was starting to get hard to read
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:54:39 +0000 (12:54 -0400)]
zink: add a third submitinfo (unused for now)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:53:32 +0000 (12:53 -0400)]
zink: make zink_resource_image_barrier2_init public
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:52:55 +0000 (12:52 -0400)]
zink: use a pointer to simplify submit struct mechanics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Yiwei Zhang [Fri, 8 Sep 2023 18:55:48 +0000 (11:55 -0700)]
venus: expose KHR_external_fence/sempahore_fd extensions
Re-purpose renderer has_external_sync to cover explicit sync emulation
in venus, so that we don't have to add a new flag to distinguish the
emulation path enablement for virtgpu and vtest.
This is to unblock zink implicit sync hanlding against venus for now,
and soon we should migrate to virtgpu fence passing.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25127>
Eric Engestrom [Tue, 11 Jul 2023 19:38:00 +0000 (20:38 +0100)]
ci: drop clover leftover
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24098>
Marek Olšák [Mon, 4 Sep 2023 17:27:09 +0000 (13:27 -0400)]
meson: use llvm-config instead of cmake to fix linking errors with meson 1.2.1
The cmake path picks a random LLVM in /usr, which happens to be 32-bit LLVM,
which fails to link with 64-bit Mesa. This is a meson, cmake, or LLVM bug.
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25042>
Sagar Ghuge [Fri, 4 Aug 2023 21:09:40 +0000 (14:09 -0700)]
anv: Program and emit STATE_COMPUTE_MODE
Don't rely on the HW to set values correctly so just emit
STATE_COMPUTE_MODE with default values set to zero.
Also, this change includes workaround changes:-
-
14015808183 (Parent HSD
14015782607) - Need to emit pipe control
with HDC flush and untyped cache flush set to 1 when CCS has
non-pipelined state update with STATE_COMPUTE_MODE.
-
14014427904 (Parent HSD
22013045878) - We need additional
invalidate/flush when emitting non-pipelined state commands with
multiple CCS enabled.
v2: (Tapani)
- Use lineage HSD numbers for check
- Don't use poisoned WA directly
- Use intel_needs_workaround helper
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>
Sagar Ghuge [Fri, 4 Aug 2023 21:09:22 +0000 (14:09 -0700)]
intel/genxml: Add STATE_COMPUTE_MODE instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>
Sagar Ghuge [Fri, 8 Sep 2023 06:42:31 +0000 (23:42 -0700)]
iris: Enable always flush cache with DEBUG_STALL option
With DEBUG_STALL option, enable always cache flush option for debugging
purpose that aligns with anv.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25108>
Konstantin Seurer [Sat, 2 Sep 2023 20:33:58 +0000 (22:33 +0200)]
radv: Don't use the depth image view for depth bias emission
If the application records a secondary command buffer that inherits
a render pass without specifying a framebuffer, we should still be able
to emit the depth bias state properly.
Fixes: 266b2cf ("radv: implement VK_EXT_depth_bias_control")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9588
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25018>
Tatsuyuki Ishi [Mon, 21 Aug 2023 05:49:29 +0000 (14:49 +0900)]
radv/amdgpu: Use rwlock to protect access to virtual BOs.
Vulkan provides no external synchronization guarantees on sparse memory
objects. Use a per-BO rwlock to prevent reading data mid-update.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24806>
Lionel Landwerlin [Wed, 30 Aug 2023 10:37:33 +0000 (13:37 +0300)]
anv: bound image usages to the associated queue family
When applying barriers for image transitions, we're currently
considering all possible usages of an image. But when running on a
compute only queue for example, the usage of an image will never be
one of those :
- VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
- VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
- VK_IMAGE_USAGE_TRANSIENT_ATTACHMENT_BIT
- VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
- VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
Removing unused usages for the compute queue allows us to reduce the
scope of the VK_IMAGE_LAYOUT_GENERAL for example. This a bunch of
transition operation that are completely useless when dealing with
barriers on the compute queue.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25092>