Arun Ramadoss [Tue, 28 Jun 2022 17:13:29 +0000 (22:43 +0530)]
net: dsa: microchip: move remaining register offset to ksz_chip_reg
This patch moves the broadcast ctrl, multicast ctrl and start control
registers from ksz_chip_dat to ksz_chip_reg.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Arun Ramadoss [Tue, 28 Jun 2022 17:13:28 +0000 (22:43 +0530)]
net: dsa: microchip: add P_STP_CTRL to ksz_chip_reg
This patch moves the stp_ctrl_reg from the ksz_chip_data to ksz_chip_reg
structure.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Arun Ramadoss [Tue, 28 Jun 2022 17:13:27 +0000 (22:43 +0530)]
net: dsa: microchip: change the size of reg from u8 to u16
The register size for the ksz8 switches is u8 and for ksz9477 series is
u16. To have common struct for ksz series switches the size of reg is
increased from u8 to u16.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Arun Ramadoss [Tue, 28 Jun 2022 17:13:26 +0000 (22:43 +0530)]
net: dsa: microchip: remove the struct ksz8
This patch removes the struct ksz8 from ksz8.h which is no longer
needed. The platform bus specific details are now deferenced through
dev->priv.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Arun Ramadoss [Tue, 28 Jun 2022 17:13:25 +0000 (22:43 +0530)]
net: dsa: microchip: move ksz8->shifts to ksz_common
This patch moves ksz8->shifts from ksz8795.c to ksz_common.c. The shifts
are dereferenced using dev->info->shifts.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Arun Ramadoss [Tue, 28 Jun 2022 17:13:24 +0000 (22:43 +0530)]
net: dsa: microchip: move ksz8->masks to ksz_common
This patch moves the ksz8->masks from ksz8795.c to ksz_common.c. The
mask will be dereferenced using dev->info->masks.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Arun Ramadoss [Tue, 28 Jun 2022 17:13:23 +0000 (22:43 +0530)]
net: dsa: microchip: move ksz8->regs to ksz_common
This patch moves the ksz8->regs from ksz8795.c to the ksz_common.c. And
the regs is dereferrenced using dev->info->regs.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Wed, 29 Jun 2022 12:45:31 +0000 (13:45 +0100)]
Merge branch 'mtk-star-emac-features'
Biao Huang says:
====================
net: add more features for mtk-star-emac
Changes in v4:
1. correct the usage of spin_lock/__napi_schedule.
2. fix coding style as Jakub's comments.
Changes in v3:
1. refractor driver as Jakub's comments in patch
"net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs".
2. add acked-by as Rob's comments.
3. add a new patch for halp-duplex support in driver.
Changes in v2:
1. fix coding style as Bartosz's comments.
2. add reviewed-by as Bartosz's comments.
This series add more features for mtk-star-emac:
1. add reference clock pad selection for RMII;
2. add simple timing adjustment for RMII;
3. add support for MII;
4. add support for new IC MT8365;
5. separate tx/rx interrupt handling.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:43 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: enable half duplex hardware support
Current driver doesn't support half duplex correctly.
This patch enable half duplex capability in hardware.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:42 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs
Current driver may lost tx interrupts under bidirectional test with iperf3,
which leads to some unexpected issues.
This patch let rx/tx interrupt enable/disable separately, and rx/tx are
handled in different NAPIs.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:41 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: add support for MII interface
Add support for MII interface.
If user wants to use MII, assign "MII" to "phy-mode" property in dts.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:40 +0000 (11:17 +0800)]
dt-bindings: net: mtk-star-emac: add description for new properties
Add description for new properties which will be parsed in driver.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:39 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: add timing adjustment support
Add simple clock inversion for timing adjustment in driver.
Add property "mediatek,txc-inverse" or "mediatek,rxc-inverse" to
device node when necessary.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:38 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: add clock pad selection for RMII
This patch add a new dts property named "mediatek,rmii-rxc" parsing
in driver, which will configure MAC to select which pin the RMII reference
clock is connected to, TXC or RXC.
TXC pad is the default reference clock pin. If user wants to use RXC pad
instead, add "mediatek,rmii-rxc" to corresponding device node.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:37 +0000 (11:17 +0800)]
dt-bindings: net: mtk-star-emac: add support for MT8365
Add binding document for Ethernet on MT8365.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:36 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: add support for MT8365 SoC
Add Ethernet driver support for MT8365 SoC.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:35 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: modify IRQ trigger flags
If the flags in request_irq() is IRQF_TRIGGER_NONE, the trigger method
is determined by "interrupt" property in dts.
So, modify the flag from IRQF_TRIGGER_FALLING to IRQF_TRIGGER_NONE.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Yinghua Pan <ot_yinghua.pan@mediatek.com>
Reviewed-by: Bartosz Golaszewski <brgl@bgdev.pl>
Signed-off-by: David S. Miller <davem@davemloft.net>
Biao Huang [Wed, 29 Jun 2022 03:17:34 +0000 (11:17 +0800)]
net: ethernet: mtk-star-emac: store bit_clk_div in compat structure
Not all the SoC are using the same clock divider. Move the divider into
a compat structure specific to the SoCs.
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Wed, 29 Jun 2022 12:40:47 +0000 (13:40 +0100)]
Merge branch 'sfc-add-extra-states-for-VDPA'
Martin Habets says:
====================
sfc: Add extra states for VDPA
For EF100 VDPA support we need to enhance the sfc driver's load and
unload functionality so that it can probe and then unregister its
network device, so that VDPA can use services such as MCDI to initialise
VDPA resources.
v2:
- Fix checkpatch errors.
- Correct signoffs.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 14:00:47 +0000 (15:00 +0100)]
sfc: Separate netdev probe/remove from PCI probe/remove
The netdev probe will be used when moving from vDPA to EF100 BAR config.
The netdev remove will be used when moving from EF100 to vDPA BAR config.
In the process, change several log messages to pci_ instead of netif_
to remove the "(unregistered net_device)" text.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 14:00:34 +0000 (15:00 +0100)]
sfc: replace function name in string with __func__
Minor fix to existing code to make later patch checkpatch clean.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Acked-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 14:00:22 +0000 (15:00 +0100)]
sfc: Unsplit literal string.
Minor fix to existing code to later patch checkpatch clean.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Acked-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 14:00:10 +0000 (15:00 +0100)]
sfc: Move EF100 efx_nic_type structs to the end of the file
This avoids a forward declaration in a subsequent patch.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 13:59:57 +0000 (14:59 +0100)]
sfc: Separate efx_nic memory from net_device memory
As we have a lot of common code this applies to all NIC architectures.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 13:59:45 +0000 (14:59 +0100)]
sfc: Encapsulate access to netdev_priv()
Once we separate struct efx_nic memory from net_device memory the
existing usage will have to change.
Apart from the new function efx_netdev_priv() accesses have been
changed using:
sed -i 's/netdev_priv/efx_netdev_priv/'
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 13:59:32 +0000 (14:59 +0100)]
sfc: Change BUG_ON to WARN_ON and recovery code.
Pre-emptively fix a checkpatch warning in a subsequent patch.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 13:59:20 +0000 (14:59 +0100)]
sfc: Remove netdev init from efx_init_struct
Move functionality involving the struct net_device out of
efx_init_struct so that we can initialise without a net dev
for VDPA operation.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 13:59:08 +0000 (14:59 +0100)]
sfc: Add a PROBED state for EF100 VDPA use.
For VDPA we need to tear down the driver to the point where it
has various control channels like MCDI, but it no longer has
a network device. This adds a state corresponding to
that mode that will be used when VDPA support is added.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Co-developed-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jonathan Cooper [Tue, 28 Jun 2022 13:58:55 +0000 (14:58 +0100)]
sfc: Split STATE_READY in to STATE_NET_DOWN and STATE_NET_UP.
This patch splits the READY state in to NET_UP and NET_DOWN. This
is to prepare for future work to delay resource allocation until
interface up so that we can use resources more efficiently in
SRIOV environments, and also to lay the ground work for an extra
PROBED state where we don't create a network interface,
for VDPA operation.
Signed-off-by: Jonathan Cooper <jonathan.s.cooper@amd.com>
Acked-by: Martin Habets <habetsm.xilinx@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Wed, 29 Jun 2022 12:35:47 +0000 (13:35 +0100)]
Merge branch 'mlxsw-unified-bridge-conversion-part-5'
Ido Schimmel says:
====================
mlxsw: Unified bridge conversion - part 5/6
This is the fifth part of the conversion of mlxsw to the unified bridge
model.
The previous part that was merged in commit
d521bc0a0f7c ("Merge branch
'mlxsw-unified-bridge-conversion-part-4-6'") converted the flooding code
to use the new APIs of the unified bridge model. As part of this
conversion, the flooding code started accessing the port group table
(PGT) directly in order to allocate MID indexes and configure the ports
via which a packet needs to be replicated.
MDB entries in the device also make use of the PGT table, but the
related code has its own PGT allocator and does not make use of the
common core that was added in the previous patchset. This patchset
converts the MDB code to use the common PGT code.
The first nine patches prepare the MDB code for the conversion that is
performed by the last patch.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:07 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Convert MDB code to use PGT APIs
The previous patches added common APIs for maintaining PGT (Port Group
Table) table. In the legacy model, software did not interact with this
table directly. Instead, it was accessed by firmware in response to
registers such as SFTR and SMID. In the new model, software has full
control over the PGT table using the SMID register.
The configuration of MDB entries is already done via SMID, so the new
PGT APIs can be used also using the legacy model, the only difference is
that MID index should be aligned to bridge model. See a previous patch
which added API for that.
The main changes are:
- MDB code does not maintain bitmap of ports in MDB entry anymore, instead,
it stores a list of ports with additional information.
- MDB code does not configure SMID register directly anymore, it will be
done via PGT API when port is first added or removed.
- Today MDB code does not update SMID when port is added/removed while
multicast is disabled. Instead, it maintains bitmap of ports and once
multicast is enabled, it rewrite the entry to hardware. Using PGT APIs,
the entry will be updated also when multicast is disabled, but the
mapping between {MAC, FID}->{MID} will not appear in SFD register. It
means that SMID will be updated all the time and disable/enable multicast
will impact only SFD configuration.
- For multicast router, today only SMID is updated and the bitmap is not
updated. Using the new list of ports, there is a reference count for each
port, so it can be saved in software also. For such port,
'struct mlxsw_sp_mdb_entry.ports_count' will not be updated and the
port in the list will be marked as 'mrouter'.
- Finally, `struct mlxsw_sp_mid.in_hw` is not needed anymore.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:06 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Flush port from MDB entries according to FID index
Currently, flushing port from all MDB entries is done when the last VLAN
is removed. This behavior is inaccurate, as port can be removed while there
is another port which uses the same VLAN, in such case, this is not the
last port which uses this VLAN and removed, but this port is supposed to be
removed from the MDB entries.
Flush the port from MDB when it is removed, regardless the state of other
ports. Flush only the MDB entries which are relevant for the same FID
index.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:05 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Add support for getting and putting MDB entry
A previous patch added support for init() and fini() for MDB entries. MDB
entry can be updated, ports can be added and removed from the entry. Add
get() and put() functions, the first one checks if the entry already exists
and otherwise initializes the entry. The second removes the entry just in
case that there are no more ports in this entry.
Use the list of the ports which was added in a previous patch. When the
list contains only one port which is not multicast router, and this port
is removed, the MDB entry can be removed. Use
'struct mlxsw_sp_mdb_entry.ports_count' to know how many ports use the
entry, regardless the use of multicast router ports.
When mlxsw_sp_mc_mdb_entry_put() is called with specific port which
supposed to be removed, check if the removal will cause a deletion of
the entry. If this is the case, call mlxsw_sp_mc_mdb_entry_fini() which
first deletes the MDB entry and then releases the PGT entry, to avoid a
temporary situation in which the MDB entry points to an empty PGT entry,
as otherwise packets will be temporarily dropped instead of being flooded.
The new functions will be used in the next patches.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:04 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Implement mlxsw_sp_mc_mdb_entry_{init, fini}()
The next patches will convert MDB code to use PGT APIs. The change will
move the responsibility of allocating MID indexes and writing PGT
configurations to hardware to PGT code. As part of this change, most of the
MDB code will be changed and improved.
As a preparation for the above mentioned change, implement
mlxsw_sp_mc_mdb_entry_{init, fini}(). Currently, there is a function
__mlxsw_sp_mc_alloc(), which does not only allocate MID. In addition,
there is no an equivalent function to free the MID. When
mlxsw_sp_port_remove_from_mid() removes the last port, it handles MID
removal. Instead, add init() and fini() functions, which use PGT APIs.
The differences between the existing and the new functions are as follows:
1. Today MDB code does not update SMID when port is added/removed while
multicast is disabled. It maintains a bitmap of ports and once multicast
is enabled, it writes the entry to hardware. Instead, using PGT APIs,
the entry will be updated also when multicast is disabled, but the
mapping between {MAC, FID}->{MID} (is configured using SFD) will be
updated according to multicast state. It means that SMID will be updated
all the time and disable/enable multicast will impact only SFD
configuration.
2. Today the allocation of MID index is done as part of
mlxsw_sp_mc_write_mdb_entry(). The fact that the entry will be
written in hardware all the time, moves the allocation of the index to
be as part of the MDB entry initialization. PGT API is used for the
allocation.
3. Today the update of multicast router ports is done as part of
mlxsw_sp_mc_write_mdb_entry(). Instead, add functions to add/remove
all multicast router ports when entry is first added or removed. When
new multicast router port will be added/removed, the dedicated API will
be used to add/remove it from the existing entries.
4. A list of ports will be stored per MDB entry instead of the exiting
bitmap. The list will contain the multicast router ports and maintain
reference counter per port.
Add mlxsw_sp_mdb_entry_write() which is almost identical to
mlxsw_sp_port_mdb_op(). Use more clear name and align the MID index to
bridge model using PGT API. The existing function will be removed in the
next patches.
Note that PGT APIs configure the firmware using SMID register, like the
driver already does today for MDB entries, so PGT APIs can be used also
using legacy bridge model.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:03 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Add support for maintaining list of ports per MDB entry
As part of converting MDB code to use PGT APIs, PGT code stores which ports
are mapped to each PGT entry. PGT code is not aware of the type of the port
(multicast router or not), as it is not relevant there.
To be able to release an MDB entry when the there are no ports which are
not multicast routers, the entry should be aware of the state of its
ports. Add support for maintaining list of ports per MDB entry.
Each port will hold a reference count as multiple MDB entries can use the
same hardware MDB entry. It occurs because MDB entries in the Linux bridge
are keyed according to their multicast IP, when these entries are notified
to device drivers via switchdev, the multicast IP is converted to a
multicast MAC. This conversion might cause collisions, for example,
ff0e::1 and ff0e:1234::1 are both mapped to the multicast MAC
33:33:00:00:00:01.
Multicast router port will take a reference once, and will be marked as
'mrouter', then when port in the list is multicast router and its
reference value is one, it means that the entry can be removed in case
that there are no other ports which are not multicast routers. For that,
maintain a counter per MDB entry to count ports in the list, which were
added to the multicast group, and not because they are multicast routers.
When this counter is zero, the entry can be removed.
Add mlxsw_sp_mdb_entry_port_{get,put}() for regular ports and
mlxsw_sp_mdb_entry_mrouter_port_{get,put}() for multicast router ports.
Call PGT API to add or remove port from PGT entry when port is first added
or removed, according to the reference counting.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:02 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Add support for maintaining hash table of MDB entries
Currently MDB entries are stored in a list as part of
'struct mlxsw_sp_bridge_device'. Storing them in a hash table in
addition to the list will allow finding a specific entry more efficiently.
Add support for the required hash table, the next patches will insert
and remove MDB entries from the table. The existing code which adds and
removes entries will be removed and replaced by new code in the next
patches, so there is no point to adjust the existing code.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:01 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Save MAC and FID as a key in 'struct mlxsw_sp_mdb_entry'
The next patch will add support for storing all the MDB entries in a hash
table. As a preparation, save the MAC address and the FID in a
separate structure. This structure will be used later as a key for the
hash table.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:40:00 +0000 (12:40 +0300)]
mlxsw: spectrum_switchdev: Rename MIDs list
Currently, the list which stores the MDB entries for a given bridge
instance is called 'mids_list'.
This name is not accurate as a MID entry stores a bitmap of ports to
which a packet needs to be replicated and a MDB entry stores the mapping
from {MAC, FID} to PGT index (MID)
Rename it to 'mdb_list'.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:39:59 +0000 (12:39 +0300)]
mlxsw: spectrum_switchdev: Rename MID structure
Currently the structure which represents MDB entry is called
'struct mlxsw_sp_mid'. This name is not accurate as a MID entry stores a
bitmap of ports to which a packet needs to be replicated and a MDB entry
stores the mapping from {MAC, FID} to PGT index (MID).
Rename the structure to 'struct mlxsw_sp_mdb_entry'. The structure
'mlxsw_sp_mid' is defined as part of spectrum.h. The only file which
uses it is spectrum_switchdev.c, so there is no reason to expose it to
other files. Move the definition to spectrum_switchdev.c.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Amit Cohen [Wed, 29 Jun 2022 09:39:58 +0000 (12:39 +0300)]
mlxsw: Align PGT index to legacy bridge model
FID code reserves about 15K entries in PGT table for flooding. These
entries are just allocated and are not used yet because the code that uses
them is skipped now.
The next patches will convert MDB code to use PGT APIs. The allocation of
indexes for multicast is done after FID code reserves 15K entries.
Currently, legacy bridge model is used and firmware manages PGT table. That
means that the indexes which are allocated using PGT API are too high when
legacy bridge model is used. To not exceed firmware limitation for MDB
entries, add an API that returns the correct 'mid_index', based on bridge
model. For legacy model, subtract the number of flood entries from PGT
index. Use it to write the correct MID to SMID register. This API will be
used also from MDB code in the next patches.
PGT should not be aware of MDB and FID different usage, this API is
temporary and will be removed once unified bridge model will be used.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Menglong Dong [Mon, 27 Jun 2022 12:16:25 +0000 (20:16 +0800)]
net: mptcp: fix some spelling mistake in mptcp
codespell finds some spelling mistake in mptcp:
net/mptcp/subflow.c:1624: interaces ==> interfaces
net/mptcp/pm_netlink.c:1130: regarless ==> regardless
Just fix them.
Signed-off-by: Menglong Dong <imagedong@tencent.com>
Reviewed-by: Matthieu Baerts <matthieu.baerts@tessares.net>
Link: https://lore.kernel.org/r/20220627121626.1595732-1-imagedong@tencent.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Jakub Kicinski [Mon, 27 Jun 2022 17:39:00 +0000 (10:39 -0700)]
Revert the ARM/dts changes for Renesas RZ/N1
Based on a request from Geert:
Revert "ARM: dts: r9a06g032-rzn1d400-db: add switch description"
This reverts commit
9aab31d66ec97d7047e42feacc356bc9c21a5bf5.
Revert "ARM: dts: r9a06g032: describe switch"
This reverts commit
cf9695d8a7e927f7563ce6ea0a4e54b8214a12f1.
Revert "ARM: dts: r9a06g032: describe GMAC2"
This reverts commit
3f5261f1c2a8d7b178f9f65c6dda92523329486e.
Revert "ARM: dts: r9a06g032: describe MII converter"
This reverts commit
066c3bd358355185d9313358281fe03113c0a9ad.
to let these changes flow thru the platform and SoC trees.
Link: https://lore.kernel.org/r/CAMuHMdUvSLFU56gsp1a9isOiP9otdCJ2-BqhbrffcoHuA6JNig@mail.gmail.com/
Link: https://lore.kernel.org/r/20220627173900.3136386-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Jakub Kicinski [Wed, 29 Jun 2022 04:30:11 +0000 (21:30 -0700)]
Merge branch 'net-phylink-cleanup-pcs-code'
Russell King says:
====================
net: phylink: cleanup pcs code
These two patches were part of the larger series for the mv88e6xxx
phylink pcs conversion. As this is delayed, I've decided to send these
two patches now.
====================
Link: https://lore.kernel.org/r/YrmYEC2N9mVpg9g6@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Russell King (Oracle) [Mon, 27 Jun 2022 11:44:43 +0000 (12:44 +0100)]
net: phylink: disable PCS polling over major configuration
While we are performing a major configuration, there is no point having
the PCS polling timer running. Stop it before we begin preparing for
the configuration change, and restart it only once we've successfully
completed the change.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Russell King (Oracle) [Mon, 27 Jun 2022 11:44:38 +0000 (12:44 +0100)]
net: phylink: remove pcs_ops member
Remove the pcs_ops member from struct phylink, using the one stored in
struct phylink_pcs instead.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Eric Dumazet [Mon, 27 Jun 2022 12:10:38 +0000 (12:10 +0000)]
tcp: diag: add support for TIME_WAIT sockets to tcp_abort()
Currently, "ss -K -ta ..." does not support TIME_WAIT sockets.
Issue has been raised at least two times in the past [1] [2]
it is time to fix it.
[1] https://lore.kernel.org/netdev/
ba65f579-4e69-ae0d-4770-
bc6234beb428@gmail.com/
[2] https://lore.kernel.org/netdev/CANn89i+R9RgmD=AQ4vX1Vb_SQAj4c3fi7-ZtQz-inYY4Sq4CMQ@mail.gmail.com/T/
While we are at it, use inet_sk_state_load() while tcp_abort()
does not hold a lock on the socket.
Signed-off-by: Eric Dumazet <edumazet@google.com>
Tested-by: Muhammad Usama Anjum <usama.anjum@collabora.com>
Link: https://lore.kernel.org/r/20220627121038.226500-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Dimitris Michailidis [Mon, 27 Jun 2022 18:20:00 +0000 (11:20 -0700)]
net/funeth: Support for ethtool -m
Add the FW command for reading port module memory pages and implement
ethtool's get_module_eeprom_by_page operation.
Signed-off-by: Dimitris Michailidis <dmichail@fungible.com>
Link: https://lore.kernel.org/r/20220627182000.8198-1-dmichail@fungible.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Kuniyuki Iwashima [Mon, 27 Jun 2022 23:36:27 +0000 (16:36 -0700)]
af_unix: Do not call kmemdup() for init_net's sysctl table.
While setting up init_net's sysctl table, we need not duplicate the
global table and can use it directly as ipv4_sysctl_init_net() does.
Unlike IPv4, AF_UNIX does not have a huge sysctl table for now, so it
cannot be a problem, but this patch makes code consistent.
Acked-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Kuniyuki Iwashima <kuniyu@amazon.com>
Link: https://lore.kernel.org/r/20220627233627.51646-1-kuniyu@amazon.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Paolo Abeni [Tue, 28 Jun 2022 12:31:43 +0000 (14:31 +0200)]
Merge branch 'mlxsw-unified-bridge-conversion-part-4-6'
Ido Schimmel says:
====================
mlxsw: Unified bridge conversion - part 4/6
This is the fourth part of the conversion of mlxsw to the unified bridge
model.
Unlike previous parts that prepared mlxsw for the conversion, this part
actually starts the conversion. It focuses on flooding configuration and
converts mlxsw to the more "raw" APIs of the unified bridge model.
The patches configure the different stages of the flooding pipeline in
Spectrum that looks as follows (at a high-level):
+------------+ +----------+ +-------+
{FID, | | {Packet type, | | | | MID
DMAC} | FDB lookup | Bridge type} | SFGC | MID base | | Index
+--------> (miss) +----------------> register +-----------> Adder +------->
| | | | | |
| | | | | |
+------------+ +----+-----+ +---^---+
| |
Table | |
type | | Offset
| +-------+ |
| | | |
| | | |
+----->+ Mux +------+
| |
| |
+-^---^-+
| |
FID| |FID
| |offset
+ +
The multicast identifier (MID) index is used as an index to the port
group table (PGT) that contains a bitmap of ports via which a packet
needs to be replicated.
From the PGT table, the packet continues to the multicast port egress
(MPE) table that determines the packet's egress VLAN. This is a
two-dimensional table that is indexed by port and switch multicast port
to egress (SMPE) index. The latter can be thought of as a FID. Without
it, all the packets replicated via a certain port would get the same
VLAN, regardless of the bridge domain (FID).
Logically, these two steps look as follows:
PGT table MPE table
+-----------------------+ +---------------+
| | {Local port, | | Egress
MID index | Local ports bitmap #1 | SMPE index} | | VID
+------------> ... +---------------> +-------->
| Local ports bitmap #N | | |
| | SMPE | |
+-----------------------+ +---------------+
Local port
Patchset overview:
Patch #1 adds a variable to guard against mixed model configuration.
Will be removed in part 6 when mlxsw is fully converted to the unified
model.
Patches #2-#5 introduce two new FID attributes required for flooding
configuration in the new model:
1. 'flood_rsp': Instructs the firmware to handle flooding configuration
for this FID. Only set for router FIDs (rFIDs) which are used to connect
a {Port, VLAN} to the router block.
2. 'bridge_type': Allows the device to determine the flood table (i.e.,
base index to the PGT table) for the FID. The first type will be used
for FIDs in a VLAN-aware bridge and the second for FIDs representing
VLAN-unaware bridges.
Patch #6 configures the MPE table that determines the egress VLAN of a
packet that is forwarded according to L2 multicast / flood.
Patches #7-#11 add the PGT table and related APIs to allocate entries
and set / clear ports in them.
Patches #12-#13 convert the flooding configuration to use the new PGT
APIs.
====================
Link: https://lore.kernel.org/r/20220627070621.648499-1-idosch@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:21 +0000 (10:06 +0300)]
mlxsw: spectrum_fid: Configure flooding entries using PGT APIs
The PGT (Port Group Table) table maps an index to a bitmap of local ports
to which a packet needs to be replicated. This table is used for layer 2
multicast and flooding.
In the legacy model, software did not interact with PGT table directly.
Instead, it was accessed by firmware in response to registers such as SFTR
and SMID. In the new model, the SFTR register is deprecated and software
has full control over the PGT table using the SMID register.
Use the new PGT APIs to allocate entries for flooding as part of flood
tables initialization. Add mlxsw_sp_fid_flood_tables_fini() to free the
allocated indexes. In addition, use PGT APIs to add/remove ports from PGT
table. The existing code which configures the flood entries via SFTR2 will
be removed later.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:20 +0000 (10:06 +0300)]
mlxsw: spectrum_fid: Set 'mid_base' as part of flood tables initialization
The PGT (Port Group Table) table maps an index to a bitmap of local ports
to which a packet needs to be replicated. This table is used for layer 2
multicast and flooding.
The index to PGT table which is called 'mid_index', is a result of
'mid_base' + 'fid_offset'. Using the legacy bridge model, firmware
configures 'mid_base'. However, using the new model, software is
responsible to configure it via SFGC register. The first 15K entries will
be used for flooding and the rest for multicast. The table will look as
follows:
+----------------------------+
| |
| 802.1q, unicast flooding | 4K entries
| |
+----------------------------+
| |
| 802.1q, multicast flooding | 4K entries
| |
+----------------------------+
| |
| 802.1q, broadcast flooding | 4K entries
| |
+----------------------------+
| 802.1d, unicast flooding | 1K entries
+----------------------------+
| 802.1d, multicast flooding | 1K entries
+----------------------------+
| 802.1d, broadcast flooding | 1K entries
+----------------------------+
| |
| |
| Multicast entries | The rest of the table
| |
| |
+----------------------------+
Add 'pgt_base' to 'struct mlxsw_sp_fid_family' and use it to calculate
MID base, set 'SFGC.mid_base' as part of flood tables initialization.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:19 +0000 (10:06 +0300)]
mlxsw: spectrum: Initialize PGT table
Initialize PGT table as part of mlxsw_sp_init(). This table will be used
first in the next patch by FID code to set flooding entries, and later by
MDB code to add multicast entries.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:18 +0000 (10:06 +0300)]
mlxsw: Extend PGT APIs to support maintaining list of ports per entry
Add an API to associate a PGT entry with SMPE index and add or remove a
port. This API will be used by FID code and MDB code, to add/remove port
from specific PGT entry.
When the first port is added to PGT entry, allocate the entry in the given
MID index, when the last port is removed from PGT entry, free it.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:17 +0000 (10:06 +0300)]
mlxsw: Add a dedicated structure for bitmap of ports
Currently when bitmap of ports is needed, 'unsigned long *' type is
used. The functions which use the bitmap assume its length according to
its name, i.e., each function which gets a bitmap of ports queries the
maximum number of ports and uses it as the size.
As preparation for the next patch which will use bitmap of ports, add a
dedicated structure for it. Refactor the existing code to use the new
structure.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:16 +0000 (10:06 +0300)]
mlxsw: Add an indication of SMPE index validity for PGT table
In Spectrum-1, the index into the MPE table - called switch multicast to
port egress VID (SMPE) - is derived from the PGT entry, whereas in
Spectrum-2 and later ASICs it is derived from the FID.
Therefore, in Spectrum-1, the SMPE index needs to be programmed as part of
the PGT entry via SMID register, while it is reserved for Spectrum-2 and
later ASICs.
Add 'pgt_smpe_index_valid' boolean as part of 'struct mlxsw_sp' and set
it to true for Spectrum-1 and to false for the later ASICs. Add
'smpe_index_valid' as part of 'struct mlxsw_sp_pgt' and set it according
to the value in 'struct mlxsw_sp' as part of PGT initialization.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:15 +0000 (10:06 +0300)]
mlxsw: Add an initial PGT table support
The PGT (Port Group Table) table maps an index to a bitmap of local ports
to which a packet needs to be replicated. This table is used for layer 2
multicast and flooding.
In the legacy model, software did not interact with this table directly.
Instead, it was accessed by firmware in response to registers such as
SFTR and SMID. In the new model, the SFTR register is deprecated and
software has full control over the PGT table using the SMID register.
The entire state of the PGT table needs to be maintained in software
because member ports in a PGT entry needs to be reference counted to avoid
releasing entries which are still in use.
Add the following APIs:
1. mlxsw_sp_pgt_{init, fini}() - allocate/free the PGT table.
2. mlxsw_sp_pgt_mid_alloc_range() - allocate a range of MID indexes in PGT.
To be used by FID code during initialization to reserve specific PGT
indexes for flooding entries.
3. mlxsw_sp_pgt_mid_free_range() - free indexes in a given range.
4. mlxsw_sp_pgt_mid_alloc() - allocate one MID index in the PGT at a
non-specific range, just search for free index. To be used by MDB code.
5. mlxsw_sp_pgt_mid_free() - free the given index.
Note that alloc() functions do not allocate the entries in software, just
allocate IDs using 'idr'.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:14 +0000 (10:06 +0300)]
mlxsw: spectrum_fid: Configure egress VID classification for multicast
The device includes two main tables to support layer 2 multicast (i.e.,
MDB and flooding). These are the PGT (Port Group Table) table and the MPE
(Multicast Port Egress) table.
- PGT is {MID -> (bitmap of local_port, SPME index)}
- MPE is {(Local port, SMPE index) -> eVID}
In the legacy model, software did not interact with MPE table as it was
completely hidden in firmware. In the new model, software needs to
populate the table itself in order to map from {Local port, SMPE} to an
egress VID. This is done using the SMPE register.
Configure SMPE register when a {Local port, VID} are mapped/unmapped to a
802.1d and 802.1q emulated FIDs. The MPE table is not relevant for rFIDs as
firmware handles their flooding.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:13 +0000 (10:06 +0300)]
mlxsw: Set flood bridge type for FIDs
In the unified bridge model, the bridge type FID attribute is no longer
configured by the firmware, but instead by software when creating and
editing a FID via SFMR register.
Set this field as part of FID creation and edition flow. Default to 0
(reserved) as long as the driver operates in the legacy bridge model.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:12 +0000 (10:06 +0300)]
mlxsw: spectrum_fid: Store 'bridge_type' as part of FID family
Currently, 'bridge_type' is an attribute of 'struct mlxsw_sp_flood_table',
which is defined per FID family. Instead, it can be an attribute of
'struct mlxsw_sp_fid_family' as all flood tables in the same family are of
the same type. This change will ease the configuration of
'SFMR.flood_bridge_type' which will be added in the next patch.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:11 +0000 (10:06 +0300)]
mlxsw: Prepare 'bridge_type' field for SFMR usage
Under the legacy bridge model, the field 'bridge_type' is used only
in SFGC register, to determine the type of flood table (FID/FID offset).
Under the unified bridge model, it will be used also in SFMR register.
When a BUM packet needs to be flooded, SFGC is used to provide the
'mid_base' for PGT table. The access to SFGC is by
{packet type, bridge type}. Under the unified bridge model, software is
responsible for configuring 'bridge_type' as part of SFMR.
As preparation for the new required configuration, rename
'enum mlxsw_reg_sfgc_bridge_type' to 'enum mlxsw_reg_bridge_type'. Then
it can be used also in SFMR. In addition, align the names of the values to
internal documentation.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:10 +0000 (10:06 +0300)]
mlxsw: spectrum_fid: Configure flooding table type for rFID
Using unified bridge model, RITR register no longer configures the rFID
used for sub-port RIFs. It needs to be created by software via SFMR. Such
FIDs need to be created with a special flood indication using
'SFMR.flood_rsp=1'. It means that for such FIDs, router sub-port flooding
table will be used, this table is configured by firmware.
Set the above mentioned field as part of FID initialization and FID
edition, so then when other fields will be updated in SFMR, this field
will store the correct value and will not be overwritten.
Add 'flood_rsp' variable to 'struct mlxsw_sp_fid_family', set it to true
for rFID and to false for the rest.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Amit Cohen [Mon, 27 Jun 2022 07:06:09 +0000 (10:06 +0300)]
mlxsw: spectrum: Add a temporary variable to indicate bridge model
As part of transition to unified bridge model, many different firmware
configurations are done.
Some of the configuration that needs to be done for the unified bridge
model is not valid under the legacy model, and would be rejected by the
firmware. At the same time, the driver cannot switch to the unified bridge
model until all of the code has been converted.
To allow breaking the change into patches, and to not break driver
behavior during the transition, add a boolean variable to indicate bridge
model. Then, forbidden configurations will be skipped using the check -
"if (!mlxsw_sp->ubridge)".
The new variable is temporary for several sets, it will be removed when
firmware will be configured to work with unified bridge model.
Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Sam Edwards [Thu, 23 Jun 2022 18:11:04 +0000 (12:11 -0600)]
ipv6/addrconf: fix timing bug in tempaddr regen
The addrconf_verify_rtnl() function uses a big if/elseif/elseif/... block
to categorize each address by what type of attention it needs. An
about-to-expire (RFC 4941) temporary address is one such category, but the
previous elseif branch catches addresses that have already run out their
prefered_lft. This means that if addrconf_verify_rtnl() fails to run in
the necessary time window (i.e. REGEN_ADVANCE time units before the end of
the prefered_lft), the temporary address will never be regenerated, and no
temporary addresses will be available until each one's valid_lft runs out
and manage_tempaddrs() begins anew.
Fix this by moving the entire temporary address regeneration case out of
that block. That block is supposed to implement the "destructive" part of
an address's lifecycle, and regenerating a fresh temporary address is not,
semantically speaking, actually tied to any particular lifecycle stage.
The age test is also changed from `age >= prefered_lft - regen_advance`
to `age + regen_advance >= prefered_lft` instead, to ensure no underflow
occurs if the system administrator increases the regen_advance to a value
greater than the already-set prefered_lft.
Note that this does not fix the problem of addrconf_verify_rtnl() sometimes
not running in time, resulting in the race condition described in RFC 4941
section 3.4 - it only ensures that the address is regenerated. Fixing THAT
problem may require either using jiffies instead of seconds for all time
arithmetic here, or always rounding up when regen_advance is converted to
seconds.
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Link: https://lore.kernel.org/r/20220623181103.7033-1-CFSworks@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Christophe JAILLET [Sun, 26 Jun 2022 16:27:45 +0000 (18:27 +0200)]
hinic: Use the bitmap API when applicable
'vlan_bitmap' is a bitmap and is used as such. So allocate it with
devm_bitmap_zalloc() and its explicit bit size (i.e. VLAN_N_VID).
This avoids the need of the VLAN_BITMAP_SIZE macro which:
- needlessly has a 'nic_dev' parameter
- should be "long" (and not byte) aligned, so that the bitmap semantic
is respected
This is in fact not an issue because VLAN_N_VID is 4096 at the time
being, but devm_bitmap_zalloc() is less verbose and easier to understand.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/6ff7b7d21414240794a77dc2456914412718a145.1656260842.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Jakub Kicinski [Tue, 28 Jun 2022 05:07:11 +0000 (22:07 -0700)]
Merge branch 'nfp-add-vepa-and-adapter-selftest-support'
Simon Horman says:
====================
nfp: add VEPA and adapter selftest support
1. Support for ethtool -t: adapter selftest
2. VEPA mode in HW bridge.
This supplements existing support for VEB mode.
====================
Link: https://lore.kernel.org/r/20220624073816.1272984-1-simon.horman@corigine.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Fei Qin [Fri, 24 Jun 2022 07:38:16 +0000 (09:38 +0200)]
nfp: add support for 'ethtool -t DEVNAME' command
Add support for ethtool selftest.
e.g.
# ethtool -t DEVNAME
test result like:
The test result is PASS
The test extra info:
Link Test 0
NSP Test 0
Firmware Test 0
Register Test 0
Signed-off-by: Fei Qin <fei.qin@corigine.com>
Reviewed-by: Louis Peens <louis.peens@corigine.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Yinjun Zhang [Fri, 24 Jun 2022 07:38:15 +0000 (09:38 +0200)]
nfp: support vepa mode in HW bridge
Add support for VEPA mode of HW bridge.
The default remains VEB mode.
The mode may be configured using ndo_bridge_setlink,
and inspected using ndo_bridge_getlink.
Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com>
Reviewed-by: Louis Peens <louis.peens@corigine.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Jilin Yuan [Sat, 25 Jun 2022 07:15:58 +0000 (15:15 +0800)]
net: atlantic:fix repeated words in comments
Delete the redundant word 'the'.
Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
Link: https://lore.kernel.org/r/20220625071558.3852-1-yuanjilin@cdjrlc.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Jilin Yuan [Sat, 25 Jun 2022 07:06:33 +0000 (15:06 +0800)]
amd/xgbe: fix repeated words in comments
Delete the redundant word 'use'.
Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
Link: https://lore.kernel.org/r/20220625070633.64982-1-yuanjilin@cdjrlc.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Jilin Yuan [Sat, 25 Jun 2022 06:57:45 +0000 (14:57 +0800)]
agere: fix repeated words in comments
Delete the redundant word 'the'.
Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
Link: https://lore.kernel.org/r/20220625065745.61464-1-yuanjilin@cdjrlc.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Deming Wang [Fri, 24 Jun 2022 01:31:14 +0000 (21:31 -0400)]
net: axienet: Modify function description
Delete duplicate words of "the".
Signed-off-by: Deming Wang <wangdeming@inspur.com>
Link: https://lore.kernel.org/r/20220624013114.1913-1-wangdeming@inspur.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Eric Dumazet [Sat, 25 Jun 2022 06:47:22 +0000 (06:47 +0000)]
ipmr: fix a lockdep splat in ipmr_rtm_dumplink()
vif_dev_read() should be used from RCU protected sections only.
ipmr_rtm_dumplink() is holding RTNL, so the data structures
can not be changed.
syzbot reported:
net/ipv4/ipmr.c:84 suspicious rcu_dereference_check() usage!
other info that might help us debug this:
rcu_scheduler_active = 2, debug_locks = 1
1 lock held by syz-executor.4/3068:
stack backtrace:
CPU: 1 PID: 3068 Comm: syz-executor.4 Not tainted 5.19.0-rc3-syzkaller-00565-g5d04b0b634bb #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
Call Trace:
<TASK>
__dump_stack lib/dump_stack.c:88 [inline]
dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106
vif_dev_read net/ipv4/ipmr.c:84 [inline]
vif_dev_read net/ipv4/ipmr.c:82 [inline]
ipmr_fill_vif net/ipv4/ipmr.c:2756 [inline]
ipmr_rtm_dumplink+0x1343/0x18c0 net/ipv4/ipmr.c:2866
netlink_dump+0x541/0xc20 net/netlink/af_netlink.c:2275
__netlink_dump_start+0x647/0x900 net/netlink/af_netlink.c:2380
netlink_dump_start include/linux/netlink.h:245 [inline]
rtnetlink_rcv_msg+0x73e/0xc90 net/core/rtnetlink.c:6046
netlink_rcv_skb+0x153/0x420 net/netlink/af_netlink.c:2501
netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline]
netlink_unicast+0x543/0x7f0 net/netlink/af_netlink.c:1345
netlink_sendmsg+0x917/0xe10 net/netlink/af_netlink.c:1921
sock_sendmsg_nosec net/socket.c:714 [inline]
sock_sendmsg+0xcf/0x120 net/socket.c:734
____sys_sendmsg+0x334/0x810 net/socket.c:2489
___sys_sendmsg+0xf3/0x170 net/socket.c:2543
__sys_sendmmsg+0x195/0x470 net/socket.c:2629
__do_sys_sendmmsg net/socket.c:2658 [inline]
__se_sys_sendmmsg net/socket.c:2655 [inline]
__x64_sys_sendmmsg+0x99/0x100 net/socket.c:2655
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x46/0xb0
RIP: 0033:0x7fefd8a89109
Code: ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48
RSP: 002b:
00007fefd9ca6168 EFLAGS:
00000246 ORIG_RAX:
0000000000000133
RAX:
ffffffffffffffda RBX:
00007fefd8b9bf60 RCX:
00007fefd8a89109
RDX:
0000000004924b68 RSI:
0000000020000140 RDI:
0000000000000003
RBP:
00007fefd8ae305d R08:
0000000000000000 R09:
0000000000000000
R10:
0000000000000000 R11:
0000000000000246 R12:
0000000000000000
R13:
00007ffc346febaf R14:
00007fefd9ca6300 R15:
0000000000022000
</TASK>
Fixes:
ebc3197963fc ("ipmr: add rcu protection over (struct vif_device)->dev")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jilin Yuan [Sat, 25 Jun 2022 06:32:40 +0000 (14:32 +0800)]
sfc:falcon: fix repeated words in comments
Delete the redundant word 'in'.
Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Jilin Yuan [Sat, 25 Jun 2022 06:12:23 +0000 (14:12 +0800)]
sfc: fix repeated words in comments
Delete the redundant word 'set'.
Delete the redundant word 'a'.
Delete the redundant word 'in'.
Found the same error as before.
Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Subash Abhinov Kasiviswanathan [Fri, 24 Jun 2022 21:34:25 +0000 (15:34 -0600)]
net: Print hashed skb addresses for all net and qdisc events
The following commits added support for printing the real address-
65875073eddd ("net: use %px to print skb address in trace_netif_receive_skb")
70713dddf3d2 ("net_sched: introduce tracepoint trace_qdisc_enqueue()")
851f36e40962 ("net_sched: use %px to print skb address in trace_qdisc_dequeue()")
However, tracing the packet traversal shows a mix of hashes and real
addresses. Pasting a sample trace for reference-
ping-14249 [002] ..... 3424.046612: netif_rx_entry: dev=lo napi_id=0x3 queue_mapping=0
skbaddr=
00000000dcbed83e vlan_tagged=0 vlan_proto=0x0000 vlan_tci=0x0000 protocol=0x0800
ip_summed=0 hash=0x00000000 l4_hash=0 len=84 data_len=0 truesize=768 mac_header_valid=1
mac_header=-14 nr_frags=0 gso_size=0 gso_type=0x0
ping-14249 [002] ..... 3424.046615: netif_rx: dev=lo skbaddr=
ffffff888e5d1000 len=84
Switch the trace print formats to %p for all the events to have a
consistent format of printing the hashed addresses in all cases.
Signed-off-by: Sean Tranchetti <quic_stranche@quicinc.com>
Signed-off-by: Subash Abhinov Kasiviswanathan <quic_subashab@quicinc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Mon, 27 Jun 2022 10:47:18 +0000 (11:47 +0100)]
Merge tag 'linux-can-next-for-5.20-
20220625' of git://git./linux/kernel/git/mkl/linux-can-next
Marc Kleine-Budde says:
====================
pull-request: can-next 2022-06-25
this is a pull request of 22 patches for net-next/master.
The first 2 patches target the xilinx driver. Srinivas Neeli's patch
adds Transmitter Delay Compensation (TDC) support, a patch by me fixes
a typo.
The next patch is by me and fixes a typo in the m_can driver.
Another patch by me allows the configuration of fixed bit rates
without need for do_set_bittiming callback.
The following 7 patches are by Vincent Mailhol and refactor the
can-dev module and Kbuild, de-inline the can_dropped_invalid_skb()
function, which has grown over the time, and drop outgoing skbs if the
controller is in listen only mode.
Max Staudt's patch fixes a reference in the networking/can.rst
documentation.
Vincent Mailhol provides 2 patches with cleanups for the etas_es58x
driver.
Conor Dooley adds bindings for the mpfs-can to the PolarFire SoC dtsi.
Another patch by me allows the configuration of fixed data bit rates
without need for do_set_data_bittiming callback.
The last 5 patches are by Frank Jungclaus. They prepare the esd_usb
driver to add support for the the CAN-USB/3 device in a later series.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
David S. Miller [Mon, 27 Jun 2022 10:37:56 +0000 (11:37 +0100)]
Merge branch 'Renesas-rz-n1'
Clément Léger says:
====================
net: add support for Renesas RZ/N1 ethernet su
The Renesas RZ/N1 SoCs features an ethernet subsystem which contains
(most notably) a switch, two GMACs, and a MII converter [1]. This
series adds support for the switch and the MII converter.
The MII converter present on this SoC has been represented as a PCS
which sit between the MACs and the PHY. This PCS driver is probed from
the device-tree since it requires to be configured. Indeed the MII
converter also contains the registers that are handling the muxing of
ports (Switch, MAC, HSR, RTOS, etc) internally to the SoC.
The switch driver is based on DSA and exposes 4 ports + 1 CPU
management port. It include basic bridging support as well as FDB and
statistics support.
Link: [1] https://www.renesas.com/us/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals
-----
Changes in V9:
- Cover letter:
- Remove comment about RZN1 patches that are now in the master branch.
- Commits:
- Add Vladimir Oltean Reviewed-by
- PCS:
- Add "Depends on OF" for PCS_RZN1_MIIC due to error found by intel
kernel test robot <lkp@intel.com>.
- Check return value of of_property_read_u32() for
"renesas,miic-switch-portin" property before setting conf.
- Return miic_parse_dt() return value in miic_probe() on error
- Switch:
- Add "Depends on OF" for NET_DSA_RZN1_A5PSW due to errors found by
intel kernel test robot <lkp@intel.com>.
- DT:
- Add spaces between switch port and '{'
====================
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:40:01 +0000 (16:40 +0200)]
MAINTAINERS: add Renesas RZ/N1 switch related driver entry
After contributing the drivers, volunteer for maintenance and add
myself as the maintainer for Renesas RZ/N1 switch related drivers.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:40:00 +0000 (16:40 +0200)]
ARM: dts: r9a06g032-rzn1d400-db: add switch description
Add description for the switch, GMAC2 and MII converter. With these
definitions, the switch port 0 and 1 (MII port 5 and 4) are working on
RZ/N1D-DB board.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:59 +0000 (16:39 +0200)]
ARM: dts: r9a06g032: describe switch
Add description of the switch that is present on the RZ/N1 SoC. This
description includes ethernet-ports description for all the ports that
are present on the switch along with their connection to the MII
converter ports and to the GMAC for the CPU port.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:58 +0000 (16:39 +0200)]
ARM: dts: r9a06g032: describe GMAC2
RZ/N1 SoC includes two MAC named GMACx that are compatible with the
"snps,dwmac" driver. GMAC1 is connected directly to the MII converter
port 1. GMAC2 however can be used as the MAC for the switch CPU
management port or can be muxed to be connected directly to the MII
converter port 2. This commit add description for the GMAC2 which will
be used by the switch description.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:57 +0000 (16:39 +0200)]
ARM: dts: r9a06g032: describe MII converter
Add the MII converter node which describes the MII converter that is
present on the RZ/N1 SoC.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:56 +0000 (16:39 +0200)]
dt-bindings: net: snps,dwmac: add "renesas,rzn1" compatible
Add "renesas,rzn1-gmac" and "renesas,r9a06g032-gmac" compatible strings.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:55 +0000 (16:39 +0200)]
dt-bindings: net: snps,dwmac: add "power-domains" property
Since the stmmac driver already uses pm_runtime*() functions, describe
"power-domains" property in the binding.
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:54 +0000 (16:39 +0200)]
net: dsa: rzn1-a5psw: add FDB support
This commits add forwarding database support to the driver. It
implements fdb_add(), fdb_del() and fdb_dump().
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:53 +0000 (16:39 +0200)]
net: dsa: rzn1-a5psw: add statistics support
Add statistics support to the rzn1-a5psw driver by implementing the
following dsa_switch_ops callbacks:
- get_sset_count()
- get_strings()
- get_ethtool_stats()
- get_eth_mac_stats()
- get_eth_ctrl_stats()
- get_rmon_stats()
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:52 +0000 (16:39 +0200)]
net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver
Add Renesas RZ/N1 advanced 5 port switch driver. This switch handles 5
ports including 1 CPU management port. A MDIO bus is also exposed by
this switch and allows to communicate with PHYs connected to the ports.
Each switch port (except for the CPU management ports) is connected to
the MII converter.
This driver includes basic bridging support, more support will be added
later (vlan, etc).
Suggested-by: Jean-Pierre Geslin <jean-pierre.geslin@non.se.com>
Suggested-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:51 +0000 (16:39 +0200)]
dt-bindings: net: dsa: add bindings for Renesas RZ/N1 Advanced 5 port switch
Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is
present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP.
This company does not exists anymore and has been bought by Synopsys.
Since this IP can't be find anymore in the Synospsy portfolio, lets use
Renesas as the vendor compatible for this IP.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:50 +0000 (16:39 +0200)]
net: pcs: add Renesas MII converter driver
Add a PCS driver for the MII converter that is present on the Renesas
RZ/N1 SoC. This MII converter is reponsible for converting MII to
RMII/RGMII or act as a MII pass-trough. Exposing it as a PCS allows to
reuse it in both the switch driver and the stmmac driver. Currently,
this driver only allows the PCS to be used by the dual Cortex-A7
subsystem since the register locking system is not used.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:49 +0000 (16:39 +0200)]
dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converter
This MII converter can be found on the RZ/N1 processor family. The MII
converter ports are declared as subnodes which are then referenced by
users of the PCS driver such as the switch.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:48 +0000 (16:39 +0200)]
net: dsa: add Renesas RZ/N1 switch tag driver
The switch that is present on the Renesas RZ/N1 SoC uses a specific
VLAN value followed by 6 bytes which contains forwarding configuration.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:47 +0000 (16:39 +0200)]
net: dsa: add support for ethtool get_rmon_stats()
Add support to allow dsa drivers to specify the .get_rmon_stats()
operation.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Clément Léger [Fri, 24 Jun 2022 14:39:46 +0000 (16:39 +0200)]
net: dsa: allow port_bridge_join() to override extack message
Some drivers might report that they are unable to bridge ports by
returning -EOPNOTSUPP, but still wants to override extack message.
In order to do so, in dsa_slave_changeupper(), if port_bridge_join()
returns -EOPNOTSUPP, check if extack message is set and if so, do not
override it.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Marc Kleine-Budde [Sat, 25 Jun 2022 11:08:41 +0000 (13:08 +0200)]
Merge branch 'preparation-for-supporting-esd-CAN-USB-3'
Frank Jungclaus says:
====================
All following 5 patches must be seen as preparation for adding support
of the newly available esd CAN-USB/3 to esd_usb2.c.
After having gained some confidence and experience on sending patches
to linux-can@vger.kernel.org, I'll again submit the code changes for
CAN-USB/3 support as step #2.
====================
Link: https://lore.kernel.org/all/20220624190517.2299701-1-frank.jungclaus@esd.eu
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Frank Jungclaus [Fri, 24 Jun 2022 19:05:19 +0000 (21:05 +0200)]
can/esd_usb: Update to copyright, M_AUTHOR and M_DESCRIPTION
- Brought the copyright notice up to date
- Also regarding the changed company name from
esd electronic system design gmbh to esd electronics gmbh
- Using socketcan@esd.eu as a generic mail address for matthias who
left esd 6 years before
- Added a second MODULE_AUTHOR() for Frank Jungclaus
Link: https://lore.kernel.org/all/20220624190517.2299701-6-frank.jungclaus@esd.eu
Signed-off-by: Frank Jungclaus <frank.jungclaus@esd.eu>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Frank Jungclaus [Fri, 24 Jun 2022 19:05:18 +0000 (21:05 +0200)]
can/esd_usb: Fixed some checkpatch.pl warnings
Link: https://lore.kernel.org/all/20220624190517.2299701-5-frank.jungclaus@esd.eu
Signed-off-by: Frank Jungclaus <frank.jungclaus@esd.eu>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Frank Jungclaus [Fri, 24 Jun 2022 19:05:17 +0000 (21:05 +0200)]
can/esd_usb: Rename all terms USB2 to USB
Each occurrence of the term "usb2" within variables, function names,
comments, etc. is changed to "usb" where it is shared for all
esd CAN/USB devices.
Link: https://lore.kernel.org/all/20220624190517.2299701-4-frank.jungclaus@esd.eu
Signed-off-by: Frank Jungclaus <frank.jungclaus@esd.eu>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Frank Jungclaus [Fri, 24 Jun 2022 19:05:16 +0000 (21:05 +0200)]
can/esd_usb: Add an entry to the MAINTAINERS file
As suggested by Marc, I added an entry for ESD CAN/USB Drivers
to the MAINTAINERS file
Link: https://lore.kernel.org/all/20220624190517.2299701-3-frank.jungclaus@esd.eu
Signed-off-by: Frank Jungclaus <frank.jungclaus@esd.eu>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Frank Jungclaus [Fri, 24 Jun 2022 19:05:15 +0000 (21:05 +0200)]
can/esd_usb2: Rename esd_usb2.c to esd_usb.c
As suggested by Vincent, renaming of esd_usb2.c to esd_usb.c
and according to that, adaption of Kconfig and Makfile, too.
Link: https://lore.kernel.org/all/20220624190517.2299701-2-frank.jungclaus@esd.eu
Signed-off-by: Frank Jungclaus <frank.jungclaus@esd.eu>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Jakub Kicinski [Thu, 23 Jun 2022 20:29:33 +0000 (13:29 -0700)]
net: pcs: xpcs: depends on PHYLINK in Kconfig
This is yet another attempt at fixing:
>> ERROR: modpost: "phylink_mii_c22_pcs_encode_advertisement" [drivers/net/pcs/pcs_xpcs.ko] undefined!
>> ERROR: modpost: "phylink_mii_c22_pcs_decode_state" [drivers/net/pcs/pcs_xpcs.ko] undefined!
Switch XPCS to be invisible, as Russell points out it's
"selected" by its consumers. Drop the dependency on MDIO_BUS
as "depends" is meaningless on "selected" symbols.
Reported-by: kernel test robot <lkp@intel.com>
Fixes:
b47aec885bcd ("net: pcs: xpcs: add CL37 1000BASE-X AN support")
Link: https://lore.kernel.org/netdev/20220620201915.1195280-1-kuba@kernel.org/
Link: https://lore.kernel.org/r/20220622083521.0de3ea5c@kernel.org/
Link: https://lore.kernel.org/r/20220623202933.2341938-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>