Jennifer Yu [Fri, 18 Nov 2022 06:03:00 +0000 (22:03 -0800)]
[OPENMP5.1] Initial support for message clause.
Brad Smith [Fri, 18 Nov 2022 09:44:33 +0000 (04:44 -0500)]
[llvm] - Recognizing 'PT_OPENBSD_MUTABLE' segment type.
Recognizing 'PT_OPENBSD_MUTABLE' segment type.
https://github.com/openbsd/src/commit/
bd249b5664da50f0178adea78250a7a0d8ea6566
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D137903
chenglin.bi [Sat, 19 Nov 2022 01:11:47 +0000 (09:11 +0800)]
[GlobalISel] Fix crash in applyShiftOfShiftedLogic caused by CSEMIRBuilder reuse instruction
If LogicNonShiftReg is the same to Shift1Base, and shift1 const is the same to MatchInfo.Shift2 const, CSEMIRBuilder will reuse the old shift1 when build shift2.
So, if we erase MatchInfo.Shift2 at the end, actually we remove old shift1. And it will cause crash later.
Solution for this issue is just erase it earlier to avoid the crash.
Fix #58423
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D138187
Fangrui Song [Sat, 19 Nov 2022 01:06:26 +0000 (01:06 +0000)]
[asan] Keep Itanium mangled names in global metadata
The runtime calls `MaybeDemangleGlobalName` for error reporting and
`__cxxabiv1::__cxa_demangle` is called if available, so demanging Itanium
mangled names in global metadata is unnecessary and wastes data size.
Add `MaybeDemangleGlobalName` in ODR violation detection to support demangled
names in a suppressions file. `MaybeDemangleGlobalName` may call
`DemangleCXXABI` and leak memory. Use an internal allocation to prevent lsan
leak (in case there is no fatal asan error).
The debug feature `report_globals=2` prints information for all instrumented
global variables. `MaybeDemangleGlobalName` would be slow, so don't do that.
The output looks like `Added Global[0x56448f092d60]: beg=0x56448fa66d60 size=4/32 name=_ZL13test_global_2`
and I think the mangled name is fine.
Other mangled schemes e.g. Windows (see win-string-literal.ll) remain the
current behavior.
Reviewed By: hctim
Differential Revision: https://reviews.llvm.org/D138095
Matt Arsenault [Tue, 15 Nov 2022 22:07:07 +0000 (14:07 -0800)]
GlobalISel: Try to fold G_SEXT_INREG to G_AND with mask
Copies the same transform from the DAG. Helps eliminate some codegen
diffs to allowed shared checks in a future change.
Not sure if apply supports anything better than C++ fragments for
the result. It's also not really reasonable that every combine has
to set the default insertion point.
Fazlay Rabbi [Fri, 18 Nov 2022 23:21:49 +0000 (15:21 -0800)]
[OpenMP] Initial parsing/sema for 'strict' modifier with 'num_tasks' clause
This patch gives basic parsing and semantic analysis support for 'strict'
modifier with 'num_tasks' clause of 'taskloop' construct introduced in
OpenMP 5.1 (section 2.12.2)
Differential Revision: https://reviews.llvm.org/D138328
Matt Arsenault [Mon, 14 Nov 2022 23:22:45 +0000 (15:22 -0800)]
AMDGPU/GlobalISel: Add some end-to-end g_sext_inreg tests
Matt Arsenault [Mon, 14 Nov 2022 23:44:22 +0000 (15:44 -0800)]
AMDGPU/GlobalISel: Insert freeze when splitting vector G_SEXT_INREG
This transform is broken for undef or poison inputs without a freeze.
This is also broken in lots of other places where shifts are split
into 32-bit pieces.
Amt < 32 case:
; Broken: https://alive2.llvm.org/ce/z/7bb4vc
; Freezing the low half of the bits makes it correct
; Fixed: https://alive2.llvm.org/ce/z/zJAZFr
define i64 @src(i64 %val) {
%shl = shl i64 %val, 55
%shr = ashr i64 %shl, 55
ret i64 %shr
}
define i64 @tgt(i64 %val) {
%lo32 = trunc i64 %val to i32
%shr.half = lshr i64 %val, 32
%hi32 = trunc i64 %shr.half to i32
%inreg.0 = shl i32 %lo32, 23
%new.lo = ashr i32 %inreg.0, 23
%new.hi = ashr i32 %new.lo, 31
%zext.lo = zext i32 %new.lo to i64
%zext.hi = zext i32 %new.hi to i64
%hi.ins = shl i64 %zext.hi, 32
%or = or i64 %hi.ins, %zext.lo
ret i64 %or
}
Amt == 32 case:
Broken: https://alive2.llvm.org/ce/z/5f4qwQ
Fixed: https://alive2.llvm.org/ce/z/A2hWWF
This one times out alive; works if argument is made noundef or
scaled down to a smaller bitwidth.
define i64 @src(i64 %val) {
%shl = shl i64 %val, 32
%shr = ashr i64 %shl, 32
ret i64 %shr
}
define i64 @tgt(i64 %val) {
%lo32 = trunc i64 %val to i32
%shr.half = lshr i64 %val, 32
%hi32 = trunc i64 %shr.half to i32
%new.hi = ashr i32 %lo32, 31
%zext.lo = zext i32 %lo32 to i64
%zext.hi = zext i32 %new.hi to i64
%hi.ins = shl i64 %zext.hi, 32
%or = or i64 %hi.ins, %zext.lo
ret i64 %or
}
Amt > 32 case:
; Correct: https://alive2.llvm.org/ce/z/tvrhPf
define i64 @src(i64 %val) {
%shl = shl i64 %val, 9
%shr = ashr i64 %shl, 9
ret i64 %shr
}
define i64 @tgt(i64 %val) {
%lo32 = trunc i64 %val to i32
%lshr = lshr i64 %val, 32
%hi32 = trunc i64 %lshr to i32
%inreg.0 = shl i32 %hi32, 9
%new.hi = ashr i32 %inreg.0, 9
%zext.lo = zext i32 %lo32 to i64
%zext.hi = zext i32 %new.hi to i64
%hi.ins = shl i64 %zext.hi, 32
%or = or i64 %hi.ins, %zext.lo
ret i64 %or
}
Peter Rong [Thu, 17 Nov 2022 23:12:48 +0000 (15:12 -0800)]
[FuzzMutate] Update InstModifierStrategy
We can randomly switch two operands of an instruction now
Signed-off-by: Peter Rong <PeterRong96@gmail.com>
Philip Reames [Fri, 18 Nov 2022 23:30:39 +0000 (15:30 -0800)]
[RISCV] Optimize scalable frame setup when VLEN is precisely known
If we know the exact value of VLEN, the frame offset adjustment for scalable stack slots becomes a fixed constant. This avoids the need to read vlenb, and may allow the offset to be folded into the immediate field of an add/sub.
We could go further here, and fold the offset into a single larger frame adjustment - instead of having a separate scalable adjustment step - but that requires a bit more code reorganization. I may (or may not) return to that in a future patch.
Differential Revision: https://reviews.llvm.org/D137593
Philip Reames [Fri, 18 Nov 2022 23:29:14 +0000 (15:29 -0800)]
Revert "[SDAG] Allow scalable vectors in ComputeKnownBits"
This reverts commit
bc0fea0d551b5182c541c43070830bfdcaa33ef2.
There was a "timeout for a Halide Hexagon test" reported. Revert until investigation complete.
Philip Reames [Fri, 18 Nov 2022 23:14:18 +0000 (15:14 -0800)]
Revert "[SDAG] Allow scalable vectors in ComputeNumSignBits" and follow up
This reverts commits
3fb08d14a63f5f745d3fec2b5f6ffef4cf0a398c and
f8c63a7fbf50fb5883bd566c7539d0ac18c7700f.
There was a "timeout for a Halide Hexagon test" reported. Revert until investigation complete.
Matt Arsenault [Fri, 18 Nov 2022 07:03:23 +0000 (23:03 -0800)]
GlobalISel: Legalize strict_fsub
In the future should probably have a more convenient
way to switch between building strict and non-strict ops.
Teresa Johnson [Thu, 17 Nov 2022 02:07:07 +0000 (18:07 -0800)]
[MemProf] Defer profile file setup until dump time
With all of the writing of the memprof profile consolidated into one
place, there is no need to set up the profile file (which creates the
file and also redirects all printing from the runtime to it) until we
are ready to dump the profile.
This allows errors and other messages to be dumped to stderr instead of
the profile file, which by default is in a binary format. Additionally,
reset the output file to stderr after dumping the profile so that any
requested memprof allocator statistics are printed to stderr.
Differential Revision: https://reviews.llvm.org/D138175
Michael Jones [Fri, 11 Nov 2022 22:08:58 +0000 (14:08 -0800)]
[libc][reland] Fix builtin definition for memory functions
The memory functions are highly performance sensitive and use builtins
where possible, but also need to define those functions names when they
don't exist to avoid compilation errors. Previously all those
redefinitions were behind the SSE2 flag for x86, which caused errors on
CPUs that supported SSE2 but not AVX512. This patch splits the various
CPU extensions out to avoid errors on such CPUs.
Reviewed By: gchatelet
Differential Revision: https://reviews.llvm.org/D138163
Doru Bercea [Thu, 17 Nov 2022 21:30:53 +0000 (15:30 -0600)]
[Clang][OpenMP] Add support for default to/from map types on target enter/exit data
Med Ismail Bennani [Fri, 18 Nov 2022 21:56:19 +0000 (13:56 -0800)]
[lldb/Python] Unify PythonFormat & GetPythonValueFormatString (NFC)
This patch removes all occurences to GetPythonValueFormatString and
use the template specialization of PythonFormat structs instead.
Differential Revision: https://reviews.llvm.org/D134033
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Med Ismail Bennani [Fri, 18 Nov 2022 21:53:57 +0000 (13:53 -0800)]
[lldb/Plugins] Improve error reporting with reading memory in Scripted Process
This patch improves the ScriptedPythonInterface::Dispatch method to
support passing lldb_private types to the python implementation.
This will allow, for instance, the Scripted Process python implementation
to report errors when reading memory back to lldb.
To do so, the Dispatch method will transform the private types in the
parameter pack into `PythonObject`s to be able to pass them down to the
python methods.
Then, if the call succeeded, the transformed arguments will be converted
back to their original type and re-assigned in the parameter pack, to
ensure pointers and references behaviours are preserved.
This patch also updates various scripted process python class and tests
to reflect this change.
rdar://
100030995
Differential Revision: https://reviews.llvm.org/D134033
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Med Ismail Bennani [Fri, 18 Nov 2022 07:55:52 +0000 (23:55 -0800)]
[lldb/Python] Make use of PythonObject and PythonFormat in callbacks (NFC)
This patch extends the template specialization of PythonFormat structs
and makes use of the pre-existing PythonObject class to format arguments
and pass them to the right method, before calling it.
This is a preparatory patch to merge PythonFormat with SWIGPythonBridge's
GetPythonValueFormatString methods.
Differential Revision: https://reviews.llvm.org/D138248
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Sami Tolvanen [Fri, 18 Nov 2022 21:23:04 +0000 (21:23 +0000)]
[X86][KCFI] Don't fold loads into indirect calls that need a KCFI check
Avoid unnecessary folding as X86KCFIPass would have to unfold these
anyway when emitting the KCFI_CHECK.
Krzysztof Parzyszek [Fri, 18 Nov 2022 21:45:07 +0000 (13:45 -0800)]
[Hexagon] Remove non-existent instructions
Some instructions that don't actually exist in hardware were emitted
by the generator script in error. Delete them from the .td files.
Arthur Eubanks [Fri, 18 Nov 2022 21:35:51 +0000 (13:35 -0800)]
[Bye] Remove legacy pipeline registration
D137915 has somehow caused a flang bot to fail: https://lab.llvm.org/buildbot/#/builders/191/builds/11279.
Given that the issue is with the legacy pipeline registration code and the legacy pipeline registration infrastructure is to be removed soon, remove this part of Bye.
Peiming Liu [Wed, 16 Nov 2022 23:18:16 +0000 (23:18 +0000)]
[mlir][sparse] refactoring: move genAffine to loopEmitter
This is the beginning patch of a sequence of dependent patches that in together provide the affine expression on matched indexing mapping for sparse tensors.
This patch itself simply move `genAffine` into loop emitter to be prepared for upcoming patches.
D138169 provides support for affine expression on dense dimensions only (except for constant affine expression)
D138170 provides support for constant affine expressions on dense dimensions
D138171 provides **merger** support for affine expression on sparse dimension (without codegen)
D138172 provides **codegen** support (by generating a "filter" loop) for affine expression on sparse dimensions.
D138173 fixes a crash on resolveCycle when dealing with affine expressions.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D138168
Simon Pilgrim [Fri, 18 Nov 2022 21:10:46 +0000 (21:10 +0000)]
[MCA][X86] Add test coverage for VPCLMULQDQ instructions
Evgenii Stepanov [Thu, 3 Nov 2022 19:42:37 +0000 (12:42 -0700)]
[scudo] Detect double free when running with MTE.
Try to trigger an MTE fault on double/invalid free by touching the first
byte of the allocation with the provided pointer.
Differential Revision: https://reviews.llvm.org/D137352
Sanjay Patel [Fri, 18 Nov 2022 20:56:38 +0000 (15:56 -0500)]
[VectorCombine] check instruction type before dispatching to folds
This is no externally visible change intended, but appears to be a
noticeable (surprising) improvement in compile-time based on:
https://llvm-compile-time-tracker.com/compare.php?from=
0f3e72e86c8c7c6bf0ec24bf1e2acd74b4123e7b&to=
5e8c2026d10e8e2c93c038c776853bed0e7c8fc1&stat=instructions:u
The early returns in the individual fold functions are not good
enough to avoid the overhead of the many "fold*" calls, so this
speeds up the main instruction loop enough to make a difference.
Simon Pilgrim [Thu, 17 Nov 2022 21:20:37 +0000 (21:20 +0000)]
[MCA][X86] Add missing IceLake test coverage for VPOPCNTDQ instructions
Simon Pilgrim [Thu, 17 Nov 2022 20:56:19 +0000 (20:56 +0000)]
[MCA][X86] Add test coverage for AVX512CD instructions
Slava Zakharin [Fri, 18 Nov 2022 20:08:02 +0000 (12:08 -0800)]
[flang] Use proper attributes for runtime calls with 'i1' arguments/returns.
Clang uses signext/zeroext attributes for integer arguments shorter than
the default 'int' type on a target. So Flang has to match this for functions
from Fortran runtime and also for BIND(C) routines. This patch implements
ABI adjustments only for Fortran runtime calls. BIND(C) part will be done
separately.
This resolves https://github.com/llvm/llvm-project/issues/58579
Differential Revision: https://reviews.llvm.org/D137050
Philip Reames [Fri, 18 Nov 2022 20:28:22 +0000 (12:28 -0800)]
[SDAG] Address post commit review feedback from
f8c63a7f
The major change is falling through to ComputeKnownBits when we don't have an implementation of ComputeNumSignBits due to conservatism over scalable vectors. Right now, we're mostly conservative in the same cases, but this allows our results to improve when we change ComputeKnownBits without also needing to improve ComputeNumSignBits at the same time.
Valentin Clement [Fri, 18 Nov 2022 20:16:50 +0000 (21:16 +0100)]
[flang] Add ClassIs runtime function
Add a `ClassIs` function that takes a descriptor and a
type desc to implement the check needed by the CLASS IS type guard
in SELECT TYPE construct.
Since the kind type parameter are directly folded in the type itself
in Flang and the type descriptor is a global, the function just check
if the type descriptor address of the descriptor is equivalent to
the type descriptor address of the global. If not, it check in the
parents of the descriptor's type descriptor.
Reviewed By: jeanPerier
Differential Revision: https://reviews.llvm.org/D138279
Slava Zakharin [Mon, 7 Nov 2022 20:48:32 +0000 (12:48 -0800)]
[mlir][llvmir] Translate function result attributes to LLVM IR.
Translate align, noalias, noundef, signext and zeroext result
attributes from llvm.func to LLVM IR.
This is needed for https://github.com/llvm/llvm-project/issues/58579
Differential Revision: https://reviews.llvm.org/D137049
Rob Suderman [Fri, 18 Nov 2022 19:43:55 +0000 (11:43 -0800)]
[mlir][tosa] Fix tosa.slice shape inference for ShapedType:kDynamicShape
Change for kDynamicShape means the size needs to be updated to a new value
for slice operation shape inference. Landing fix.
Reviewed By: NatashaKnk
Differential Revision: https://reviews.llvm.org/D138314
Nico Weber [Fri, 18 Nov 2022 19:28:59 +0000 (14:28 -0500)]
[bolt] Fix std::prev()-past-begin in veneer handling code
matchLinkerVeneer() returns 3 if `Instruction` and the last
two instructions in `[Instructions.begin, Instructions.end())`
match the pattern
ADRP x16, imm
ADD x16, x16, imm
BR x16
BinaryContext.cpp used to use
--Count;
for (auto It = std::prev(Instructions.end()); Count != 0;
It = std::prev(It), --Count) {
...use It...
}
to walk these instructions. The first `--Count` skips the
instruction that's in `Instruction` instead of in `Instructions`.
The loop then walks over `Instructions`.
However, on the last iteration, this calls `std::prev()` on an
iterator that points at the container's begin(), which can blow
up.
Instead, use rbegin(), which sidesteps this issue.
Fixes test/AArch64/veneer-gold.s on a macOS host.
With this, check-bolt passes on macOS.
Differential Revision: https://reviews.llvm.org/D138313
Kelvin Li [Mon, 7 Nov 2022 19:20:53 +0000 (14:20 -0500)]
[flang] Add more diagnostic for MAX/MIN intrinsic
Fix https://github.com/llvm/llvm-project/issues/56303
Differential Revision: https://reviews.llvm.org/D137742
Valentin Clement [Fri, 18 Nov 2022 19:32:18 +0000 (20:32 +0100)]
[flang][NFC] Remove unused DispatchTableop fct
Remove `appendTableEntry` as it is not used.
Reviewed By: jeanPerier, PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D138293
Bill Wendling [Fri, 18 Nov 2022 00:07:15 +0000 (16:07 -0800)]
Revert "Reapply: Add an error message to the default SIGPIPE handler"
This patch is spamming compiles with unhelpful and confusing messages.
E.g. the Linux kernel uses "grep -q" in several places. It's meant to
quit with a return code of zero when the first match is found. This can
cause a SIGPIPE signal, but that's expected, and there's no way to turn
this error message off to avoid spurious error messages.
UNIX03 apparently doesn't require printing an error message on SIGPIPE,
but specifically when there's an error on the stdout stream in a normal
program flow, e.g. when SIGPIPE trap is disabled.
A separate patch is planned to address the specific case we care most
about (involving llvm-nm).
This reverts commit
b89bcefa6202e310eb3167dd1c37f1807377ec8d.
Link: https://github.com/llvm/llvm-project/issues/59037
Link: https://github.com/ClangBuiltLinux/linux/issues/1651
Differential Revision: https://reviews.llvm.org/D138244
Aaron Ballman [Fri, 18 Nov 2022 19:15:02 +0000 (14:15 -0500)]
Add more tests for C DRs and update the status page
Krzysztof Parzyszek [Thu, 17 Nov 2022 23:16:06 +0000 (15:16 -0800)]
[Hexagon] Add checks for immediate arguments for remaining builtins
Checks for builtins for the following instructions were aded:
V6_v6mpyhubs10
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyvubs10_vxx
V6_vlutvvbi
V6_vlutvvb_oracci
V6_vlutvwhi
V6_vlutvwh_oracci
Peter Rong [Fri, 18 Nov 2022 18:53:29 +0000 (10:53 -0800)]
[FuzzMutate] change of format and comment for further code
Signed-off-by: Peter Rong <PeterRong96@gmail.com>
Philip Reames [Fri, 18 Nov 2022 17:57:42 +0000 (09:57 -0800)]
[SDAG] Allow scalable vectors in ComputeNumSignBits
This is a continuation of the series of patches adding lane wise support for scalable vectors in various knownbit-esq routines.
The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.
Differential Revision: https://reviews.llvm.org/D137141
Abhina Sreeskantharajan [Fri, 18 Nov 2022 18:38:53 +0000 (13:38 -0500)]
[SystemZ][z/OS] Set text flag correctly for llvm-reduce tool
This patch sets the text flag correctly for llvm-reduce files
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D138304
Matt Arsenault [Fri, 11 Nov 2022 19:35:14 +0000 (11:35 -0800)]
ConstantFolding: Constant fold some canonicalizes
+/-0 is obviously foldable. Other non-special, non-subnormal
values are also probably OK. For denormal values, check
the calling function's denormal mode. For now, don't fold
denormals to the input for IEEE mode because as far as I know
the langref is still pretending LLVM's float isn't IEEE.
Also folds undef to 0, although NaN may make more sense. Skips
folding nans and infinities, although it should be OK to fold those
in a future change.
Michael Maitland [Fri, 18 Nov 2022 18:09:50 +0000 (10:09 -0800)]
[RISCV][CodeGen] Chapter of vector instruction type corresponds with chapters in RISCV vector specification. NFC
The [vector spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc) is organized in chapters
based on instruction type. The comments in the tablegen marked the incorrect chapters. This change
updates the comments with the correct chapter numbers.
Differential Revision: https://reviews.llvm.org/D138311
Diego Caballero [Fri, 18 Nov 2022 18:06:49 +0000 (18:06 +0000)]
[mlir][NFC] Add static ShapedType::isDynamicShape utility
This utility is useful when we need to know if shape is dynamic and
we don't have a Type itself.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D138267
Matt Arsenault [Fri, 18 Nov 2022 17:36:38 +0000 (09:36 -0800)]
AMDGPU: Fix fcanonicalize constant folding not correctly handling -0.0
Philip Reames [Fri, 18 Nov 2022 17:52:01 +0000 (09:52 -0800)]
[RISCV] Optimize scalable frame offset calculation when VLEN is precisely known
When we have a precisely known VLEN, we can replace runtime usage of VLENB with compile time constants. This converts offsets involving both fixed and scalable components into fixed offsets. The result is that we avoid the csr read of vlenb, and can often fold the multiply as well.
Differential Revision: https://reviews.llvm.org/D137591
Michael Maitland [Fri, 4 Nov 2022 15:51:39 +0000 (08:51 -0700)]
[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV
On x86 and AArch, SIMD instructions encode all of the scheduling information in the instruction
itself. For example, VADD.I16 q0, q1, q2 is a neon instruction that operates on 16-bit integer
elements stored in 128-bit Q registers, which leads to eight 16-bit lanes in parallel. This kind
of information impacts how the instruction takes to execute and what dependencies this may cause.
On RISCV however, the data that impacts scheduling is encoded in CSR registers such as vtype or
vl, in addition with the instruction itself. But MCA does not track or use the data in these
registers. This patch fixes this problem by introducing Instruments into MCA.
* Replace `CodeRegions` with `AnalysisRegions`
* Add `Instrument` and `InstrumentManager`
* Add `InstrumentRegions`
* Add RISCV Instrument and `InstrumentManager`
* Parse `Instruments` in driver
* Use instruments to override schedule class
* RISCV use lmul instrument to override schedule class
* Fix unit tests to pass empty instruments
* Add -ignore-im clopt to disable this change
A prior version of this patch was commited in
5e82ee537321.
2323a4ee610f reverted
that change because the unit test files caused build errors. The change with fixes
were committed in
b88b8307bf9e but reverted once again
e8e92c8313a0 due to more
build errors.
This commit adds the prior changes and fixes the build error.
Differential Revision: https://reviews.llvm.org/D137440
Krzysztof Parzyszek [Thu, 17 Nov 2022 23:16:06 +0000 (15:16 -0800)]
[Hexagon] Add clang flags for v71, v71t, v73
Mirko Brkusanin [Fri, 18 Nov 2022 17:09:24 +0000 (18:09 +0100)]
[AMDGPU] Add subtarget feature for MAD_U64/I64 bug on GFX11
Differential Revision: https://reviews.llvm.org/D133012
Matt Arsenault [Wed, 16 Nov 2022 20:49:00 +0000 (12:49 -0800)]
AMDGPU: Add some baseline tests for llvm.amdgcn.trig.preop folding
zhijian [Fri, 18 Nov 2022 17:10:16 +0000 (12:10 -0500)]
[XCOFF] llvvm-readobj support display symbol table of loader section of xcoff object file.
Reviewers: James Henderson, Esme Yi
Differential Revision: https://reviews.llvm.org/D135887
Nico Weber [Fri, 18 Nov 2022 16:35:35 +0000 (11:35 -0500)]
[bolt] Pass %cflags in test/X86/is-strip.s
Without this, clang builds a binary for macOS on a macOS host, and
then the linker complains that it doesn't know the -q flag.
Differential Revision: https://reviews.llvm.org/D138306
Nico Weber [Fri, 18 Nov 2022 16:33:23 +0000 (11:33 -0500)]
[bolt] Make test/X86/end-symbol.test not use "tac"
"tac" doesn't exist on macOS, so this makes the test pass there.
Differential Revision: https://reviews.llvm.org/D138305
Nico Weber [Fri, 18 Nov 2022 15:36:14 +0000 (10:36 -0500)]
[bolt] Clean up lit site cfg files a bit
* Stop setting config.python_executable in Unit/lit.site.cfg.py.in.
All other projects only set this in the main lit config, not in the
one for unit tests. (Unit tests don't spawn Python.)
* Set config.python_executable to Python3_EXECUTABLE in main
lit.site.cfg.py.in instead of PYTHON_EXECUTABLE. All other files
did this in
c4c3883b00.
* Stop setting enable_abi_breaking_checks, enable_backtrace, enable_shared.
Nothing in bolt's tests (or in lit) reads them.
Differential Revision: https://reviews.llvm.org/D138299
Alex Langford [Thu, 17 Nov 2022 21:46:40 +0000 (13:46 -0800)]
[lldb] Restore default setting of LLDB_INCLUDE_TESTS in standalone builds
In
52f39853abd46495a6d636c4b035e1b92cf4b833 the option LLDB_INCLUDE_TESTS was
moved above the inclusion of LLDBStandalone. This isn't a problem per-se, but
it changes the default value of LLDB_INCLUDE_TESTS in standalone builds.
LLDBStandalone explicitly sets LLVM_INCLUDE_TESTS to true, indicating that
for standalone builds this is considered the default behavior.
This patch restores said default behavior.
Differential Revision: https://reviews.llvm.org/D138237
Petar Avramovic [Fri, 18 Nov 2022 17:00:01 +0000 (18:00 +0100)]
AMDGPU/GlobalISel: Fix crash after mad/fma_mix fails selection
When selectVOP3PMadMixModsImpl fails, it can still create new copy instr
via selectVOP3ModsImpl. When selectG_FMA_FMAD gives up, new copy instr
will remain dead but will not be automatically removed.
InstructionSelect does not check if instructions created during selection
are dead.
Such dead copy doesn't have register class on dst operand and causes crash.
Fix is to build copy when operands are being added to selected instruction.
Differential Revision: https://reviews.llvm.org/D138044
Jay Foad [Fri, 18 Nov 2022 16:11:18 +0000 (16:11 +0000)]
[AMDGPU] Stop looking for implicit M0 uses on MOV instructions
Before D114230, indirect moves used regular MOV opcodes and were
identified by having an implicit use of M0. Since D114230 they use
dedicated opcodes instead, so remove some old code that checks for
implicit uses of M0. NFCI.
Differential Revision: https://reviews.llvm.org/D138308
Matt Arsenault [Fri, 11 Nov 2022 18:30:22 +0000 (10:30 -0800)]
InstSimplify: Add baseline tests for canonicalize
Matt Arsenault [Fri, 18 Nov 2022 06:14:35 +0000 (22:14 -0800)]
AMDGPU/GlobalISel: Fix strictfp fmul
Xing Xue [Fri, 18 Nov 2022 16:36:56 +0000 (11:36 -0500)]
[Clang][CodeGen][AIX] Map __builtin_frexpl, __builtin_ldexpl, and __builtin_modfl to 'double' version lib calls in 64-bit 'long double' mode
Summary:
AIX library functions frexpl(), ldexpl(), and modfl() are for 128-bit IBM long double, i.e. __ibm128. Other *l() functions, e.g., acosl(), are for 64-bit long double. The AIX Clang compiler currently maps builtin functions __builtin_frexpl(), __builtin_ldexpl(), and __builtin_modfl() to frexpl(), ldexpl(), and modfl() in 64-bit long double mode which results in seg-faults or incorrect return values. This patch changes to map __builtin_frexpl(), __builtin_ldexpl(), and __builtin_modfl() to double version lib functions frexp(), ldexp() and modf() in 64-bit long double mode.
Reviewed by: hubert.reinterpretcast, daltenty
Differential Revision: https://reviews.llvm.org/D137986
Louis Dionne [Thu, 17 Nov 2022 15:33:08 +0000 (10:33 -0500)]
[libc++] Use numeric_limits instead of raw INT_MAX
This allows discard_block_engine to work on platforms that might not
provide a full <limits.h> header.
Differential Revision: https://reviews.llvm.org/D138212
Dinar Temirbulatov [Fri, 18 Nov 2022 16:21:10 +0000 (16:21 +0000)]
[AArch64][SVE] Use PTRUE instruction instead of WHILELO if the range is appropriate for predicator constant.
While get_active_lane_mask lowering it uses WHILELO instruction,
but forconstant range suitable for PTRUE then we could issue PTRUE instruction
instead.
Differential Revision: https://reviews.llvm.org/D137547
David Spickett [Fri, 18 Nov 2022 16:15:51 +0000 (16:15 +0000)]
[LLDB][AArch64] Add
BF16BF16, SME2p1 and SVE2p1 to disassembler test
See:
https://reviews.llvm.org/rGcf69895ab31b
https://reviews.llvm.org/D136352
https://reviews.llvm.org/D137410
Krzysztof Parzyszek [Fri, 18 Nov 2022 15:35:03 +0000 (07:35 -0800)]
[Hexagon] Add missing patterns for mulhs/mulhu
bzcheeseman [Wed, 16 Nov 2022 05:23:18 +0000 (21:23 -0800)]
[MLIR][Parser] Add `parseBase64Bytes`.
This patch adds `parseBase64Bytes` to the parser. It attempts to avoid double-allocating the buffer by re-using the token's spelling directly and eliding the quotes if they exist. It also avoids extra allocations by using std::vector<char> in the API - something we should change when the llvm::decodeBase64 API changes.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D138090
Raphael Isemann [Wed, 16 Nov 2022 23:52:02 +0000 (00:52 +0100)]
[lldb] Fix that empty target.run-args are not actually used when launching process
`GetPropertyAtIndexAsArgs` returns true on success and false on failure. Right
now it returns the converted `size_t` returned from `GetArgs` which describes
the number of arguments in the argument list. So for empty argument lists
(`(size_t)0` -> `(bool)false`) this function always fails.
The only observable effect of this seems to be that empty arguments are never
propagated to the internal LaunchInfo for a process. This causes that once any
argument has been added to `target.run-args`, clearing `target.run-args` doesn't
have any effect.
Fixes issue #55568
Reviewed By: JDevlieghere, jingham
Differential Revision: https://reviews.llvm.org/D126057
David Spickett [Fri, 18 Nov 2022 12:55:15 +0000 (12:55 +0000)]
[libcxx] Fix link to Buildbot interface
Reviewed By: #libc, philnik, ldionne
Differential Revision: https://reviews.llvm.org/D138286
Philip Reames [Fri, 18 Nov 2022 15:23:10 +0000 (07:23 -0800)]
[SDAG] Allow scalable vectors in ComputeKnownBits
his is the SelectionDAG equivalent of D136470, and is thus an alternate patch to D128159.
The basic idea here is that we track a single lane for scalable vectors which corresponds to an unknown number of lanes at runtime. This is enough for us to perform lane wise reasoning on many arithmetic operations.
This patch also includes an implementation for SPLAT_VECTOR as without it, the lane wise reasoning has no base case. The original patch which inspired this (D128159), also included STEP_VECTOR. I plan to do that as a separate patch.
Differential Revision: https://reviews.llvm.org/D137140
Timm Bäder [Fri, 18 Nov 2022 13:53:28 +0000 (14:53 +0100)]
[clang][NFC] Remove unused parameter from ParseConstantExpression
Florian Hahn [Fri, 18 Nov 2022 15:19:50 +0000 (15:19 +0000)]
[llvm-reduce] Do not crash when accessing landingpads of invokes.
Unconditionally removing landing pads results in invalid IR,
if there is a different `invoke` that uses it. Update the code
to only remove the landing pad if the current invoke is the only
user. Also carefully avoid creating plain branches to bbs with
landing pads we couldn't remove.
Reviewed By: arsenm, aeubanks
Differential Revision: https://reviews.llvm.org/D138072
Timm Bäder [Fri, 18 Nov 2022 13:46:16 +0000 (14:46 +0100)]
[clang][parse] Avoid creating StmtVectors every loop iteration
Timm Bäder [Sat, 12 Nov 2022 17:06:06 +0000 (18:06 +0100)]
[clang][sema][NFC] Make some local variables const
We don't modify them. Also use auto here since we already wrote the full
type in the cast.
Alexander Timofeev [Fri, 18 Nov 2022 15:16:10 +0000 (16:16 +0100)]
ARCRegisterInfo::eliminateFrameIndex updated to fix build error caused by
32bd75716c27d1a094c2436529b596ce1547f6eb
Alexander Timofeev [Thu, 17 Nov 2022 18:03:22 +0000 (19:03 +0100)]
PEI should be able to use backward walk in replaceFrameIndicesBackward.
The backward register scavenger has correct register
liveness information. PEI should leverage the backward register scavenger.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D137574
Oleg Shyshkov [Fri, 18 Nov 2022 13:45:33 +0000 (14:45 +0100)]
[mlir][linalg] Do not check if added dimension are static in linalg.broadcast.
Added dimensions can be both static and dinamic. Mapped dimension should be the same in the input and the init.
Differential Revision: https://reviews.llvm.org/D138291
Nico Weber [Fri, 18 Nov 2022 14:47:01 +0000 (09:47 -0500)]
[bolt] add missing space in "llvm-bolt -help" output
gbreynoo [Fri, 18 Nov 2022 14:37:56 +0000 (14:37 +0000)]
[llvm-ar] Fix when llvm-ar fails to replace existing members when updating a thin archive
As seen in https://github.com/llvm/llvm-project/issues/55023 when a thin
archive is updated when not in the CWD, replacement does not work as
expected. This change fixes the relative file path comparison so the
correct files are updated.
Differential Revision: https://reviews.llvm.org/D138218
David Sherwood [Fri, 18 Nov 2022 13:07:35 +0000 (13:07 +0000)]
[AArch64][SME2] Remove vector constraints from zip/uzp (2-vector) instruction classes
The zip/uzp (2-vector) instruction classes have the incorrect
register constraints and mark the destination as also being an
input. However, the instructions are fully destructive so I've
restructured the classes.
Differential Revision: https://reviews.llvm.org/D138288
Tobias Gysi [Fri, 18 Nov 2022 14:04:38 +0000 (15:04 +0100)]
[mlir][llvm] Iterative constant import from LLVM IR.
Instead of importing constant expressions recursively, the revision
walks all dependencies of an LLVM constant iteratively. The actual
conversion then iterates over a list of constants and all intermediate
constant values are added to the value mapping. As a result, an LLVM IR
constant maps to exactly one MLIR operation per function. The revision
adapts the existing tests since the constant ordering changed for
aggregate types. Additionally, it adds extra tests that mix aggregate
constants and constant expressions.
Depends on D137416
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D137559
Haojian Wu [Fri, 18 Nov 2022 14:05:56 +0000 (15:05 +0100)]
[clang-tidy] Remove a duplicated if-branch in the unused-using-decl
check, NFC
Aarush Bhat [Fri, 18 Nov 2022 13:54:31 +0000 (21:54 +0800)]
[docs] remove extra slash from llvm github url
Reviewed By: tstellar
Differential Revision: https://reviews.llvm.org/D137418
Phoebe Wang [Fri, 18 Nov 2022 13:08:01 +0000 (21:08 +0800)]
[X86] Use lock add/sub for cases that we only care about the EFLAGS
This fixes #36373, #36905 and partial of #58685.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D137711
Guillaume Chatelet [Fri, 18 Nov 2022 10:14:37 +0000 (10:14 +0000)]
[reland][libc][bazel] Add tests to the bazel build
This patch adds bazel tests for llvm-libc.
Some math tests rely on the `mpfr` library. This is controlled via the `--@llvm-project//libc:libc_math_mpfr` flag. It can take three values:
- `external` (default) will build `mpfr` and `gmp` from source.
- `system` will use the system installed `mpfr` library.
- `disable` will skip tests relying on `mpfr`.
Reviewed By: sivachandra, GMNGeoffrey
Differential Revision: https://reviews.llvm.org/D119547
Tom Praschan [Wed, 16 Nov 2022 23:20:37 +0000 (00:20 +0100)]
[Support] Add support for attaching payloads to points and ranges
This is useful where tests previously encoded information in the name
names of ranges and points. Currently, this is pretty limited because
names consist of only alphanumeric characters and '_'.
With this patch, we can keep the names simple and attach optional
payloads to ranges and points instead.
The new syntax should be fully backwards compatible (if I haven't missed
anything). I tested this against clangd unit tests and everything still passes.
Differential Revision: https://reviews.llvm.org/D137909
Haojian Wu [Mon, 14 Nov 2022 08:58:39 +0000 (09:58 +0100)]
[include-cleaner] Add self-contained file support for PragmaIncludes.
And use it findHeaders. findHeaders now finds all header candidates
given a symbol location (these headers will be attached with proper
signals, in a followup patch).
Differential Revision: https://reviews.llvm.org/D137698
Phoebe Wang [Fri, 18 Nov 2022 12:50:24 +0000 (20:50 +0800)]
[X86] Pre-commit tests for pr58685
OCHyams [Fri, 18 Nov 2022 12:36:41 +0000 (12:36 +0000)]
[Assignment Tracking][24/*] Always RemoveRedundantDbgInstrs in instcombine in assignment tracking builds
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
This reduces peak memory overhead by 15% when building CTMark's tramp3d-v4 with
-O2 -g with assignment tracking enabled.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D133321
OCHyams [Fri, 18 Nov 2022 12:20:58 +0000 (12:20 +0000)]
Fix inliner test after
e3cd498ff7748f967be1bdcc0a994e40ce82268f
Bot failure: https://lab.llvm.org/buildbot/#/builders/16/builds/38156
e3cd498ff7748f967be1bdcc0a994e40ce82268f (D133318) updates CloneBlock to
preserve debug use-before-defs. Update local-as-metadata-undominated-use.ll to
reflect this.
Hassnaa Hamdi [Thu, 17 Nov 2022 17:40:51 +0000 (17:40 +0000)]
[AArch64][SME]: Generate streaming-compatible code for ISD::INSERT_VECTOR_ELT.
1- Enable custom lowering INSERT_VECTOR_ELT to generate code compatible
to streaming mode.
2- Add testing file:
insert-vector-elt.ll
Differential Revision: https://reviews.llvm.org/D138222
Hassnaa Hamdi [Thu, 17 Nov 2022 17:38:30 +0000 (17:38 +0000)]
[AArch64][SME]: Add precursory tests for D138222
Dominik Adamski [Thu, 20 Oct 2022 13:20:37 +0000 (08:20 -0500)]
[mlir][OpenMP] Add order clause definition to simd construct
Update simd construct definition and add mlir tests to prove
that order(concurrent) clause is correctly modeled for simd
construct.
Jay Foad [Fri, 18 Nov 2022 11:56:12 +0000 (11:56 +0000)]
[AMDGPU] Test MAD formation on GFX11
GFX11 has no MAD instructions, only FMA, so this is just testing that we
generate separate MUL and ADD.
OCHyams [Fri, 18 Nov 2022 11:49:43 +0000 (11:49 +0000)]
[Assignment Tracking][21/*] Account for assignment tracking in inliner
The Assignment Tracking debug-info feature is outlined in this RFC:
https://discourse.llvm.org/t/
rfc-assignment-tracking-a-better-way-of-specifying-variable-locations-in-ir
The inliner requires two additions:
fixupAssignments - Update inlined instructions' DIAssignID metadata so that
inlined DIAssignID attachments are unique to the inlined instance.
trackInlinedStores - Treat inlined stores to caller-local variables
(i.e. callee stores to argument pointers that point to the caller's allocas) as
assignments. Track them using trackAssignments, which is the same method as is
used by the AssignmentTrackingPass. This means that we're able to detect stale
memory locations due to DSE after inlining. Because the stores are only tracked
_after_ inlining, any DSE or movement of stores _before_ inlining will not be
accounted for. This is an accepted limitation mentioned in the RFC.
One change is also required:
Update CloneBlock to preserve debug use-before-defs. Otherwise the assignments
will be dropped due to having the intrinsic operands replaced with empty
metadata (see use-before-def.ll in this patch and this related discourse post.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D133318
Nico Weber [Fri, 18 Nov 2022 11:48:07 +0000 (06:48 -0500)]
[gn build] port
7059a6c32cfa
Hassnaa Hamdi [Thu, 17 Nov 2022 15:27:45 +0000 (15:27 +0000)]
[AArch64][SME]: Use SVE mov instruction for FPR128 registers in streaming-compatible mode.
1- in streaming mode, use SVE OR/mov instruction instead of NEON OR,
during copying phyReg -AArch64InstrInfo::copyPhysReg-.
2- add testing file:
register-mov.ll
Differential Revision: https://reviews.llvm.org/D138211
Dmitry Preobrazhensky [Fri, 18 Nov 2022 11:12:22 +0000 (14:12 +0300)]
[AMDGPU][GFX11][NFC] Refactor VOPD operands handling (part 2)
Rename interface functions and operands to make code clearer.
Differential Revision: https://reviews.llvm.org/D138133
Valery Pykhtin [Thu, 17 Nov 2022 19:19:04 +0000 (20:19 +0100)]
[AMDGPU] Fix PreRARematStage::sinkTriviallyRematInsts region boundary update after sinking.
First boundary of a region wasn't updated when a sinked instruction was added first into the region.
Reviewed By: vangthao
Differential Revision: https://reviews.llvm.org/D138256
Matthias Springer [Fri, 18 Nov 2022 10:18:19 +0000 (11:18 +0100)]
[mlir] GreedyPatternRewriter: Reprocess modified ops
Ops that were modifed in-place (`finalizeRootUpdate` was called) should be reprocessed by the GreedyPatternRewriter. This is currently not happening with `GreedyRewriteConfig::maxIterations = 1`.
Note: If your project goes into an infinite loop because of this change, you likely have one or multiple faulty patterns that modify the same operations in-place (`updateRootInplace`) indefinitely.
Differential Revision: https://reviews.llvm.org/D138038
Benjamin Maxwell [Fri, 18 Nov 2022 10:14:55 +0000 (10:14 +0000)]
[DAG] Allow folding AND of anyext masked_load with >1 user to zext version
This now allows folding an AND of a anyext masked_load to a
zext_masked_load even if the masked load has multiple users. Doing is
eliminates some redundant ANDs/MOVs for certain AArch64 SVE code.
I'm not sure if there's any cases where doing this could negatively the
other users of the masked_load. Looking at other optimizations of
masked loads, most don't apply if the load is used more than once, so it
doesn't look like this would interfere.
Reviewed By: c-rhodes
Differential Revision: https://reviews.llvm.org/D137844