iris: Add pre-draw flushing for stream output targets

When stream output is active, we need to let the cache tracker know
about any SO buffers, which we access via IRIS_DOMAIN_OTHER_WRITE.

In particular, we may have written to those buffers via another
mechanism, such as BLORP buffer copies.  In that case, previous writes
happened via IRIS_DOMAIN_RENDER_WRITE, in which case we'd need to flush
both the render cache and the tile cache to make that data globally-
observable before we begin writing via streamout, which is incoherent
with the earlier mechanism.

Fixes misrendering in Ryujinx.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6085
Fixes: d8cb76211c5 ("iris: Fix MOCS for buffer copies")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

iris: Extend the cache tracker to handle L3 flushes and invalidates

Most clients are L3-coherent these days.  However, there are some
notable exceptions, such as push constants, stream output, and command
streamer memory reads and writes.

With the advent of the tile cache, flushing the render or depth caches
alone are no longer sufficient for memory to become globally-observable.
For those, we need to flush the tile cache as well.  However, we'd like
to avoid that for L3-coherent clients, as it shouldn't be necessary,
and is expensive.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

iris: Add a separate PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE bit

This will let us use it without performing a VF cache invalidation,
should we want to do that.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

iris: Add an iris_is_domain_l3_coherent helper.

The render, depth, sampler, and data (HDC) caches are all coherent
with L3.  We consider OTHER_READ and OTHER_WRITE to be non-coherent,
as they're kitchen-sink domains which include non-L3-clients.

Starting with Tigerlake, the VF cache is coherent with L3 (because we
set the L3BypassDisable bit in the vertex/index buffer packets).

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

iris: Fix UBO cache tracking for the !indirect_ubos_use_sampler case

On Tigerlake, we use the data cache for reading indirect UBOs instead
of the sampler.  But we still use the constant cache for direct UBO
access, so unfortunately we may access it through two different domains.

To work around this, we add a new domain for pull constants (UBOs),
which will be either constant+texture or constant+data.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

iris: Split out an IRIS_DOMAIN_SAMPLER_READ domain from OTHER_READ

The bulk of IRIS_DOMAIN_OTHER_READ domain usage was the 3D sampler, but
there were also a few oddball cases like command streamer reads, blitter
access, and so on.  The sampler is definitely L3 coherent, but some off
the more esoteric reads may not be, so I'd like to separate them, so
that OTHER_READ can become a non-L3-coherent kitchen-sink domain.

The sampler cases only need TEXTURE_CACHE_INVALIDATE, and can skip the
CONSTANT_CACHE_INVALIDATE we had on IRIS_DOMAIN_OTHER_READ.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

iris: Use IRIS_DOMAIN_DEPTH_WRITE for read only depth/stencil.

We were using IRIS_DOMAIN_OTHER_READ for read-only depth/stencil access
in an attempt to avoid unnecessary flushing; IRIS_DOMAIN_DEPTH_WRITE
could indicate read-write access.

However, IRIS_DOMAIN_OTHER_READ is clearly the wrong domain.  Depth and
stencil data is read via the depth cache, while IRIS_DOMAIN_OTHER_READ
currently corresponds to the sampler cache and constant cache together
(although this will change in future patches).

It's unclear whether this hack was useful.  For now, just drop it and
use the correct depth cache domain, even if it's marked as read-write.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

virgl: Apply integer op fix only for ALU ops and clear modifiers

For texture fetches and buffer load the fix is not needed,
and the override creates faulty TGSI.

In addition remove all modifiers from the src in the additional mov
instruction.

Fixes: d1c7a7b1317c518e160cc6d37245de22b2bfa60d
  virgl: Add an extra mov for int outputs from constant and immediate inputs

v2: Move workaround after the use of
    virgl_tgsi_rewrite_src_for_input_temp (Emma)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15896>

r600: Assign shader type when creating a new CS state

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15898>

st/mesa: Transcode ASTC to BC7 (BPTC) where possible

This patch adds support for transcoding ASTC to BC7 (BPTC) and prefers
it over BC3 (DXT5) when hardware supports that format.

BC7 is a much newer format (~2009 vs. ~1999) and offers higher quality
than the older BC3 format.  Furthermore, our encoder seems to be faster.

Tapani put together a small benchmark for transcoding a 1024x1024 ASTC
texture, and switching from BC3 to BC7 improves performance of that
microbenchmark by 25% on my Tigerlake NUC (with hardware ASTC disabled
so we can test this path).  Presumably, this isn't fundamental to the
formats, but rather reflects the speed of our in-tree compressors.

So, we should use BC7 where possible.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15875>

st/mesa: Make transcode_astc also check for non-SRGB format support

This is probably unnecessary in that all drivers which support the sRGB
format likely also support the non-sRGB format.  But we may as well
check both the formats we use, for documentation if nothing else.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15875>

ci: Move most stuff out of root .gitlab-ci.yml

This file was getting a bit hard to navigate. Split container, build and
test jobs to their own files.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15891>

ci: Allow local installations to build additional stuff into the rootfs

This can make it more convenient for other projects to reuse these
scripts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15891>

ci: Add env var to add packages to install in debian/arm_build image

This can make it more convenient for other projects to reuse these
scripts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15891>

ci: Add env var to add packages to install in rootfs

This can make it more convenient for other projects to reuse these
scripts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15891>

ci: Allow specifying a different kernel in LAVA jobs

To make it possible to use a kernel different from that built along with
the rootfs.

This can make it more convenient for other projects to reuse these
scripts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15891>

ci: Use CI_PROJECT_NAME instead of hardcoding 'mesa'

This can make it more convenient for other projects to reuse these
scripts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15891>

nir/lower_shader_calls: name resume shaders

Helpful when lost in a sea of NIR :)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15887>

ci: Disable Google's lab

The runner is down and pipelines are being stuck.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15909>

zink: rework choose_pdev to (finally) be competent

now zink will init using a priority system if multiple devices are available

multiple devices will ONLY be available if:
* the user does not specify VK_ICD_FILENAMES as they should
* the user does not specify LIBGL_ALWAYS_SOFTWARE
* multiple drivers exist

I've prioritized the virtualized gpu here with the assumption that if
such a thing is detected, the environment is most likely virtualized

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15857>

aux/trace: clean up some zink+lavapipe tracing awfulness

now that it's easier to determine whether zink is being used (mostly),
this whole thing can be simplified

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15857>

zink: ZINK_USE_LAVAPIPE -> LIBGL_ALWAYS_SOFTWARE

this is a documented variable, so reuse it

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15857>

egl: don't make LIBGL_ALWAYS_SOFTWARE and MESA_LOADER_DRIVER_OVERRIDE=zink exclusive

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15857>

ac/gpu_info: disallow displayable DCC for Navi12 and Navi14

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15813>

intel/nir: Lower 8 and 16-bit bitwise unops

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15829>

intel/fs: Implement 16-bit [ui]mul_high

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15829>

nir/lower_int64: Fix [iu]mul_high handling

e551040c602d, which added a new mechanism for 64-bit imul which is more
efficient on BDW and later Intel hardware also introduced a bug where we
weren't properly walking both X and Y.  No idea how testing didn't find
this.

Fixes: e551040c602d ("nir/glsl: Add another way of doing lower_imul64 for gen8+"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6306
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15829>

kopper: print better error message if loader not detected

silently failing on release builds is annoying

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15851>

lima: fix vector const src referenced multiple times

It can happen that a single vector constant is referenced multiple times
by the same node, with different swizzles.
This needs to be taken into account by checking and updating the
swizzles for all the srcs of a target node when inserting the const
node to the same instruction.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15726>

features: mark off ARB_seamless_cubemap_per_texture for zink

forgot to do this with the MR

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15902>

ntt: translate nir_intrinsic_shader_clock

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15889>

zink: finish up radv piglit baseline updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15900>

radv: Refactor ray tracing support checks

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15860>

radv: Refactor radv_tex_aniso_filter

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15860>

radv: set read/write without format flags for supported texel buffers

if the storage case is supported, this should be supported too

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15826>

Revert "radv: Disable NGG for GS with suboptimal output vertex count."

It breaks too many things and shouldn't have been merged. The fix isn't
trivial and it will probably not be backported because it's intrusive.

It will be re-applied later when everything will work.

This reverts commit 94706601fa2f52605d6e488f30fad9a0e2440612.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15882>

r600: make r600_load_ar available to driver code

This is needed for the new NIR assembler

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>

r600: Set the last bit if an alu group is split by kcache allocation

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>

r600: Force last instruction of group when starting a new CF

When emitting the AR forces splitting an ALU group, and at the same time
a new CF instruction is started, then the last instrcution in the finished
CF block might not have the "last" bit set, which results in an invalid
shader that might hang, or crash SB.
So when a new CF is started, force the last bit in the last ALU instruction.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>

r600: don't reschedule INTERP_LOAD_P0

With the NIR code, we have instructions groups that use
INTERP_LOAD_P0 that don't fill all slots. Just make sure
the backend scheduler doesn't fill in INTERP_LOAD_P0
instructions with a different LDS location.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>

r600: ignore dest sel for non-write targets when counting registers

Since the value is not written, there is no need to allocate
a register for it, so don't take it into account.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>

r600: Don't limit scheduling of PARAM_SRC values

ALU_SRC_PARAM_BASE is an inline constant that defines the
address for pulling data from LDS memory for interpolation
and not a value from the kcache, so there is no need to
take these values into account when allocating kcache
load slots.

v2: Fix the constant range check to not exclude the translated
    ranges for kcache banks 2 and 3.
v3: limit range check to only include kcache values and and
    rename relevant function (Emma).

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15714>

radv: increase inline push constant limit if we can inline all constants

fossil-db (Sienna Cichlid):
Totals from 665 (0.49% of 134627) affected shaders:
CodeSize: 4519620 -> 4491724 (-0.62%); split: -0.62%, +0.01%
Instrs: 842745 -> 837313 (-0.64%); split: -0.66%, +0.01%
Latency: 7289925 -> 7279661 (-0.14%); split: -0.30%, +0.16%
InvThroughput: 1240770 -> 1240639 (-0.01%); split: -0.01%, +0.00%
VClause: 15799 -> 15772 (-0.17%)
SClause: 33773 -> 32604 (-3.46%); split: -3.66%, +0.20%
Copies: 67695 -> 64992 (-3.99%); split: -4.49%, +0.50%
PreSGPRs: 38597 -> 38640 (+0.11%); split: -0.14%, +0.25%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12145>

radv,aco: implement 64-bit inline push constants

fossil-db (Sienna Cichlid):
Totals from 21 (0.02% of 134621) affected shaders:
CodeSize: 1932 -> 1560 (-19.25%)
Instrs: 357 -> 303 (-15.13%)
Latency: 6576 -> 5883 (-10.54%)
InvThroughput: 26304 -> 23532 (-10.54%)
SClause: 42 -> 24 (-42.86%)
Copies: 90 -> 105 (+16.67%); split: -10.00%, +26.67%
PreSGPRs: 144 -> 201 (+39.58%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12145>

radv: allow holes in inline push constants

Use a dword mask instead of a range to track which push constants to
inline.

fossil-db (Sienna Cichlid):
Totals from 5724 (4.25% of 134621) affected shaders:
CodeSize: 20894044 -> 20815748 (-0.37%); split: -0.39%, +0.02%
Instrs: 4002568 -> 3988385 (-0.35%); split: -0.38%, +0.02%
Latency: 29285060 -> 29224414 (-0.21%); split: -0.22%, +0.01%
InvThroughput: 5529700 -> 5526893 (-0.05%); split: -0.05%, +0.00%
VClause: 78093 -> 78240 (+0.19%); split: -0.23%, +0.41%
SClause: 135495 -> 131027 (-3.30%); split: -3.30%, +0.00%
Copies: 330856 -> 324552 (-1.91%); split: -2.37%, +0.46%
PreSGPRs: 226031 -> 224778 (-0.55%); split: -0.61%, +0.05%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12145>

radv: allow inline push constants in more situations

We don't need to disable this path if there are indirect or 8/16/64-bit
push constant loads. We can just use the default path for them.

fossil-db (Sienna Cichlid):
Totals from 21 (0.02% of 134621) affected shaders:
CodeSize: 2028 -> 1884 (-7.10%)
Instrs: 366 -> 363 (-0.82%); split: -2.46%, +1.64%
Latency: 6630 -> 6579 (-0.77%)
InvThroughput: 26520 -> 26316 (-0.77%)
Copies: 84 -> 102 (+21.43%)
PreSGPRs: 141 -> 222 (+57.45%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12145>

intel/fs: Enable b2f(inot(a)) and b2i(inot(a)) optimization for Gfx12+

The commit enables the optimization for Intel Gfx12+ graphics.

Tigerlake
```
total instructions in shared programs: 1289326 -> 1289015 (-0.02%)
instructions in affected programs: 37841 -> 37530 (-0.82%)
helped: 78
HURT: 9
helped stats (abs) min: 1 max: 26 x̄: 4.69 x̃: 3
helped stats (rel) min: 0.10% max: 12.50% x̄: 2.07% x̃: 1.21%
HURT stats (abs)   min: 1 max: 18 x̄: 6.11 x̃: 4
HURT stats (rel)   min: 0.16% max: 1.95% x̄: 0.94% x̃: 0.61%
95% mean confidence interval for instructions value: -4.95 -2.20
95% mean confidence interval for instructions %-change: -2.34% -1.18%
Instructions are helped.

total cycles in shared programs: 105606388 -> 105606442 (<.01%)
cycles in affected programs: 620119 -> 620173 (<.01%)
helped: 49
HURT: 28
helped stats (abs) min: 2 max: 3618 x̄: 228.63 x̃: 12
helped stats (rel) min: 0.02% max: 23.31% x̄: 4.60% x̃: 1.11%
HURT stats (abs)   min: 1 max: 2142 x̄: 402.04 x̃: 29
HURT stats (rel)   min: 0.01% max: 36.42% x̄: 5.01% x̃: 0.46%
95% mean confidence interval for cycles value: -151.80 153.20
95% mean confidence interval for cycles %-change: -3.00% 0.79%
Inconclusive result (value mean confidence interval includes 0).
```

Related-to: https://gitlab.freedesktop.org/mesa/mesa/-/commit/7725d609387a8165ccb71e2d9e0221d9248b1729
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14017>

virgl: Add an extra mov for int outputs from constant and immediate inputs

virglrenderer doesn't properly emit the conversion code when the source
is a integer value and the output is also integer.

Fixes on NTT:
  dEQP-GLES31.functional.shaders.sample_variables.sample_mask.inverse_per_*

v2: fix typo (Emma)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15836>

virgl: Always make some extra temps available for transformations

The host driver will optimize unused variables away, and checking thoroughly whether we
may need an extra temp is just uselessly costly.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15836>

virgl: Propagate precice flag through moves

NIR doesn't propagate precise through moves, and with NTT the
last output is usually preceded by a move, so that we no longer
see that the evaluation of some value is supposed to be exact,
and, hence we can't decorate the outputs accordingly.

Fixes with NTT:
 dEQP-GLES31.functional.tessellation.common_edge.
     triangles_equal_spacing_precise
     triangles_fractional_odd_spacing_precise
     triangles_fractional_even_spacing_precise
     quads_equal_spacing_precise
     quads_fractional_odd_spacing_precise
     quads_fractional_even_spacing_precise

v2: Don't clear the precise flag when we hit a mov, because we may
    hit a if/else construct like below and we don't track branches

    IF X
       TEMP[0] = OP_PRECICE ...
    ELSE
       TEMP[0] = MOV CONST[]
    ENDIF

    Thanks Emma for pointing out the problem.

v2: allocate precise handling flags to transform_prolog (Emma)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15836>

ci: add Broadcom CI maintainer

Include in the CODEOWNERS file who to ping in case of issues with the
Broadcom (V3D/V3DV/VC4) CI.

v2:
 - Add Chema (Chema)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15858>

CODEOWNERS: add Broadcom maintainers

v2:
 - Add more maintainers (Iago)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15858>

r600: Only emit the NOP group triggered by dest.rel after a full group

In addition really fill all slots, because otherwise the alu-group merger
might move a read from the indirectly written register into the 't' slot.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15848>

drm-shim: Implement a shim function for close

Remove the fd from the fd_map, so that if the fd is later reused for
another file then mmap won't be intercepted.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12203>

drm-shim: Explicitly use off64_t for the offset to drm_shim_mmap

drm_shim.c undefines the _FILE_OFFSET_BITS macro, so plain off_t might
be 32 bits, while it's 64 bits in device.c. To avoid this mismatch,
use off64_t which will always be 64 bits in both source files.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12203>

drm-shim: Return fake render nodes in /dev/dri first

loader_open_render_node returns the first device in /dev/dri that it
can use. To make sure the drm-shim device always gets chosen, return
the fake entries in readdir before returning the real ones.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12203>

drm-shim: Add a function for mmap64 rather than using an alias

Fixes build on 32-bit systems.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12203>

nir: remove gl_PrimitiveID output from MS when it's not used in FS

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15340>

anv: initialize 3DMESH_1D.ExtendedParameter0 when ExtendedParameter0Present

When IndirectParameterEnable==true it's not actually used by the hardware,
but if it's not initialized and INTEL_DEBUG=bat is set, then Valgrind complains.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15850>

anv: fix push constant lowering for task/mesh

Fixes: a6031cd9bd4 ("anv: fix push constant lowering with bindless shaders")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15850>

glsl/st: use nir pass to lower indirect rather than GLSL IR

Will allow us to drop more GLSL IR code in future once we switch
all drivers to NIR. Also stops the need for all drivers to call
this pass to remove indirect temps that may have been added during
the NIR varying linking lowering/optimisations.

This patch fixes some tests on i915, d3d12, lima and vc4.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15871>

radv: add few helpers to deal with pipeline layout

With VK_EXT_graphics_pipeline_library, we will have to support
independent sets and also to merge sets from different libraries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15849>

radv: remove unused radv_pipeline_layout::size field

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15849>

radv: drop the remaining uses of shader modules

With VK_EXT_graphics_pipeline_library, shader modules can be NULL and
be passed via the pNext of VkPipelineShaderStageCreateInfo. To prepare
for this, just store everything we need to radv_pipeline_stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15847>

radv: store the shader sha1 to radv_pipeline_stage

To remove use of shader modules completely in the next commit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15847>

radv: replace convert_rt_stage() by vk_to_mesa_shader_stage()

Mesa shader stages are correctly sorted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15847>

nine: check hardware support before using vertex texture

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15864>

zink: create pipeline layout if only bindless descriptor set is used

bindless descriptors are descriptors too.

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15853>

zink: handle 0 ubos and 0 ssbos in pipeline layout

this is the number of types needed, and it can be zero

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15853>

zink: prune unused st-injected pointsize exports

only the last vertex stage needs to keep these, so prune any that aren't
being weirdly passed through

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15853>

zink: try copy region first for non-resolve blits

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15853>

zink: refactor copy_region path in zink_blit to util function

no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15853>

draw: handle tess eval shader when getting num outputs

This tripped up some pointsize/prim id interactions with zink.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15872>

turnip: Move autotune buffers to suballoc.

Now the ANGLE trex_200 trace replay does a single BO allocation at startup
for autotune results instead of one per frame (~350 for the whole replay).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

turnip: Get autotune off of ralloc destructors.

We've wanted to remove destructors from ralloc's API for a long time (it's
an extra storage cost per ralloc for a rarely-used feature), and for the
suballoc change we'd need to spend more storage on storing the tu_device
pointer per result since destructors don't get anything else but the
pointer passed into them.

Fixes use-after-frees:

=================================================================
==2383==ERROR: AddressSanitizer: heap-use-after-free on address 0xffff88fe1940 at pc 0xffff934f427c bp 0xfffff5481e90 sp 0xfffff5481ea8
WRITE of size 8 at 0xffff88fe1940 thread T0
    #0 0xffff934f4278 in list_del ../src/util/list.h:108
    #1 0xffff934f4278 in result_destructor ../src/freedreno/vulkan/tu_autotune.c:237
    #2 0xffff9377793c in unsafe_free ../src/util/ralloc.c:300
    #3 0xffff9377793c in ralloc_free ../src/util/ralloc.c:265
    #4 0xffff934f4368 in history_destructor ../src/freedreno/vulkan/tu_autotune.c:229
    #5 0xffff9377793c in unsafe_free ../src/util/ralloc.c:300
    #6 0xffff9377793c in ralloc_free ../src/util/ralloc.c:265
    #7 0xffff934f5990 in tu_autotune_on_submit ../src/freedreno/vulkan/tu_autotune.c:442
[...]

0xffff88fe1940 is located 80 bytes inside of 112-byte region [0xffff88fe18f0,0xffff88fe1960)
freed by thread T0 here:
    #0 0xffff9c1c90d8 in __interceptor_free ../../../../src/libsanitizer/asan/asan_malloc_linux.cpp:127
    #1 0xffff934f4368 in history_destructor ../src/freedreno/vulkan/tu_autotune.c:229
    #2 0xffff9377793c in unsafe_free ../src/util/ralloc.c:300
    #3 0xffff9377793c in ralloc_free ../src/util/ralloc.c:265
    #4 0xffff934f5990 in tu_autotune_on_submit ../src/freedreno/vulkan/tu_autotune.c:442
    #5 0xffff935cf2ac in tu_queue_submit_locked ../src/freedreno/vulkan/tu_drm.c:997
[...]

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

turnip: Reduce the pipeline's CS allocation a bit.

We don't return unused space to the suballocator, so it's a little useful
to limit how much we overallocate to reduce memory footprint.  I took a
look through the tu_cs_emit_array() calls and accounted for a couple of
them in the variant-specific space calculation, then dropped the base
allocation by factors of 2 until we started throwing asserts.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

turnip: Skip telling the kernel the BO list when we don't need any.

In fencing, we sometimes do a dummy submit with no nr_cmds.  If we don't
have commands to execute, we don't need to pin or fence any BOs either.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

turnip: Sub-allocate pipelines out of a device-global BO pool.

Allocating a BO for each pipeline meant that for apps with many pipelines
(such as Asphalt9 under ANGLE), we would end up spending too much time in
the kernel tracking the BO references.

Looking at CS:Source on zink, before we had 85 BOs for the pipelines for a
total of 1036 kb, and now we have 7 BOs for a total of 896 kb.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

turnip: Stop allocating unused pvtmem space in the pipeline CS.

The pvtmem was split off to a separate read/write BO.

Fixes: 931ad19a1817 ("turnip: make cmdstream bo's read-only to GPU")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

turnip: Track refcounts on BOs in kgsl as well.

I'm going to be using the BO refcount for the pipeline and autotune buffer
suballocation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15038>

intel/perf: Fix OA report accumulation on Gfx12+.

The intel_perf_query path used for performance queries on GL was
passing a bogus "end" pointer to intel_perf_query_result_accumulate(),
causing it to accumulate garbage values.  This was causing the values
of many performance counters to be corrupted.

The "end" pointer was incorrect because the current code was assuming
that different OA reports were located TOTAL_QUERY_DATA_SIZE bytes
apart, which is a hard-coded preprocessor define.  However recent
(Gfx12+) hardware generations use a variable query size determined by
the query layout.  Use the size derived from it instead, and remove
the stale define.

Fixes: 3c513250255d6a ("intel/perf: switch query code to use query layout")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15783>

zink/query: refactor out vk queries and allow sharing them

gallium queries have to be mapped onto multiple vulkan queries,
this can happen for two reasons.

1. primitives generated and overflow any don't map directly, and
multiple vulkan queries are needs per iteration. These are stored
inside the "starts" as zink_vk_query ptrs.

2. suspending/resuming queries uses multiple queries, these are
the "starts". Every suspend/resume cycle adds a new start.

Vulkan also requires that multiple queries of the same time don't
execute at once, which affects the overflow any vs xfb normal
queries, so vk_query structs are refcounted and can be shared
between starts. Due to this when the draw state changes, it's
simple to just suspend/resume all queries so the shared vulkan
queries get handled properly.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15785>

r300: move pointer dereference after a NULL check

Vs state can be NULL by the time r300_set_constant_buffer is called.
We don't hit this with OpenGL though, so this is why I didn't spot
this in my testing, but nine hits this codepath. Restore the original
behavior here.

Fixes: 882811b1ff67fa37197e27f56caaffbe3e6164d6
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15842>

zink: add issue notes for remaining radv fails

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15867>

llvmpipe: remove unused array

chans variable doesn't need to be an array.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6204
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15556>

llvmpipe: fix color rendering on big endian.

Some colors were missing/inverted on big endian machine(s390x).
because blend_type.length > src_fmt->nr_channels.
In my case, blend_type has 4 channels (rgba) but src_fmt has only 3.

So the from_lsb was wrong by 1, and channels got messed up.
(blue was always 255, green -> red, and blue -> green).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6204
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15556>

zink: update radv piglit baseline

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15865>

intel/genxml: Add SAMPLER_MODE bits for enabling Small PL on Icelake

This enables a lower power mode in the sampler hardware in certain
common scenarios.  On Tigerlake, SAMPLER_MODE is not programmable by
userspace but the kernel already sets this bit for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>

intel/genxml: Delete SAMPLER_MODE register definition on Gfx12+

While this register still exists, it's no longer a per-context register.
Instead, on Gfx12+, SAMPLER_MODE exists per dual-subslice and is
accessed as a "multicast" register, where you write control which
version is accessed by the "steering control register".

At any rate, userspace cannot write it any longer, and so there's not
much point to it existing in our genxml (which was missing most of the
fields anyway).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>

intel/genxml: Add new "Low Quality Filter" field on Gfx12+.

This allows the sampler to perform faster filtering of 8-bit UNORM
textures by filtering them at a different precision.  The filtering
is intended to still be OpenGL and DirectX spec compliant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>

intel/genxml: Add SAMPLER_STATE::Allow Low Quality LOD Calculation field

This allows the hardware to perform a faster LOD calculation in many
simple cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15628>

ci: enable v3dv arm64 jobs

This reverts commit f567a832eed19cf01bb5f38e662f5ed53a8ac47f.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15856>

zink: reorganize radv ci baseline

categorize known fails and move remainder to top of file for better
visibility

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15855>

zink: update radv ci baseline

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15855>

dzn: Fix loop condition in dzn_descriptor_set_copy()

We need to make sure we still have descriptors to copy in the
while() condition. While at it, drop the assert() checking that
the number of descriptors already copied is less than the
requested number.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15828>

zink: only do swapchain update during fb setup if swapchain is active

otherwise this explodes blitter operations

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15809>

util: Convert util/u_printf.cpp to util/u_printf.c

By doing this to remove the need of C++ runtime when not using llvmpipe

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15659>

util: Add tests for u_printf.h

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15659>

zink: force texture barriers when performing in-renderpass clears

according to spec, a barrier is required any time the pixels of the
framebuffer are changed. since zink defers clears and runs them at
a later time, it must also be responsible for handling the required
synchronization for such operations

fixes (radv):
KHR-GL46.blend_equation_advanced.blend_all*

fixes #5572

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15831>

zink: rework texture_barrier hook

according to spec, for fbfetch this should match the subpass self-dependency of
* stage   FRAGMENT_STAGE -> FRAGMENT_STAGE
* access  0 -> INPUT_ATTACHMENT_READ

zs fbfetch doesn't seem to be a thing, so that code is left for historical
and/or future purposes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15831>