Siva Durga Prasad Paladugu [Sun, 21 Feb 2016 10:16:14 +0000 (15:46 +0530)]
net: xilinx_axi: Use interface type instead of zero
Pass appropriate interface type to phy_connect
instead of zero.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Fri, 5 Feb 2016 07:52:12 +0000 (13:22 +0530)]
zynq-common: Enable phy driver for Xilinx PCS/PMA core
Add support of Xilinx PCS/PMA core phy for Zynq
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Fri, 5 Feb 2016 07:52:11 +0000 (13:22 +0530)]
net: zynq_gem: Add support for SGMII interface
Add support of SGMII interface for zynq GEM.
Read xlnx,emio property from DT.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Fri, 5 Feb 2016 07:52:10 +0000 (13:22 +0530)]
phy: Add phy driver support for xilinx PCS/PMA core
Add phy driver support for xilinx PCS/PMA core
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Karsten Merker [Mon, 21 Mar 2016 19:29:07 +0000 (20:29 +0100)]
net: phy: Realtek RTL8211B/C PHY ID fix
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.
The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.
After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.
Fix this by setting the full PHY ID in the RTL8211B_driver uid field.
Fixes:
42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: Karsten Merker <merker@debian.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Scott Wood [Fri, 1 Apr 2016 23:49:57 +0000 (18:49 -0500)]
MAINTAINERS: Update Scott Wood's email address
Freescale is now NXP. I still work there, but I won't be using their
mail system for U-Boot development.
Signed-off-by: Scott Wood <oss@buserror.net>
Eric Nelson [Sun, 27 Mar 2016 19:00:15 +0000 (12:00 -0700)]
sata: use block layer for sata command
Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is
used if enabled and to remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Eric Nelson [Sun, 27 Mar 2016 19:00:14 +0000 (12:00 -0700)]
mmc: use block layer in mmc command
Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is
used if enabled and to remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Eric Nelson [Mon, 28 Mar 2016 17:05:44 +0000 (10:05 -0700)]
drivers: block: add block device cache
Add a block device cache to speed up repeated reads of block devices by
various filesystems.
This small amount of cache can dramatically speed up filesystem
operations by skipping repeated reads of common areas of a block
device (typically directory structures).
This has shown to have some benefit on FAT filesystem operations of
loading a kernel and RAM disk, but more dramatic benefits on ext4
filesystems when the kernel and/or RAM disk are spread across
multiple extent header structures as described in commit fc0fc50.
The cache is implemented through a minimal list (block_cache) maintained
in most-recently-used order and count of the current number of entries
(cache_count). It uses a maximum block count setting to prevent copies
of large block reads and an upper bound on the number of cached areas.
The maximum number of entries in the cache defaults to 32 and the maximum
number of blocks per cache entry has a default of 2, which has shown to
produce the best results on testing of ext4 and FAT filesystems.
The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows
changing these values and can be used to tune for a particular filesystem
layout.
Signed-off-by: Eric Nelson <eric@nelint.com>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:34 +0000 (23:12 +0200)]
Add myself as Snapdragon and SPMI maintainer
- Update MAINTAINERS
- Update git-mailrc
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:33 +0000 (23:12 +0200)]
board: Add Qualcomm Dragonboard 410C support
This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC
U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:32 +0000 (23:12 +0200)]
arm: Add support for Qualcomm Snapdragon family
First supported chip is APQ8016 (that is compatible with MSM8916).
Drivers in SoC code:
- Reset controller (PSHOLD)
- Clock controller (very simple clock configuration for MMC and UART)
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:31 +0000 (23:12 +0200)]
gpio: Add support for Qualcomm PM8916 gpios
This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:30 +0000 (23:12 +0200)]
pmic: Add support for Qualcomm PM8916 PMIC
This PMIC is connected on SPMI bus so needs SPMI support enabled.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:29 +0000 (23:12 +0200)]
drivers: spmi: Add support for Qualcomm SPMI bus driver
Support SPMI arbiter on Qualcomm Snapdragon devices.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:28 +0000 (23:12 +0200)]
spmi: Add sandbox test driver
This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:27 +0000 (23:12 +0200)]
drivers: Add SPMI bus uclass
Qualcom processors use proprietary bus to talk with PMIC devices -
SPMI (System Power Management Interface).
On wiring level it is similar to I2C, but on protocol level, it's
multi-master and has simple autodetection capabilities.
This commit adds simple uclass that provides bus read/write interface.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:26 +0000 (23:12 +0200)]
ehci: Add support for Qualcomm EHCI
This driver is able to reconfigure OTG controller into HOST mode.
Board can add board-specific initialization as board_prepare_usb().
It requires USB_ULPI_VIEWPORT enabled in board configuration.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:25 +0000 (23:12 +0200)]
ehci-ci.h: drop generic USBCMD fields
Use definitions from ehci.h instead.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:24 +0000 (23:12 +0200)]
usb: ehci-ci: Add missing registers.
Some registers of usb_ehci were marked as reserved.
This may be true for some variants of Chipidea USB core, but they have
meaning on other devices.
The following registers were added:
sbusstatus/sbusmode: AHB-related registers
genconfig*: Auxiluary IP core configuration registers.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:23 +0000 (23:12 +0200)]
usb: Rename ehci-fsl.h to ehci-ci.h
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.
This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:22 +0000 (23:12 +0200)]
eth: asix88179: Print packet length properly
Debug printf used '%u' to print size_t variable.
This caused warnings on 64-bit machines.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:21 +0000 (23:12 +0200)]
usb: ulpi: Fix compile warning in read/write on 64-bit machines.
ulpi_read and ulpi_write are used to read/write registers via ULPI bus.
Code generates compilation warnings on 64-bit machines where pointer
is cast to u32.
This patch drops all but last 8 bits of register address.
It is possible, because addresses on ULPI bus are 6- or 8-bit.
It is not possible (according to ULPI 1.1 spec) to have more
than 8-bit addressing.
This patch should not cause regressions as all calls to
ulpi_read/write use either structure pointer (@ address 0) or integer
offsets cast to pointer - addresses requested are way below 8-bit range.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:20 +0000 (23:12 +0200)]
usb: ulpi: Fix viewport_addr type
viewport_addr is address of memory mapped ULPI viewport.
It is used only as argument to readl/writel later
causing compile warnings on 64-bit devices.
This fix changes its type to match pointer size.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:19 +0000 (23:12 +0200)]
Migrate CONFIG_ULPI* to Kconfig
Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it.
Also - add CONFIG_USB where necesarry - all boards use it,
but some are not defining it explicitly.
Affected boards:
colibri_t20, harmony, mcx, mt_ventoux, twister,
zynq_(picozed, zc702, zc706, zed, zybo)
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:18 +0000 (23:12 +0200)]
usb: ulpi: Add Kconfig options for ULPI
The following options can be now enabled via defconfig:
- CONFIG_USB_ULPI
- CONFIG_USB_ULPI_VIEWPORT
- CONFIG_USB_ULPI_VIEWPORT_OMAP
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:17 +0000 (23:12 +0200)]
ehci-hcd: Add init_after_reset
Some host controllers need addidional initialization after ehci_reset()
In non-dm implementation it is possible to use CONFIG_EHCI_HCD_INIT_AFTER_RESET.
This patch adds similar option to ehci drivers using dm.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:16 +0000 (23:12 +0200)]
mmc: Add support for Qualcomm SDHCI controller
Add support for SD/eMMC controller present on some Qualcomm Snapdragon
devices. This controller implements SDHCI 2.0 interface but requires
vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:15 +0000 (23:12 +0200)]
gpio: Add support for Qualcomm gpio controller
Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Mateusz Kulikowski [Thu, 31 Mar 2016 21:12:14 +0000 (23:12 +0200)]
serial: Add support for Qualcomm serial port
This driver works in "new" Data Mover UART mode, so
will be compatible with modern Qualcomm chips only.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Dan Murphy [Wed, 30 Mar 2016 17:58:37 +0000 (12:58 -0500)]
board: ti: DRA7: Add DP83867 TI phy for rev c
Enable the TI DP83867 Giga bit phy on the
dra7 rev c board. The rx and tx internal
delays are need for this board so the usage
of RGMII_ID is required.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Alexander Graf [Wed, 30 Mar 2016 14:38:29 +0000 (16:38 +0200)]
efi_loader: Always allocate the highest available address
Some EFI applications (grub2) expect that an allocation always returns
the highest available memory address for the given size.
Without this, we may run into situations where the initrd gets allocated
at a lower address than the kernel.
This patch fixes booting in such situations for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:27 +0000 (14:16 +0200)]
sniper: Change vendor name from lge to lg, matching devicetree vendor prefix
This moves the sniper board from the lge to lg, in order to match the devicetree
vendor prefix already defined in the kernel.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:26 +0000 (14:16 +0200)]
kc1: Proper reboot mode and boot reason validation
With the previous implementation, rebooting without registering a recognized
reboot mode would end up with U-Boot checking for a valid power-on reason, which
might result in the device turning off (e.g. with no USB cable attached and no
buttons pressed).
Since this approach is not viable (breaks reboot in most cases), the validity of
the reboot reason is checked (in turn, by checking that a warm reset happened,
as there is no magic) to detect a reboot and the 'o' char is recognized to
indicate that power-off is required. Still, that might be overridden by the
detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:25 +0000 (14:16 +0200)]
sniper: Proper reboot mode and boot reason validation
With the previous implementation, rebooting without registering a recognized
reboot mode (despite registering the magic) would end up with U-Boot checking
for a valid power-on reason, which might result in the device turning off (e.g.
with no USB cable attached and no buttons pressed).
This was designed to catch reboots that are actually intended to be power-off,
something that old Android kernels do, instead of properly turning the device
off using the TWL4030.
However, since this approach is not viable (breaks reboot in most cases), the
validity of the reboot mode magic is checked to detect a reboot and the 'o' char
is recognized to indicate that power-off is required. Still, that might be
overridden by the detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:24 +0000 (14:16 +0200)]
kc1: Add some sysboot and devicetree-related environment variables
This adds some environment variables for sysboot and devicetree.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:23 +0000 (14:16 +0200)]
kc1: Select libfdt to allow running devicetree-based kernels
Selecting CONFIG_OF_LIBFDT allows running recent mainline kernels.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:22 +0000 (14:16 +0200)]
kc1: Include explicit serial baudrate on bootargs
This makes the baudrate for the kernel command line explicit.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Paul Kocialkowski [Tue, 29 Mar 2016 12:16:21 +0000 (14:16 +0200)]
sniper: Include explicit serial baudrate on bootargs
This makes the baudrate for the kernel command line explicit.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Masahiro Yamada [Tue, 29 Mar 2016 10:51:57 +0000 (19:51 +0900)]
arm64: booti: add missing unmap_sysmem()
Make sure to call unmap_sysmem() for address allocated by map_sysmem()
before leaving the function; however this patch gives no impact on
the behavior because map_sysmem()/unmap_sysmem() does nothing except
on Sandbox. Sandbox never runs this code because "booti" is a command
for booting ARM64 kernel image.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Vitaly Andrianov [Mon, 28 Mar 2016 19:15:59 +0000 (15:15 -0400)]
configs: ti_armv7_keystone2: make SYS_TEXT_BASE configurable at build time
U-boot for general purpose KS2 devices is loaded to the beginning of the
internal memory (0x0c000000). Secure devices uses this memory and
CONFIG_SYS_TEXT_BASE has to be different for those devices.
This commit make this configurable at build time by giving
CONFIG_SYS_TEXT_BASE as a command line definition to make command.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Andreas Dannenberg [Mon, 28 Mar 2016 18:58:03 +0000 (13:58 -0500)]
arm: spl: Align default board_init_f comment with code
The default board_init_f() implementation performs a call to
board_init_r() as the last step of the sequence. Fix the comment
for this function to reflect the actual execution flow.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Robert P. J. Day [Mon, 28 Mar 2016 13:20:40 +0000 (09:20 -0400)]
post: Remove references to scrapped "netta" board.
Given that README.scrapyard shows scrapping of netta boards:
netta2 powerpc mpc8xx
c51c1c9a 2014-07-07
netta powerpc mpc8xx
c51c1c9a 2014-07-07
delete netta example from POST tests.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Peng Fan [Mon, 28 Mar 2016 09:26:27 +0000 (17:26 +0800)]
common: env_sf: Add exclamation mark
Add exclamation mark to the errmsg, when error and set_default_env.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Mario Schuknecht <mario.schuknecht@dresearch-fe.de>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Ravi Babu <ravibabu@ti.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 27 Mar 2016 18:48:36 +0000 (14:48 -0400)]
jffs2: Fix set but not used warning
We only use 'ofs' in jffs2_sum_scan_sumnode when debugging as it's part
of a dbg_summary call. Mark this as __maybe_unused.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 27 Mar 2016 18:06:11 +0000 (14:06 -0400)]
lib/physmem.c: Switch to __weak for arch_phys_memset
We normally use __weak rather than calling it out directly as an alias.
Update this function to the normal method.
Signed-off-by: Tom Rini <trini@konsulko.com>
Robert P. J. Day [Sun, 27 Mar 2016 14:18:55 +0000 (10:18 -0400)]
post: Delete unnecessary bitmask of POST_MANUAL from POST_ALWAYS
Since POST_ALWAYS is defined as:
#define POST_ALWAYS (POST_NORMAL | \
POST_SLOWTEST | \
POST_MANUAL | \
POST_POWERON )
there is no need to redundantly bitmask it with POST_MANUAL.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Robert P. J. Day [Sun, 27 Mar 2016 12:39:15 +0000 (08:39 -0400)]
post: Remove reference to deleted "lwmon" board from Makefile
POST support for sample lwmon board was removed in commit
e5d3078622.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>B
Ahmed Samir Khalil [Fri, 25 Mar 2016 12:13:17 +0000 (13:13 +0100)]
Common: SPL: spl_nand: Fixed debug correct NAND ECC type.
In case of #define DEBUG 1 (fordebugging SPL). A bug in
spl_nand_load_image() will be triggered, because it prints
using hw ecc regardless of soft ecc configurations and
initializations.
Signed-off-by: Ahmed Samir <engkhalil86@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:20 +0000 (22:15 -0600)]
rpi: BCM2837 and Raspberry Pi 3 32-bit support
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot for the Raspberry Pi 3.
>From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a
change in usage of the SoC UARTs. On all previous Pis, the PL011 was the
only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a
UART to connect to the SoC. By default, the PL011 is used for this purpose
since it has larger FIFOs than the other "mini" UART. However, this can
be configured via the VideoCore firmware's config.txt file. This patch
hard-codes use of the mini UART in the RPi 3 port. If your system uses the
PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot
port instead. A future change might determine which UART to use at
run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed
together.
The mini UART has some limitations. One externally visible issue in the
BCM2837 integration is that the UART divides the SoC's "core clock" to
generate the baud rate. The core clock is typically variable, and under
control of the VideoCore firmware for thermal management reasons. If the
VC FW does modify the core clock rate, UART communication will be
corrupted since the baud rate will vary from the expected value. This was
not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To
work around this, the VideoCore firmware can be told not to modify the SoC
core clock. However, the only way this can happen and be thermally safe is
to limit the core clock to a low/minimum frequency. This leaves
performance on the table for use-cases that don't care about a UART
console. Consequently, use of the mini UART console must be explicitly
requested by entering the following line into config.txt:
enable_uart=1
A recent version of the VC firmware is required to ensure that the mini
UART is fully and correctly initialized by the VC FW; at least
firmware.git
046effa13ebc "firmware: arm_loader: emmc clock depends on
core clock See: https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:19 +0000 (22:15 -0600)]
ARM: bcm2835: expand Kconfig target descriptions
This adds an explanation of which Raspberry Pi models each target option
supports.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:18 +0000 (22:15 -0600)]
rpi: add Raspberry Pi 3 board ID
This allows U-Boot to known the name of the board.
The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3
in 32-bit mode /if/ you have configured the firmware to use the PL011 UART
as the console UART (the default is the mini UART). This requires two
things:
a) config.txt should contain dtoverlay=pi3-miniuart-bt
b) You should run the following to tell the VC FW to process DT when
booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card
as the kernel image:
path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img
This works as of firmware.git commit
046effa13ebc "firmware: arm_loader:
emmc clock depends on core clock See:
https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:17 +0000 (22:15 -0600)]
rpi: use constant "unknown board" DT filename
To simplify support for new SoCs, just use a constant filename
for the unknown case. In practice this case shouldn't be hit anyway, so
the filename isn't relevant, and certainly doesn't need to differentiate
between SoCs. If a user has an as-yet-unknown board, they can override
this value in the environment anyway.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Fri, 25 Mar 2016 04:15:16 +0000 (22:15 -0600)]
ARM: bcm2835: move CONFIG_BCM283* to Kconfig
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Andreas Dannenberg [Wed, 23 Mar 2016 23:24:10 +0000 (18:24 -0500)]
doc: clarify openssl-based key and certificate generation process
Add some basic clarification that the dev.key file generated by OpenSSL
contains both the public and private key, and further highlight that
the certificate generated here contains the public key only.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Andreas Dannenberg [Wed, 23 Mar 2016 22:44:17 +0000 (17:44 -0500)]
doc: fix file extension for flattened image tree blob
Different sections in the document suggest flattened image tree blob
files have a file name extension of .itb. Fix the list of file extensions
to reflect that.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Fabio Estevam [Wed, 23 Mar 2016 15:46:12 +0000 (12:46 -0300)]
README: Specify the full path for README.displaying-bmps
It is clearer to specify the full path to access the
doc/README.displaying-bmps file.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Nishanth Menon [Wed, 23 Mar 2016 15:14:19 +0000 (10:14 -0500)]
ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K | K2L | K2E | K2G
-------+-----------+-----------+-----------+---------
0 | C66x 0 | C66x 0 | C66x 0 | C66x 0
1 | C66x 1 | C66x 1 | Reserved | ARM
2 | C66x 2 | C66x 2 | Reserved | ICSS0
3 | C66x 3 | C66x 3 | Reserved | ICSS1
4 | C66x 4 | Reserved | Reserved | NETCP
5 | C66x 5 | Reserved | Reserved | CPIE
6 | C66x 6 | Reserved | Reserved | USB
7 | C66x 7 | Reserved | Reserved | Reserved
8 | ARM | ARM | ARM | MLB
9 | NetCP | NetCP | NetCP | PMMC
10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS
11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC
12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13 | Reserved | Reserved | PCIe_1 | Reserved
14 | HyperLink | PCIe_1 | HyperLink | Reserved
15 | Reserved | Reserved | TSIP | Reserved
-------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.
Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).
By marking these segments as shared, we also ensure SoC wide coherency
is enabled.
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon [Wed, 23 Mar 2016 15:14:18 +0000 (10:14 -0500)]
ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs.
As the first step to ensure complete SoC wide coherency setup, lets
refactor the macros to remove the #if-deffery around the code which
obfuscates which IDs are actually enabled for which SoC.
As a result of this change the PCIe configuration is moved after the
msmc configuration is complete, but that should ideally have no
functional impact.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Wed, 23 Mar 2016 04:28:16 +0000 (22:28 -0600)]
smsc95xx: fix operation on 64-bit systems
smsc95xx_read_reg() should calculate sizeof(*data) not sizeof(data) since
data is a pointer, and the value pointed at is being transferred over USB,
not the value of the pointer. This fixes operation of the driver in 64-bit
builds, such as the Raspberry Pi 3.
Reported-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Sat, 19 Mar 2016 08:18:38 +0000 (02:18 -0600)]
Drop command-processing code when CONFIG_CMDLINE is disabled
Command parsing and processing code is not needed when the command line is
disabled. Remove this code in that case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Rob Herring [Thu, 17 Mar 2016 16:21:23 +0000 (17:21 +0100)]
fastboot: allow retrieving fastboot variables from env
Some boards need to expose device specific variable through fastboot
(to adpat the flashing script depending on hardware revision for
example).
Provide a way to expose custom fastboot variables. Note that all
variables meant to be exposed through fastboot should be be prefixed
with 'fastboot.', the variable should not exceed 32 bytes (including
the prefix and the trailing '\0') and the variable content should
fit in the response buffer (60 bytes excluding the 'OKAY' prefix and
the trailing '\0').
Signed-off-by: Rob Herring <rob.herring@linaro.org>
[Boris Brezillon: add a commit message]
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Steve Rae <srae@broadcom.com>
Tom Rini [Wed, 16 Mar 2016 23:55:55 +0000 (19:55 -0400)]
arm: clang: Update support slightly
- Move most of the flags required into LLVM_RELFLAGS to test at build
time instead of requiring them to be passed in.
- Update doc/README.clang to reflect this
- Switch to rpi_2 as the example as it's closer to working out of the
box than rpi is.
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 1 Apr 2016 12:17:55 +0000 (08:17 -0400)]
Merge branch 'master' of git.denx.de/u-boot-sunxi
Alexander Graf [Wed, 30 Mar 2016 15:53:56 +0000 (17:53 +0200)]
sunxi: Reserve ATF memory space on A64
On the A64 we usually boot with ATF running in EL3. ATF as it is available
today resides in the first 16MB of RAM. So we should make sure we reserve
that space in our memory maps.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Siarhei Siamashka [Tue, 29 Mar 2016 15:29:11 +0000 (17:29 +0200)]
sunxi: Add Pine64+ support
The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of
running AArch64 code and thus is the first of its kind for the sunxi target.
This patch adds a defconfig and device tree chunks for it.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: Change patch description]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Siarhei Siamashka [Tue, 29 Mar 2016 15:29:10 +0000 (17:29 +0200)]
sunxi: Add support for Allwinner A64 SoCs
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.
Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Alexander Graf [Tue, 29 Mar 2016 15:29:09 +0000 (17:29 +0200)]
sunxi: Explicitly cast u32 pointer conversions
Some parts of the sunxi code cast explicitly between u32 values and pointers.
This is not a problem in practice, because all 64bit SoCs today only use the
lower 32 bits for their phyical address space. But we need to make sure that
the compiler is sure this is not an accident as well.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Alexander Graf [Tue, 29 Mar 2016 15:29:07 +0000 (17:29 +0200)]
sunxi: Depend SPL configs on SUPPORT_SPL
We currently depend SPL config options on specific machine types which doesn't
scale. Fortunately there's already a kconfig variable that tells us whether we
want to build SPL code at all, so just depend them on this.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Alexander Graf [Tue, 29 Mar 2016 15:29:06 +0000 (17:29 +0200)]
sunxi: Move cpu independent code to mach directory
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.
Move all files that are not really tied to armv7 into a new mach-sunxi
directory.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:27:02 +0000 (00:27 +0800)]
sunxi: Enable USB nodes for H8Homlet v2
This provides the minimal changes to the H8Homlet v2 dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:27:01 +0000 (00:27 +0800)]
sunxi: Enable USB on Cubietruck Plus
This provides the minimal changes to the Cubietruck Plus dts to enable USB
in U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:27:00 +0000 (00:27 +0800)]
sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi
This provides the minimal changes to the A83T dtsi to enable USB in
U-boot. It is not what will be submitted to the kernel.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:59 +0000 (00:26 +0800)]
sunxi: Cubietruck Plus: Enable USB Kconfig options in defconfig
The Cubietruck Plus uses all 3 USB controllers:
- USB OTG functions are provided by the musb USB OTG controller
- Onboard SATA is provied by a USB-SATA bridge connected to USB1
- The USB host ports on the board are provided by an HSIC USB hub
FLDO1 is set to 1.2V for HSIC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:58 +0000 (00:26 +0800)]
sunxi: h8_homlet_v2: Enable USB Kconfig options in defconfig
The h8_homlet_v2 has 2 USB host ports, one connected to the OTG
controller, one connected to the EHCI/OHCI pair.
Also provide the card detect pin for MMC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Masahiro Yamada [Wed, 30 Mar 2016 11:45:19 +0000 (20:45 +0900)]
ARM: uniphier: remove CONFIG_ARP_TIMEOUT define
I no longer see the problem claimed in the comment block. Rather,
the 0.5 msec timeout seems too short for some TFTP servers.
Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 30 Mar 2016 11:17:42 +0000 (20:17 +0900)]
cosmetic: Fix typos "privide"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 30 Mar 2016 11:17:02 +0000 (20:17 +0900)]
ARM: uniphier: rename function names ph1_* to uniphier_*
Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 30 Mar 2016 01:53:15 +0000 (10:53 +0900)]
ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 30 Mar 2016 01:52:49 +0000 (10:52 +0900)]
ARM: uniphier: enable eMMC on PH1-sLD3 reference board
On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
Both devices can be enabled at the same time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 29 Mar 2016 11:18:45 +0000 (20:18 +0900)]
ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64
Currently, these functions assume #address-cells and #size-cells are
both one. Fix them to support 64bit DTB.
Also, I am fixing a buffer overrun bug while I am here. The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of
iteration in the loop should be limited by that CONFIG.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Tue, 29 Mar 2016 11:12:22 +0000 (20:12 +0900)]
ARM: uniphier: drop unneeded defines related to legacy serial driver
These defined were used for pre-DM ns16550 serial driver. They are
unneeded because UniPhier SoCs now use DM serial.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Mon, 28 Mar 2016 12:41:15 +0000 (21:41 +0900)]
ARM: dts: uniphier: add NAND pinmux node
This will be used to set up pin-muxing for the NAND controller.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Mon, 28 Mar 2016 12:39:17 +0000 (21:39 +0900)]
ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20
Since no clock driver is implemented for peripherals in U-Boot yet,
this property is needed for the serial driver to set up the divisor
register.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:47 +0000 (22:32 +0900)]
pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driver
The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20
(as far as used in boot-loader), so this commit makes the driver
shared between the two SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:46 +0000 (22:32 +0900)]
pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver
Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:45 +0000 (22:32 +0900)]
pinctrl: uniphier: support per-pin input enable for new SoCs
Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin. (While, existing ones only support it
per pin-group.) This commit prepares the core part for that.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:44 +0000 (22:32 +0900)]
pinctrl: uniphier: introduce capability flag
The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens
because pinctrl drivers include really SoC-specific stuff.
This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones. Having flags would be better than
adding new members every time a new SoC-specific capability comes up.
At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:43 +0000 (22:32 +0900)]
pinctrl: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:42 +0000 (22:32 +0900)]
mmc: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:41 +0000 (22:32 +0900)]
gpio: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:40 +0000 (22:32 +0900)]
i2c: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:39 +0000 (22:32 +0900)]
clk: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:32:38 +0000 (22:32 +0900)]
serial: uniphier: use devm_get_addr() to get base address
Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties. (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:23:36 +0000 (22:23 +0900)]
ARM: uniphier: add sramupdate command
This command would be useful to update U-Boot images in SRAM.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 24 Mar 2016 13:22:23 +0000 (22:22 +0900)]
ARM: uniphier: make u-boot-with-spl.bin really available
Commit
d085ecd61b99 ("ARM: uniphier: switch to raw U-Boot image")
claimed that u-boot-with-spl.bin would be useful in its commit log,
but it was not available because the commit missed to define
CONFIG_SPL_MAX_SIZE. Without it, CONFIG_SPL_PAD_TO is not defined
either (see include/config_fallbacks.h). So, the SPL image is not
padded correctly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Graham Moore [Thu, 24 Mar 2016 13:14:35 +0000 (22:14 +0900)]
mtd: nand: denali: max_banks calculation changed in revision 5.1
Read Denali hardware revision number and use it to
calculate max_banks, The encoding of max_banks changed
in Denali revision 5.1.
[ Linux commit :
271707b1d817f5104e02b2bd1bab43f0c8759418 ]
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
[Brian: parentheses around macro arg]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[Masahiro: import from Linux and adjust ioread32() to readl() ]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:54 +0000 (00:26 +0800)]
sunxi: ohci: Add A83T compatible
We have a separate compatible for almost each SoC. Add one for the A83T.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:53 +0000 (00:26 +0800)]
sunxi: ehci: Add A83T compatible
We have a separate compatible for almost each SoC. Add one for the A83T.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Chen-Yu Tsai [Tue, 29 Mar 2016 16:26:52 +0000 (00:26 +0800)]
sunxi: clk: Fix USB PHY clock macros for A83T
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks.
Also there is only 1 OHCI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>