agx: Fix missing #include

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20569>

asahi: Implement ARB_texture_mirror_clamp_to_edge

Guessing the enum value, passes texwrap piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20560>

asahi: Implement GL_CLAMP natively

Turns out there's a hardware mode for this. Apple's GL driver uses this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20560>

ci/zink+anv: remove dEQP-GLES31.functional.layout_binding.ubo.*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: use the null surface with unused push descriptor binding table entries

Some binding table entries have been identify as unused in the shaders
by the push constant analysis pass. We can just put the null entry in
there.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b49b18f0b7 ("anv: reduce BT emissions & surface state writes with push descriptors")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: return properly typed value for no ubo promoted

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: check that push range actually match binding considered

We can't just check the load_ubo range is contained in the push entry,
we also need to check that the push entry set/binding matches the
load_ubo set/binding.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

anv: don't nullify entries

We'll use those to fill the push constant addresses, so we can't have
them turned to null.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20555>

iris: let isl set tiling mode for external resources

Patch sets memory object external format (which is otherwise
PIPE_FORMAT_NONE for memory objects) before main surface gets
configured. With this we can add a check that when dealing
with external resource that has no modifier set, we let isl
figure out the tiling mode.

Fixes memobj tests on DG2:
   piglit.spec.ext_external_objects.vk-image-display-muliple-textures
   piglit.spec.ext_external_objects.vk-image-display-overwrite
   piglit.spec.ext_external_objects.vk-depth-display
   piglit.spec.ext_external_objects.vk-image-display
   piglit.spec.ext_external_objects.vk-stencil-display

v2: add assert and comment on tiling decision (Ken)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7684
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20473>

radv/rt: use a smaller value to enable scratch

The scratch allocation alignment on GFX11 is small enough that this should
help. Would be nice to someday remove this hack completely though.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>

aco: align scratch size during assembly

This lets us use less scratch if both VGPR spilling and scratch intrinsics
are used.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>

aco/gfx11: reduce scratch allocation alignment

fossil-db (gfx1100):
Totals from 112 (0.08% of 134574) affected shaders:
Scratch: 1513472 -> 1455360 (-3.84%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20534>

vc4: Fix running process_mux_deps on irrelevant type of instructions

Only ALU and ALU Small Imm instructions have input mux.

Signed-off-by: Qiu Wenbo <qiuwenbo@kylinos.com.cn>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20581>

vc4: Fix RADDR_A field extraction of branch instruction

Signed-off-by: Qiu Wenbo <qiuwenbo@kylinos.com.cn>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20581>

zink: add a bunch of asserts for starting dynamic render

try to avoid any race condition bugs triggering later when they're
harder to catch

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: re-clamp dynamic render area when doing swapchain fixups

this may catch another corner case if a late fixup changes fb size

fixes (lavapipe):
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.clear_render

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: catch a potential corner case with dynamic render and swapchain updates

zink_prep_fb_attachment() calls acquire internally, which means it's theoretically
possible that fixups are required very late in this function

never seen it happen, but who knows

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: split out swapchain render update fixups into separate function

this needs to be more granular for corner cases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: protect against invalid scissored renderpass clears

if the clear region is oob, this is illegal and may crash some drivers

fixes (lavapipe):
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.buffer_age_clear_render
dEQP-EGL.functional.swap_buffers_with_damage.resize_before_swap.buffer_age_render_clear

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

zink: only update framebuffer object during swapchain update if framebuffer exists

otherwise this might be randomly creating an unused framebuffer for dynamic render

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20584>

intel/eu/validate: Check predication and cmod for SEL, CMP, and CMPN

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/eu/validate: Add validation for csel

v2: Also check the condition modifier. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/eu/validate: Add validation for bfi2

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/eu/validate: More validation for logic ops

v2: Use number of source to condition validating src1 instead of using
the opcode. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/compiler: Assert that ARF used is the accumulator

v2: Move the new check to be with similar existing checks. Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/compiler: Validate 3-source instruction source strides

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

intel/compiler: Validate 3-source instruction sources have same base type

This can't be checked in EU validation because the bits to describe the
base type of the individual sources no longer exist.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20527>

aco: Mark more instructions as 16bit on GFX10.

p_cvt_f16_f32_rtne will be lowered to v_cvt_f16_f32 and we already know that
preserves the high bits.

I tested the others on GFX1036.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20574>

aco: use s_delay_alu skip field

fossil-db (gfx1100):
Totals from 130066 (96.65% of 134574) affected shaders:
Instrs: 80208817 -> 71420648 (-10.96%)
CodeSize: 403523036 -> 368370360 (-8.71%)
Latency: 658064779 -> 657935384 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 87698268 -> 87693326 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>

aco: add more dependency instructions under waitcnt class

This makes these instructions free when considering pipeline statistics
and s_delay_alu insertion.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>

aco: improve parse_delay_alu

Use gpr_map to determine how many cycles each dependency of the
s_delay_alu needs. This information helps the pass avoid further
s_delay_alu instructions.

fossil-db (gfx1100):
Totals from 13097 (9.73% of 134574) affected shaders:
Instrs: 30711894 -> 30702692 (-0.03%)
CodeSize: 153462500 -> 153425692 (-0.02%)
Latency: 372758612 -> 372741922 (-0.00%)
InvThroughput: 50164111 -> 50160717 (-0.01%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20512>

radv/winsys: fill real info for CHIP_GFX1100

From my AMD Radeon 7900 XT.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20476>

radv: configure VGT_TF_PARAM directly from the command buffer

The driver re-emits the tessellation domain origin state when a new
pipeline with tessellation is bound, so this can be moved there.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>

radv: fix re-emitting tessellation domain origin when it's dynamic

The winding order can be different between pipelines.

Fixes new dEQP-VK.pipeline.pipeline_library.dynamic_control_points.change_*_winding.

Fixes: f22290949d3 ("radv: add support for dynamic tessellation domain origin")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20486>

util/00-mesa-defaults: add Limbo workaround

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7976
Cc: mesa-stable
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20548>

anv: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+

This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

As no ANV_PIPE_INVALIDATE_BITS is set as parameter of
anv_add_pending_pipe_bits(),
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one
PIPELINE_CONTROL.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>

iris: Update PIPELINE_CONTROL flush when switching pipeline mode in TGL+

This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer
and also it have different requirements of flush, so here doing
this two changes at the same time.

BSpec: 44505
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501>

hud: extract float printf modifer selection logic to helper

And use it when printing to a file from hud_graph_add_value.

This turns:
  fps: 59.972473
Into:
  fps: 59.97

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

dri: get rid of LIBGL_SHOW_FPS

The same functionnality can be achieved using GALLIUM_HUD=stdout,fps (and for
now a fallback is doing this if LIBGL_SHOW_FPS=1 is used).

This removes one entry from the vtable and simplify dri3_handle_present_event.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

hud,dri: emulate LIBGL_SHOW_FPS using hud

LIBGL_SHOW_FPS=1 is now almost equivalent to using:

   GALLIUM_HUD=stdout,fps
   GALLIUM_HUD_VISIBLE=false
   GALLIUM_HUD_PERIOD=$LIBGL_SHOW_FPS

so we can drop LIBGL_SHOW_FPS handling in dri and move it to hud.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

hud: add "stdout" option to print values to console

Values gathered by the hud context will be printed to stdout,
prefixed by their name.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

hud: check GALLIUM_HUD_DUMP_DIR value only once

Minor cleanup but will allow another change in the next commit.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20494>

util/disk_cache: Support combined foz ro and non-foz rw caches

Mesa utilizes only one type of cache at a time. This patch enables support
for combined reading from read-only Fossilize cache + non-foz read-write
caches.

From now on, a non-foz read-write caches will first try to retrieve data
from a read-only foz cache if new MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ
environment variable is set to true, otherwise the caching behaviour is
unchanged. The new flag has no effect when MESA_DISK_CACHE_SINGLE_FILE=1,
i.e. when the single-file foz cache is used.

This change allows us to ship a prebuilt RO caches for a certain
applications, while the rest of applications will benefit from the
regular RW caching that supports cache-size limitation. This feature
will be used by ChromeOS.

Usage example #1:

MESA_DISK_CACHE_DATABASE=0
MESA_DISK_CACHE_SINGLE_FILE=0
MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ=1
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS=rocache1,rocache2

Usage example #2:

MESA_DISK_CACHE_DATABASE=1
MESA_DISK_CACHE_SINGLE_FILE=0
MESA_DISK_CACHE_COMBINE_RW_WITH_RO_FOZ=1
MESA_DISK_CACHE_READ_ONLY_FOZ_DBS=rocache1,rocache2

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18551>

util/disk_cache: Store environment variable values in disk_cache struct

Store values of all environment variables related to disk caching within
struct disk_cache. This makes code cleaner and also will allow us to
combine read-only single-file cache with read-write caches.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18551>

util/fossilize_db: Fix resource leaks in foz_prepare() error paths

The foz_prepare() doesn't perform cleanup on failure and then foz_destroy()
is never invoked for the foz_db, causing minor memory and FD leaks. Add the
cleanup to foz_prepare() error code paths. Make foz_destroy() to clear the
foz_db struct for consistency, right now the destroying is invoked only once,
but Mesa cache error code paths aren't trivial and may change in the future.

Suggested-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18551>

zink: fix disappearing smooth lines after workaround

The passthrough geometery shader was using points for smooth lines.
This meant the shader would always statically get 1 vertex and never emit a line.

Fixes: 80285db9efe ("zink: lower smooth-lines if not supported")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20582>

driconf: add a workaround for plasmashell freezing

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7624

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dan Johansen <strit@manjaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20472>

intel/fs: only avoid SIMD32 if strictly inferior in throughput

This enabled SIMD32 in blorp shaders and seems to be give a small FPS
bump when using a DG2 GPU as secondary (requires copies to linear
buffers to exchange with main GPU).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19341>

radv: remove unused radv_is_raster_enabled()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

radv: initialize blend state after compiling shaders

This function used to compute part of the graphics key but everything
has been moved.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

radv: replace blend_enable_4bit by radv_pipeline_is_blend_enabled()

Same logic, though this workaround shouldn't be determined from the
pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

radv: determine DISABLE_DUAL_QUAD directly from the command buffer

With dynamic color blend equations, dual-src blending will be
determined from the dynamic state, better to move it there now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

radv: simplify uses of color_write_mask/color_blend_enable

The common Vulkan code already sets them when they are dynamic, so this
was redundant.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

radv: adjust CB_SHADER_MASK right after SPI_SHADER_COL_FORMAT is compacted

This is a cleanup.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

radv: remove unused parameter in radv_init_multisample_state()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20517>

spirv2dxil: Fix memory leak on error path.

Fix resource leak reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable file_contents going out of scope leaks the storage it points to.

Fixes: 531d17c3342 ("spirv2dxil: Support linking multiple shaders")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20576>

ci: Start weston with Xwayland

This can be used instead of HWCI_START_XORG to provide X in CI.
It will only be actually used if HWCI_START_XORG is not set in the same
job.
It is particularly useful as weston has the explicit headless backend
which is more straightforward to use in the headless systems in CI.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20393>

virgl: Use virgl host side shader stage IDs when reading caps

The ordering of enum pipe_shader_type changed, but not all locations where
the host uses the original ordering were changed to translate to the new
ordering, namely reading the shader caps was not fixed up so do this now.

v2: - inline virgl_shader_stage_convert (Corentin)
    - encapuslate use of host shader stage when reading array elements
      of host caps

Fixes: a26543f6368fed1604cfde7fffce2024e9d8abab
   gallium: reorder the shader stage enum to match Mesa

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8023

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20544>

ci/virgl: cover more glx@glx-copy-sub-buffer flakes

Generally, where this test doesn't fail, there it flakes.

Cover all variants.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7753

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20556>

Revert "ci/venus: disable for now"

This reverts commit 22ab226396ab0b5db5a1f0f903e409ec89bb6a48.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20554>

ci: Bump crosvm and virglrenderer versions

Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20554>

isaspec: Fix bitmask conversions when isa.bitsize < 64

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20541>

etnaviv: add cleared surfaces to context flush set when necessary

A RS/BLT clear might only clear the TS buffer, so the cleared resources
need to be added to the context flush set when they aren't explicitly
flushed in order to make the effect of the clear visible in the resource
on context flush.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20012>

etnaviv: split adding resource to context flush set into own function

It is needed in a few more places, so split it into a separate
function to make it reusable.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20012>

ci_run_n_monitor.py: automatically retry on transient errors

This morning a GitLab update was deployed, leading to a few moments
where the API returned an error.

python-gitlab is actually able to handle a number of those and retry
automatically, so let's enable that:
https://python-gitlab.readthedocs.io/en/stable/api-usage-advanced.html#transient-errors

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20094>

zink: Add an assert for not seeing any more MSAA image-to-buffer copies.

Now that transfer_map gets MSAA handled by the helper, we shouldn't have
to worry about this any more.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

zink: Have u_transfer_helper resolve MSAA surfaces when mapping.

This fixes all the dEQP winsys multisampling failures (like
dEQP-GLES3.functional.multisample.default_framebuffer.depth) I've found so
far.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

u_transfer_helper: Merge in-place and split z/s interleaved map handling.

The paths were mostly the same, except that in-place was missing the
appropriate layering for MSAA helper re-mapping.  We can instead share
more code, making the differences between the interleave packing clear,
and have the MSAA resolve blit happen once before we do the split
mappings.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

u_transfer_helper: Use common code for interleaved unmap.

The function was static and only used from this caller, and the only
difference was that the interleaved case didn't handle trans->ss (which
will always be unset for an interleaved mapping since interleaving splits
the underlying map of the MSAA resource into trans->trans and
trans->trans2).

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

u_transfer_helpre: Drop !interleave handling from the interleave code.

It's only called when need_interleave_path(), and they're static functions
in this file since !17959.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

docs/gallium: Explain that MSAA transfer_map must be supported.

It's called this way in various drivers, and is an established part of the
transfer_map interface.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

ci: Fix VK driver setup for HWCI_START_*.

Review feedback requested a change that was incorrect, causing Xorg to
start to fail, but I forgot to retest the manual -full jobs that relied on
it.

Fixes: 99a6f2a1864f ("ci: Set the path to the VK drivers during HWCI_START_XORG/WESTON.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20523>

anv,hasvk: move the null check into the function call and drop null check copies

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv: Drop useless FIXME

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv,hasvk: drop unused function

align_i32 is not used anywhere

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv,hasvk: migrate to ROUND_DOWN_TO from util

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv,hasvk: migrate to u_minify from util

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv: migrate anv_minify to use u_minify

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv,hasvk: migrate to align64 from util

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv,hasvk: migrate align32 to the right functions from util

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv,hasvk: Use the inbuilt macro from src/util for clamping int64_t

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

anv: constify variables and use early returns

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20104>

ci/linker: update mold to 1.9

Bump needed for s390x fix with `-gsplit-dwarf` and `--gdb-index`.
See the https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20435
for more details.

I also switched from make to cmake (make is unsupported now).

Additionally disabled build testing and enabled LTO build for Mold.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20546>

aco/gfx11: update s_code_end padding

Match ac_rtld_open().

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Cc: 22.3 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20536>

meson: add missing dependency

Now that renderonly.h includes util/simple_mtx.h, which itself includes
valgrind.h, dep_valgrind is required by any module that includes
renderonly.h.

    In file included from ../src/gallium/auxiliary/renderonly/renderonly.h:33,
                     from ../src/gallium/winsys/kmsro/drm/kmsro_drm_winsys.c:39:
    ../src/util/simple_mtx.h:34:12: fatal error: valgrind.h: No such file or directory
       34 | #  include <valgrind.h>
          |            ^~~~~~~~~~~~
    compilation terminated.

dep_valgrind is part of idep_mesautil, which should be used instead of
copying the list of deps for each util header included (which would
have to be updated every time a util header changes its own includes),
so let's add idep_mesautil everywhere that includes renderonly.h.

Fixes: ad4d7ca8332488be8a75 ("kmsro: Fix renderonly_scanout BO aliasing")
Tested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20530>

ci: enable wayland platform in more debian builds

CI has recently gained coverage of wayland platform in EGL tests, but
some CI mesa builds such as arm builds currently don't enable the
wayland platform.
Enable it so test applications can properly initialize EGL with a
wayland platform.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20480>

radv/ci: run Zink testing on VanGogh

Running zink testing on RDNA2 hardware has been on our TODO list for
a while. While we don't have enough NAVI21 to test everything, we could
make use of the VanGogh APUs to do our Zink testing.

We will enable that job for pre-merge after a week or so of testing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20006>

zink/ci: rename zink-radv-* to zink-radv-navi10-*

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20006>

radv/ci: merge all the zink jobs into a single one

Since GL CTS, GLES CTS, and Piglit executions are very fast compared
to the machine setup time, it makes sense to combine them into one
boot.

The execution will run until the first test suite fails, or we are
done with the execution.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20006>

ci/venus: disable for now

It flakes too much. Until it gets sorted out, we disable it.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20547>

venus: Avoid to copy the descriptor sets when it is not required

Allows to reduce the amount of allocations when the VkWriteDescriptorSet is
already sanitized.

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20095>

radv: fix returning VK_PIPELINE_COMPILE_REQUIRED from library

When VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED is set by
the application, the driver should return VK_COMPILE_REQUIRED but this
was broken for GPL (it returned VK_SUCCESS instead). Also, objects
shouldn't be destroyed when creating the library failed because it's
already handled in radv_graphics_lib_pipeline_create().

Cc: 22.3 mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7512
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20532>

radeonsi: Fix amdgpu-color-export with prologues

Polygon stippling is handled in the prologue, amdgpu-color-export needs
to be set for that.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8010
Fixes: 1825ad134b17 ("radeonsi,radv/llvm: fix amdgpu-color/depth-export with epilogs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20531>

radv: stop dirtying INDEX_BUFFER for non-indexed draws

radv_emit_index_buffer() used to emit VGT_INDEX_TYPE but since I
implemented the DISABLE_INSTANCE_PACKING workaround, it's emitted
in radv_emit_draw_registers().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20522>

radv: flush push descriptors at bind time

This doesn't need to be flushed at draw time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20522>

radv: remove set but unused radv_cmd_state::index_{buffer,offset}

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20522>

radv: remove unused pipeline parameter from radv_emit_binning_state()

It's no longer needed because everything is dynamic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20522>

radv: remove enabling out-of-order rasterization internally

This was added ~4 years ago for very little performance improvements
(likely < 1%) and this is only supported on GFX8 and GFX9.

Since, the number of dynamic states increased and this is likely
disabled most of the time, and given the maintainability cost, it looks
like it's time to remove it completely.

Applications can still enable it with VK_AMD_rasterization_order.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20514>

isaspec: Give decode.c/h more descriptive names

Because these are being included across subdir boundaries, the name
"decode" is potentially pretty overloaded.  Instead, prefix them with
"isaspec_".  Also, since they're both weird includes now and not really
complete files in their own right, give them a descriptive suffix.

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20525>

isaspec: Stop depending on glue headers and out-of-folder C files

The way the isaspec decoder used to work was that it would generate a
header and a C file, each with ISA-specific stuff in it. Then that would
get built together with a stand-alone decode.c file which lives in the
isaspec folder, not the driver's folder.  In order for decode.c to find
the ISA-specific headers, it would also generate a glue header which had
to be named isaspec-isa.h.  This effectively meant that you can't have
multiple isaspec definitions in the same folder.

To solve this, we make do it the other way around and make the generated
header and C files include the stand-alone files.  This is a bit awkward
because it means including a C file from another C file but it's better
for the build system.

Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20525>