Sviatoslav Peleshko [Thu, 9 Feb 2023 15:56:32 +0000 (17:56 +0200)]
anv: Handle VkAccelerationStructureBuildRangeInfoKHR::transformOffset
Previously it was not actually handled. This meant that all geometries
with the same transform buffer were using the same (first) transformation
matrix.
Fixes:
f3ddfd81 ("anv: Build BVHs on the GPU with GRL")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7575
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21227>
Marcin Ślusarz [Wed, 25 Jan 2023 14:06:23 +0000 (15:06 +0100)]
intel/compiler/mesh: use U888X packed index format
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20910>
Danylo Piliaiev [Tue, 7 Feb 2023 15:52:53 +0000 (16:52 +0100)]
turnip: Disable draw states after dyn renderpass in all cases
Draw states were not disabled after a dynamic renderpass which
spans several command buffers, the next renderpass if started in
the same command buffer wouldn't emit the full draw state,
since TU_CMD_DIRTY_DRAW_STATE was not set by previous renderpass.
The issue could be observed when corrupting all regs at cmdbuf start in:
dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed7_geometry
Fixes:
cb0f414b2aed88f48b2593dad833844be2f5f42b
("tu: Add support for suspending and resuming renderpasses")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
Danylo Piliaiev [Mon, 6 Feb 2023 19:38:41 +0000 (20:38 +0100)]
turnip: Ensure that there is no renderpass rotation in binning
It appears that A6XX_GRAS_SC_CNTL::rotation applies to the binning,
so we should ensure there is no unexpected rotations and apply with
A6XX_GRAS_SC_CNTL during the binning pass.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
Danylo Piliaiev [Mon, 6 Feb 2023 19:36:48 +0000 (20:36 +0100)]
freedreno: Document A6XX_GRAS_SC_CNTL::rotation field
Likely used for VK_QCOM_render_pass_transform.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
Danylo Piliaiev [Mon, 6 Feb 2023 13:56:35 +0000 (14:56 +0100)]
tu: Prevent using stale value of GRAS_SC_CNTL in sysmem clear
cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
Danylo Piliaiev [Fri, 3 Feb 2023 16:02:52 +0000 (17:02 +0100)]
tu: Prevent using stale value of RB_UNKNOWN_88D0 on BLIT
Fixes:
def56b531c86f529bc32d1834ccb479457717db7
("tu: Support GMEM with layered rendering and multiview")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
Amber [Tue, 7 Feb 2023 10:53:26 +0000 (11:53 +0100)]
freedreno: use blendcoherent to set FLUSH_PER_OVERLAP
FLUSH_PER_OVERLAP is only necessary for gmem if coherent blending is
enabled.
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
Amber [Tue, 7 Feb 2023 10:53:01 +0000 (11:53 +0100)]
gallium: make BlendCoherent usable from gallium drivers
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
Amber [Mon, 6 Feb 2023 13:39:19 +0000 (14:39 +0100)]
freedreno: use A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE with fb readback
fixes:
dEQP-GLES31.functional.blend_equation_advanced.msaa.*
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
Mike Blumenkrantz [Fri, 10 Feb 2023 13:20:01 +0000 (08:20 -0500)]
zink: add newlines to some debug printfs
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21239>
Väinö Mäkelä [Thu, 8 Dec 2022 15:59:05 +0000 (17:59 +0200)]
hasvk: Tell spirv_to_nir float controls are always supported
This gets rid of the "Unsupported SPIR-V capability" warnings when
compiling shaders using float controls on gfx7.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
Väinö Mäkelä [Thu, 8 Dec 2022 15:53:03 +0000 (17:53 +0200)]
hasvk: Don't claim shaderDenormPreserveFloat32 on gfx7
From the Haswell PRM Vol. 7, "IEEE Floating Point Mode":
"Single precision (F, Float) denorms are flushed to sign-preserved
zero on input and output of any floating-point mathematical
operation."
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
Väinö Mäkelä [Thu, 8 Dec 2022 15:52:04 +0000 (17:52 +0200)]
intel/vec4: Don't optimize multiply by 1.0 away
The SPIR-V compiler's implementation of tanh generates a multiply by 1.0
to flush denorms to zero.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
Väinö Mäkelä [Thu, 8 Dec 2022 15:41:32 +0000 (17:41 +0200)]
intel/vec4: Set the rounding mode
The rounding mode only needs to be set once, because 16-bit floats or
preserving denorms aren't supported for the platforms where vec4 is
used.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
Eric Engestrom [Wed, 18 Jan 2023 18:50:39 +0000 (18:50 +0000)]
panfrost: drop no-longer-needed libglsl
Fixes:
551c2aadd4d85e922aa6 ("pan/bi: Remove standalone compiler")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21240>
Samuel Pitoiset [Thu, 2 Feb 2023 15:52:15 +0000 (16:52 +0100)]
radv: implement graphics shaders relocation for a RGP workaround
RGP requires shaders to be uploaded consecutively inside the same
buffer object. Otherwise, either it makes the driver generating
huge traces (ie. in GiB) or it fails to load traces at all. Hopefully,
this will be improved soon when AMDGPU drivers will have GPL support.
To workaround this, the driver relocates graphics shaders in the same
buffer object when a pipeline is created. Then at draw time, it
overwrites SPI_SHADER_PGM_xxx registers to make sure SQTT can match
between emitted and exported shaders. It's a bit suboptimal because
graphics shaders are uploaded twice but it's the best solution I found.
This will allow to implement GPL caching without breaking capturing
shaders with RGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21078>
Samuel Pitoiset [Wed, 12 Oct 2022 12:26:39 +0000 (14:26 +0200)]
radv: restore uploading shaders individually instead of consecutively
The shaders were uploaded consecutively to fit a RGP constraint but
this was more like a workaround. This upload path doesn't work well for
graphics pipeline library and it was the main blocker for GPL caching.
This commit breaks capturing shaders with RGP if the offset between
shaders is too big. Next commit should fix it by using shaders reloc.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21078>
Georg Lehmann [Fri, 3 Feb 2023 13:46:29 +0000 (14:46 +0100)]
aco: remove stale TODOs about v_interp opsel
These are already handled correctly according to the ISA docs.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21096>
Philipp Zabel [Wed, 8 Feb 2023 12:36:54 +0000 (13:36 +0100)]
vulkan/wsi/wayland: fix acquire_next_image to report timeouts properly
The Vulkan Specification states about possible return values from
vkAcquireNextImageKHR:
* VK_NOT_READY is returned if timeout is zero and no image was
available.
* VK_TIMEOUT is returned if timeout is greater than zero and less than
UINT64_MAX, and no image beae available within the time allowed.
That is, if info->timeout is larger than zero, the function must return
VK_TIMEOUT instead of VK_NOT_READY if no image became available before
the timeout elapsed.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21190>
Samuel Pitoiset [Thu, 9 Feb 2023 11:45:18 +0000 (12:45 +0100)]
radv/ci: bump the number of runners to 3 for vkcts-navi21-valve
RADV_PERFTEST=gpl increased execution time, so let's try with a 3d
runner.
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
seems reliably fixed now for some reasons.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21214>
Samuel Pitoiset [Wed, 8 Feb 2023 17:37:49 +0000 (18:37 +0100)]
radv/ci: set RADV_PERFTEST=GPL for all VKCTS jobs
The Vulkan CTS version in Mesa CI is so old that a bunch of tests
are broken, but it's expected.
This runs +283939 tests and the overall VKCTS execution time increased
from ~23 minutes to ~26 minutes (+~13%) on my Threadripper 1950X.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21214>
Pavel Ondračka [Tue, 31 Jan 2023 12:20:53 +0000 (13:20 +0100)]
nir: shrink phi nodes in nir_opt_shrink_vectors
While this change helps with few shaders, the main benefit is
that it allows to unroll loops comming from nine+ttn on vec4
backends. D3D9 REP ... ENDREP type loops are unrolled now already,
LOOP ... ENDLOOP need some nine changes that will come later.
r300 RV530 shader-db:
total instructions in shared programs: 132481 -> 132344 (-0.10%)
instructions in affected programs: 3532 -> 3395 (-3.88%)
helped: 13
HURT: 0
total temps in shared programs: 16961 -> 16957 (-0.02%)
temps in affected programs: 88 -> 84 (-4.55%)
helped: 4
HURT: 0
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8102
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7222
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21038>
Samuel Pitoiset [Wed, 8 Feb 2023 14:47:55 +0000 (15:47 +0100)]
docs: stop reporting RADV_PERFTEST=gpl as experimental/suboptimal
The graphics pipeline library implementation in RADV has been
improved considerably lately.
There is still a bit of work for caching individual libraries
and optimized (LTO) pipelines but I think overall it seems good
enough to stop reporting it as experimental and suboptimal.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21213>
Yonggang Luo [Thu, 3 Nov 2022 15:48:31 +0000 (23:48 +0800)]
vulkan: Use static_assert for check HWVULKAN_DISPATCH_MAGIC == ICD_LOADER_MAGIC
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21210>
Chia-I Wu [Wed, 8 Feb 2023 23:14:55 +0000 (15:14 -0800)]
freedreno: avoid conditional ib in fd6_emit_tile
CP_REG_TEST (or any command that reads registers) is slow on a618
(gen1). Since SQE can early return, we don't necessarily need
emit_conditional_ib in fd6_emit_tile.
We still CP_REG_TEST twice for load and store when there is no clear.
Not sure if we can simply drop emit_conditional_ib instead?
glmark2 score goes from 943 to 1067.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21208>
Patrick Lerda [Wed, 8 Feb 2023 14:28:08 +0000 (15:28 +0100)]
mesa/st: fix possible crash related to arb invalid memory access
This invalid memory access is a consequence of wrong assumptions,
for instance:
"prog->sh.data is NULL if it's ARB_fragment_program"
This issue is triggered with piglit/fp-formats -auto -fbo:
==9747==ERROR: AddressSanitizer: heap-use-after-free on address 0x007f7c812d90 at pc 0x007f833c09f8 bp 0x007fd7eca750 sp 0x007fd7eca768
READ of size 4 at 0x007f7c812d90 thread T0
#0 0x7f833c09f4 in st_get_sampler_views ../src/mesa/state_tracker/st_atom_texture.c:109
#1 0x7f833c0b48 in update_textures ../src/mesa/state_tracker/st_atom_texture.c:266
#2 0x7f82b2d120 in st_validate_state ../src/mesa/state_tracker/st_util.h:128
#3 0x7f82b2d120 in prepare_draw ../src/mesa/state_tracker/st_draw.c:88
#4 0x7f82b2de64 in st_draw_gallium ../src/mesa/state_tracker/st_draw.c:141
#5 0x7f83105940 in _mesa_draw_arrays ../src/mesa/main/draw.c:1202
#6 0x7f8d5fa5cc in piglit_draw_rect_from_arrays piglit/tests/util/piglit-util-gl.c:711
#7 0x7f8d5fac34 in piglit_draw_rect_custom piglit/tests/util/piglit-util-gl.c:833
#8 0x4019e0 in piglit_display piglit/tests/shaders/fp-formats.c:67
#9 0x7f8d643fc4 in run_test piglit/tests/util/piglit-framework-gl/piglit_fbo_framework.c:52
#10 0x401624 in main piglit/tests/shaders/fp-formats.c:39
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21175>
Chia-I Wu [Wed, 8 Feb 2023 04:43:48 +0000 (20:43 -0800)]
freedreno/registers: document more bits of CP_REG_TEST
On gen3+, there are 32 predicate bits instead of 1.
I set out to see why CP_REG_TEST (and others commands that read
registers) is slower on gen1 but could not find anything. Since the
blob seems to use multiple predicate bits, let's keep them documented.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
Chia-I Wu [Wed, 8 Feb 2023 20:25:21 +0000 (12:25 -0800)]
turnip: skip unnecessary CP_REG_TEST for cond load/store
When no attachment allows conditional load/store, skip the unnecessary
CP_REG_TEST.
This is done to avoid a performance trap on a618 (gen1). CP_REG_TEST or
any command that reads a register is slow on a618.
glmark2 score goes from 830 to 1001.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8162
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
Chia-I Wu [Wed, 8 Feb 2023 20:25:17 +0000 (12:25 -0800)]
turnip: add a comment to tu_render_pass_cond_config
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
Mike Blumenkrantz [Thu, 9 Feb 2023 17:17:25 +0000 (12:17 -0500)]
zink: implement cross-program pipeline library sharing
some games/apps (e.g., DOOM2016) compile+link shaders in one context
and then use them in another, expecting that the compiled shaders
will be reused. vulkan has pipeline (library) objects, which are not
specific to shaders but are in theory representing the shaders being used
thus, pipeline (library) objects need to be reusable for any case where
a shader can be reused
to handle this:
* extract pipeline library cache to a refcounted object
* store these objects on the screen
* make them owned by shaders
separable programs are slightly different since they'll use their own
fastpath, thus making their library caches owned by the programs to avoid
polluting the optimized caches
fixes #8264
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21223>
Mike Blumenkrantz [Thu, 9 Feb 2023 17:16:12 +0000 (12:16 -0500)]
zink: break out zink_gfx_program::libs into refcounted object
no functional changes yet, and these are still 1:1 with their programs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21223>
Mike Blumenkrantz [Thu, 9 Feb 2023 17:12:16 +0000 (12:12 -0500)]
zink: store gfx_hash on zink_gfx_program
this avoids needing to reference ctx->gfx_hash in threads or recalc the hash
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21223>
Ian Romanick [Fri, 3 Feb 2023 23:57:22 +0000 (15:57 -0800)]
nir/inline_uniforms: Add inot condition support
From the
96c19d23c95700 commit message:
Ever since
4246c2869c3c and
7d85dc4f350b loop unrolling can no
longer depend on inot being eliminated from the loop
terminator condition so we need to be able to handle it.
Support these conditions here too.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Ian Romanick [Mon, 6 Feb 2023 20:32:48 +0000 (12:32 -0800)]
nir/inline_uniforms: Make add_inlinable_uniforms public
This is step 5 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Ian Romanick [Mon, 6 Feb 2023 20:17:45 +0000 (12:17 -0800)]
nir/inline_uniforms: Make src_only_uses_uniforms public, change name
While making the function public, rename it to
nir_collect_src_uniforms. The old name makes it sound like it's just a
query that doesn't have side effects. That is, however, not the case.
This is step 4 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Ian Romanick [Mon, 6 Feb 2023 20:41:49 +0000 (12:41 -0800)]
nir/inline_uniforms: Allow possibility of uni_offsets and num_offsets being NULL
This is step 3 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Ian Romanick [Mon, 6 Feb 2023 19:25:19 +0000 (11:25 -0800)]
nir/inline_uniforms: Allow possibility of more than one UBO
Only caller in this file still only passes 1.
This is step 2 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Ian Romanick [Mon, 6 Feb 2023 19:05:11 +0000 (11:05 -0800)]
nir/inline_uniforms: Pass max_num_bo and max_offset around as parameters
max_num_bo is currently limited to 1. That will change in the next
commit.
This is step 1 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Ian Romanick [Mon, 6 Feb 2023 18:51:34 +0000 (10:51 -0800)]
nir/inline_uniforms: Change num_offsets type to uint8_t
This is step 0 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
Emma Anholt [Wed, 8 Feb 2023 23:56:26 +0000 (15:56 -0800)]
ci/crocus: Update HSW expectations.
2 good-looking trace updates, one new crash.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 21:06:22 +0000 (13:06 -0800)]
ci/radv: Update navi21 llvm xfails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:58:59 +0000 (12:58 -0800)]
ci/nouveau: Disable the gm20b jobs entirely.
The old (broken, hw failure) board isn't really hooked up right now, and
I'm waiting on buying some remaining bits to set up the 10 boards sitting
in the box here.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:55:48 +0000 (12:55 -0800)]
ci/freedreno: Update a3xx piglit_shader xfails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:53:30 +0000 (12:53 -0800)]
ci/freedreno: Add an xfail for a618 VK full run.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:43:11 +0000 (12:43 -0800)]
ci/freedreno: Update a530 manual-run xfails.
A lot of this looks like fractional run test list updates.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:30:36 +0000 (12:30 -0800)]
ci/freedreno: Disable the a306_piglit_gl job.
It's broken with recurring hangchecks. Someone would need to restabilize
it, but turn it off for anyone to find until someone (me? :( ) cares.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:19:59 +0000 (12:19 -0800)]
ci/zink: Update TGL full-run xfails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Emma Anholt [Wed, 8 Feb 2023 20:17:03 +0000 (12:17 -0800)]
ci: Disable systems in my farm that haven't recovered.
We lost power in a storm, and these ones didn't come back afterwards. I
suspect I need a new PSU. And maybe some surge protection for the future.
:(
I've left the CI code in place for some day when I hopefully swap out the
power supplies.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
Nanley Chery [Mon, 14 Nov 2022 22:42:53 +0000 (14:42 -0800)]
mesa/st: Measure compressed fallback unmap paths
Add code to help find performance issues. The logging is disabled by
default.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Fri, 22 Jul 2022 00:28:22 +0000 (17:28 -0700)]
mesa/st: Enable compute-based transcoding to DXT5
By enabling this path, we get a 56% decrease in upload time on a texture
upload microbenchmark. This was measured on an Ice Lake with an iris
driver that tries to use the compressed format fallback path.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Mon, 24 Oct 2022 23:44:03 +0000 (16:44 -0700)]
mesa/st: Add st_texture_image_resource_level
Returns the level of the gl_texture_image with respect to the resource
it's allocated within. Example: returns 0 for non-finalized texture.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Mon, 12 Dec 2022 13:12:46 +0000 (05:12 -0800)]
mesa/st: Add st_compute_transcode_astc_to_dxt5
Add a function to upload ASTC data, transcoding it to BC3/DXT5 in the
process.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Tue, 25 Oct 2022 17:08:21 +0000 (10:08 -0700)]
mesa/st: Add and use create_bc1_endpoint_ssbo
Create and cache the SSBO used by the BC1 compute shader program.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Fri, 22 Jul 2022 00:02:40 +0000 (17:02 -0700)]
mesa/st: Add get_compute_program
Add a function to create and cache the compute programs that will be
used to transcode ASTC to DXT5.
Note that the error paths in st_create_context_priv may actually lead to
segfaults if hit. I've been able to work around them by 1) moving them
further down and 2) returning early from st_glFlush if st->pipe is NULL.
I don't know if that's the right solution however.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Fri, 4 Nov 2022 16:45:10 +0000 (09:45 -0700)]
mesa: Create _mesa_CreateShaderProgramv_impl
Factor out the implementation of _mesa_CreateShaderProgramv so that we
can make programs that will encode DXT5.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Wed, 5 Oct 2022 05:10:39 +0000 (22:10 -0700)]
glsl: Modify the #includes in the DXT5 shaders
1. Drop the commented out includes. Shader caching is disabled if those
are found.
2. Replace the active includes with "%s". Later on, we'll construct the
final strings with vasprintf. One downside to doing this is that the
glsl file extensions are no longer true. These files are now
templates.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Thu, 28 Jul 2022 00:01:05 +0000 (17:01 -0700)]
glsl: Add compute shaders to encode DXT5/BC3
These compute shaders are from the MIT-licensed GPU compressor, Betsy.
I have included copyright headers, inlined the __sharedOnlyBarrier macro
definition from the "UavCrossPlatform_piece_all.glsl" header when
applicable, and made the following changes to support GLES:
* Conditionally disable the const keyword in the BC3 shaders
* Make the params uniform in the BC4 shader uint2
* Avoid implicit data type conversions in the BC3 shaders
* Use constructors for array initialization in the BC1 shader
* Add precision qualifiers to the BC3 shaders
* Output to an rgba16ui image for the BC1 and BC4 shaders
* Set the version of the BC3 shaders to 310 es
Ref: https://github.com/darksylinc/betsy/tree/
cc723dcae9
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Nanley Chery [Thu, 24 Nov 2022 00:20:43 +0000 (16:20 -0800)]
docs: Document the implicit barriers around blits
We're going to use resource_copy_region to copy from a resource that has
been written to with imageStore. Make it clear that this is safe.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
Dave Airlie [Thu, 9 Feb 2023 02:59:53 +0000 (12:59 +1000)]
crocus: disable Y tiling for render targets properly.
The old code would disallow linear targets as well which would confuse
things with reimporting dma-bufs.
Fixes:
32728dc66e36 ("crocus: introduce main resource configuration helper.")
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21209>
Tapani Pälli [Wed, 23 Nov 2022 07:22:36 +0000 (09:22 +0200)]
iris: disable preemption for 3DPRIMITIVE during streamout
This is required by Wa_16013994831.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19947>
Lionel Landwerlin [Wed, 8 Feb 2023 12:11:07 +0000 (14:11 +0200)]
intel/fs: fix mesh indirect movs
The size in src[2] is in byte and needs to cover any possible data
accessed in src[0] by the indirection. That way the register
allocation is aware of what cannot be spilled for the instruction to
execute on valid data.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
70ace2bbcd ("intel/compiler: Implement Task Output and Mesh Input")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21188>
Mike Blumenkrantz [Thu, 9 Feb 2023 14:22:14 +0000 (09:22 -0500)]
zink: set PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
this fixes perf for CompressedTexSubImage and makes DOOM2016 run at full speed
ref #8223
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21218>
Mike Blumenkrantz [Tue, 7 Feb 2023 18:32:21 +0000 (13:32 -0500)]
zink: use GPL to handle (simple) separate shader objects
apps/games using separate shader objects end up passing the separable
shaders to the link_shader hook individually, which is still not ideal for
zink's usage since the more optimal path is to have all the shaders and create
a RAST+FS GPL stage that can run all the inter-stage io handlers
it IS technically possible to handle this for simple VS+FS pipelines using
GPL, however, but it's kinda gross. such shaders now use descriptor buffer
to create their own pipelines/layouts/descriptors async, and then a "separable"
variant of the gfx program can be created by fast-linking these together
the "separable" gfx program can't handle shader variants, but it can do basic
pipeline caching for PSO state changes, which makes it flexible enough to sorta
kinda maybe handle the most basic cases of separate shader objects
descriptor buffer is used because having to create and manage a separate architecture
for sets/pools/templates is too nightmarish even for me
this is, at best, a partial solution, but it's the best the vulkan api can
currently do
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Tue, 7 Feb 2023 18:29:18 +0000 (13:29 -0500)]
zink: enable combining intermediate gpl libs from combine function
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Mon, 6 Feb 2023 19:27:11 +0000 (14:27 -0500)]
zink: move gpl input/output funcs to zink_pipeline.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Mon, 6 Feb 2023 19:15:34 +0000 (14:15 -0500)]
zink: allow multiple gpl libraries in zink_create_gfx_pipeline_combined()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Mon, 6 Feb 2023 18:54:24 +0000 (13:54 -0500)]
zink: add gpl flags for libraries based on shaders passed
no change to current operations
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Mon, 6 Feb 2023 18:49:08 +0000 (13:49 -0500)]
zink: split out gfx pipeline library creation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Mon, 6 Feb 2023 18:33:43 +0000 (13:33 -0500)]
zink: add flags param to zink_pipeline_layout_create()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Mon, 6 Feb 2023 15:40:48 +0000 (10:40 -0500)]
zink: split out VkShaderModule creation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21197>
Mike Blumenkrantz [Thu, 9 Feb 2023 13:03:05 +0000 (08:03 -0500)]
zink: avoid the descriptor set multiplier for bindless buffers
the bindless descriptor buffer is already correctly sized, so it needs
to avoid the huge set multiplier or it'll explode all available vram
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21216>
Mike Blumenkrantz [Thu, 9 Feb 2023 12:48:39 +0000 (07:48 -0500)]
zink: flag bindless_init before calling zink_batch_bind_db() in init
this otherwise fails to bind the bindless buffer
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21216>
Samuel Pitoiset [Tue, 7 Feb 2023 07:39:44 +0000 (08:39 +0100)]
docs: add missing RADV_PERFTEST=video_decode
Fixes:
9477f117f4d ("radv/video: add initial frameworking.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21158>
Tatsuyuki Ishi [Wed, 8 Feb 2023 12:20:41 +0000 (21:20 +0900)]
radv: Assert the hardware support rbplus when emitting rbplus state.
If someone forget to check for rbplus before setting dirty bits, it's going
to cause really mysterious bugs.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21189>
Tatsuyuki Ishi [Wed, 8 Feb 2023 12:19:26 +0000 (21:19 +0900)]
radv: Fix missing rbplus_allowed check for dynamic PS epilogs.
This created really mysterious bugs on gfx10.
Fixes flickering in a bunch of DXVK games, most visibly Overwatch 2.
Fixes:
eb07a11b8f4 ("radv: add support for compiling PS epilogs on-demand")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8258
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21189>
Samuel Pitoiset [Wed, 8 Feb 2023 15:25:43 +0000 (16:25 +0100)]
radv: stop skipping the cache for monolithic graphics pipelines with GPL
Only libraries and optimized (LTO) pipelines are still unsupported,
but there is no reason to skip the cache for monolithic pipelines.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21198>
Samuel Pitoiset [Wed, 8 Feb 2023 14:44:37 +0000 (15:44 +0100)]
radv: stop skipping the cache for compute/raytracing pipelines with GPL
This was a hard solution somewhat.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21198>
Samuel Pitoiset [Wed, 8 Feb 2023 14:10:01 +0000 (15:10 +0100)]
radv: simplify creating a FS epilog from a library
It's now compiled in radv_graphics_pipeline_compile().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21140>
Samuel Pitoiset [Wed, 8 Feb 2023 14:09:09 +0000 (15:09 +0100)]
radv: make sure to disable MRT compaction when compiling a PS epilog with GPL
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21140>
Samuel Pitoiset [Mon, 6 Feb 2023 15:29:05 +0000 (16:29 +0100)]
radv: fix disabling MRT compaction for on-demand PS epilogs
Some dynamic states require to compile PS epilogs on-demand. In this
case, MRT compaction should be disabled because we don't know the CB
state when compiling the fragment shader.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21140>
Samuel Pitoiset [Mon, 6 Feb 2023 15:25:15 +0000 (16:25 +0100)]
radv: regroup PS epilog info when generating the graphics pipeline key
No logical change.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21140>
Samuel Pitoiset [Mon, 6 Feb 2023 15:02:45 +0000 (16:02 +0100)]
radv: simplify determining when the fragment shader needs an epilog
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21140>
Samuel Pitoiset [Mon, 6 Feb 2023 12:54:04 +0000 (13:54 +0100)]
radv: cleanup graphics pipeline library flags uses
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21140>
Samuel Pitoiset [Wed, 8 Feb 2023 13:21:50 +0000 (14:21 +0100)]
radv: fix skipping graphics pipeline compilation when the FS is NULL
Fixes:
3eb97b9d334 ("radv: skip compilation when possible with GPL fast-linking")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21192>
Tapani Pälli [Mon, 6 Feb 2023 12:50:16 +0000 (14:50 +0200)]
intel/blorp: disable REP16 for gfx12+ with R10G10B10_FLOAT_A2
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21137>
Yonggang Luo [Wed, 8 Feb 2023 08:00:35 +0000 (16:00 +0800)]
util: Fixes error: no previous prototype for 'mesa_cache_db_entry_remove'
Fixes:
c92c99481fd ("util/mesa-db: Support removal of cache entries")
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21191>
Emma Anholt [Wed, 11 Jan 2023 19:12:40 +0000 (11:12 -0800)]
zink: Add tracing of blit operations.
I found this useful in lining up some perfetto traces between zink+anv and
iris, and understanding what was going on in them. Also it's a demo of
being able to insert annotations for work in the command stream, which I
suspect we'll want more of.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20657>
Emma Anholt [Mon, 6 Feb 2023 21:18:08 +0000 (13:18 -0800)]
u_trace: Add an interface for checking trace enablement outside a context.
For zink, we want to know if we should pass command stream markers down to
the underlying driver, but we don't have our own trace context we're
recording trace events with. We definitely want those markers if the
underlying driver is going to be doing perfetto tracing, or is requesting
marker tracing. So, create an interface for querying those flags before
they get copied down to an actual u_trace_context.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20657>
José Roberto de Souza [Tue, 7 Feb 2023 16:15:16 +0000 (08:15 -0800)]
hasvk: Remove remaining bits of anv_i915_query()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
José Roberto de Souza [Tue, 7 Feb 2023 16:11:45 +0000 (08:11 -0800)]
anv: Remove remaining bits of anv_i915_query()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
José Roberto de Souza [Tue, 7 Feb 2023 16:42:00 +0000 (08:42 -0800)]
anv: Start to move anv_gem_stubs.c to kmd backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
José Roberto de Souza [Thu, 26 Jan 2023 19:06:46 +0000 (11:06 -0800)]
anv: Add basic KMD backend infrastructure
Functions that are in hot paths will have a different treatment to
support i915 and Xe KMD.
Each KMD will have an anv_kmd_backend that will have the hot path
functions set, this way we can avoid branch prediction misses.
Other functions will gradually be moved to anv_kmd_backend.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
José Roberto de Souza [Mon, 6 Feb 2023 16:41:08 +0000 (08:41 -0800)]
anv: Use DRM_IOCTL_I915_GEM_CREATE_EXT in all supported kernels
As we continue to refactor the code base to support Xe KMD here I'm
dropping anv_gem_create() and unifying all graphics memory allocation
calls to anv_gem_create_regions().
anv_gem_create_regions() will call DRM_IOCTL_I915_GEM_CREATE_EXT
for integrated platforms too only leaving DRM_IOCTL_I915_GEM_CREATE
calls to kernel versions that do not support
DRM_IOCTL_I915_GEM_CREATE_EXT.
This can be detected by devinfo->mem.use_class_instance as
DRM_I915_QUERY_MEMORY_REGIONS uAPI landed in the same kernel version
as DRM_IOCTL_I915_GEM_CREATE_EXT.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
José Roberto de Souza [Fri, 21 Oct 2022 18:53:17 +0000 (11:53 -0700)]
anv: Convert drm_i915_gem_memory_class_instance to intel_memory_class_instance
Also using pointers to intel_device_info struct instead of replicate
the same information.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
José Roberto de Souza [Fri, 21 Oct 2022 18:22:39 +0000 (11:22 -0700)]
intel: Add intel_memory_class_instance
This is a KMD independent struct to hold memory class and instance
values.
drm_i915_gem_memory_class_instance usage will be gradually replaced.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20948>
Emma Anholt [Fri, 3 Feb 2023 00:46:33 +0000 (16:46 -0800)]
ci/freedreno: Don't forget to report flakes on a618, too.
I just noticed that our flake reports are only coming from cheza, which is
a bummer because almost all the VK coverage is on a618 unless you're
kicking off a full run.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21092>
Amber [Wed, 1 Feb 2023 15:38:36 +0000 (16:38 +0100)]
freedreno: make sure depth/stencil layouts are always tiled
Small depth/stencil textures were using linear tiling, but depth/stencil
attachments cannot use linear tiling for sysmem rendering.
Fixes:
KHR-GL45.geometry_shader.layered_framebuffer.stencil_support
KHR-GL45.geometry_shader.layered_framebuffer.depth_support
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21046>
Eric Engestrom [Wed, 8 Feb 2023 22:24:54 +0000 (22:24 +0000)]
docs: update calendar for 22.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21207>
Eric Engestrom [Wed, 8 Feb 2023 21:05:31 +0000 (21:05 +0000)]
docs: add release notes for 22.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21207>