antonino [Fri, 28 Apr 2023 09:35:27 +0000 (11:35 +0200)]
Revert "zink: set when pipeline dirty flag when multisample changes"
This reverts commit
5969541123dbfe1ac339284911a83af712fdcc25.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22753>
Mike Blumenkrantz [Fri, 28 Apr 2023 19:35:00 +0000 (15:35 -0400)]
zink: add extendedDynamicState3DepthClipNegativeOneToOne to profile
Fixes:
3017d01c9de ("zink: check for extendedDynamicState3DepthClipNegativeOneToOne for ds3 support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22765>
Mike Blumenkrantz [Fri, 28 Apr 2023 14:19:04 +0000 (10:19 -0400)]
zink: update amdpro fails
how is this driver still so broken
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22761>
Mike Blumenkrantz [Fri, 28 Apr 2023 20:34:44 +0000 (16:34 -0400)]
llvmpipe: fix native vector width init
this otherwise causes infinite loops in subgroup tests
and kills ci
Fixes:
4a056807bc3 ("gallivm: break out native vector width calc for reuse")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22767>
Dave Airlie [Fri, 26 Aug 2022 06:56:41 +0000 (16:56 +1000)]
gallivm: reorder some texture/image members.
This just aligns texture/image a bit more, shouldn't have much
affect, but might make things easier going forward.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18265>
Dave Airlie [Fri, 26 Aug 2022 06:47:26 +0000 (16:47 +1000)]
gallium: consolidate jit image types between draw/llvmpipe
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18265>
Dave Airlie [Fri, 26 Aug 2022 06:43:18 +0000 (16:43 +1000)]
gallivm: consolidate llvmpipe/draw sampler types.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18265>
Dave Airlie [Fri, 26 Aug 2022 06:36:37 +0000 (16:36 +1000)]
gallivm: consolidate draw/lp texture type.
This just makes the type creation, struct and fields the same.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18265>
Dave Airlie [Fri, 26 Aug 2022 06:31:43 +0000 (16:31 +1000)]
lp_jit: use pipe max for the lp_jit texture levels.
Align this with draw, so we the structs can be shared.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18265>
Mike Blumenkrantz [Sat, 29 Apr 2023 01:09:31 +0000 (21:09 -0400)]
ci: disable all a306/a530/a630 jobs
these have been dead and timing out all day
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22768>
David Heidelberg [Fri, 28 Apr 2023 20:35:21 +0000 (22:35 +0200)]
ci/dzn: add flaking test
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22766>
Ruijing Dong [Thu, 20 Apr 2023 15:22:31 +0000 (11:22 -0400)]
radeonsi/vcn: correct cropping for hevc case
reason:
corect cropping calculation error.
If no cropping from the external, then it will
need to calculate cropping size internally, the
padding size on left and top should be zero.
Cc: mesa-stable
Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7171
Reviewed-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22758>
Samuel Pitoiset [Fri, 28 Apr 2023 12:49:49 +0000 (14:49 +0200)]
ac/nir: fix 8-bit/10-bit PS exports clamping
This broke many tests on GFX6 (Pitcairn).
Fixes:
c1821544562 ("ac/nir: add ac_nir_lower_ps")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22756>
Samuel Pitoiset [Wed, 26 Apr 2023 15:02:38 +0000 (17:02 +0200)]
ac,radv,radeonsi: rename thread_trace to sqtt everywhere
SQTT stands for SQ Thread Trace but it's shorter.
Note that environment variables aren't renamed because this might
break external applications.
This renames:
- ac_thread_trace_data to ac_sqtt (this is the main struct)
- ac_thread_trace_info to ac_sqtt_data_info
- ac_thread_trace_se to ac_sqtt_data_se
- ac_thread_trace to ac_sqtt_trace (this contains trace only)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22732>
Samuel Pitoiset [Wed, 26 Apr 2023 13:41:41 +0000 (15:41 +0200)]
ac/rgp: remove ac_thread_trace_data from ac_thread_trace
We only need the RGP objects.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22732>
Samuel Pitoiset [Wed, 26 Apr 2023 12:28:19 +0000 (14:28 +0200)]
radv: do not abort when the SQTT buffer resize failed
This seems to much. While we are at it, update the error msg.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22732>
Samuel Pitoiset [Wed, 26 Apr 2023 12:26:07 +0000 (14:26 +0200)]
ac/sqtt: add ac_sqtt_get_trace() helper
It can be shared between RADV and RadeonSI. The only difference is
that RadeonSI can't auto-resize the SQTT BO.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22732>
Samuel Pitoiset [Wed, 26 Apr 2023 12:08:44 +0000 (14:08 +0200)]
ac/sqtt: add ac_sqtt_se_is_disabled() helper
It can be shared between RADV and RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22732>
Matt Coster [Tue, 25 Apr 2023 15:31:22 +0000 (16:31 +0100)]
pvr: Fixup format features
Fixes: dEQP-VK.api.info.format_features.*
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22749>
Matt Coster [Fri, 28 Apr 2023 09:11:07 +0000 (10:11 +0100)]
pvr: Remove false assumption from pvr_write_draw_indirect_vdm_stream()
Partially reverts:
bd513059433a6bbda8ce0f95b85dcc76d48f959c
pvr: Minor cleanup around pvr_emit_vdm_index_list()
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22751>
Eric Engestrom [Thu, 27 Apr 2023 18:40:07 +0000 (19:40 +0100)]
v3d: fix various minor issues in gen_pack_header.py
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22742>
José Roberto de Souza [Thu, 20 Apr 2023 18:52:20 +0000 (11:52 -0700)]
iris: Allow shared scanout buffer to be placed in smem as well
i915 and Xe kmd allows scanout to display of prime buffers placed
in smem.
Allowing shared and scanout bos to be placed in smem and lmem allows
the dma buf to work in some cases that only lmem is not enough.
Fixes:
c10ff1970461 ("iris: Place scanout buffers only into lmem for discrete GPUs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8867
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8766
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22665>
Gert Wollny [Mon, 17 Apr 2023 10:06:45 +0000 (12:06 +0200)]
r600/sfn: Tie in address load splitting
Add R600_NIR_DEBUG flag "noaddrsplit" to disable the behaviour and use the
old code path.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Sun, 16 Apr 2023 13:31:32 +0000 (15:31 +0200)]
r600/sfn: prepare for emitting AR loads
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Sun, 16 Apr 2023 07:52:06 +0000 (09:52 +0200)]
r600/sfn: factor out index loading for non-alu instructions
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Tue, 7 Mar 2023 13:30:06 +0000 (14:30 +0100)]
r600/sfn: Can't use an indirect array access as source to AR load
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Mon, 6 Mar 2023 12:02:32 +0000 (13:02 +0100)]
r600/sfn: print failing block when scheduling fails
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:40:04 +0000 (16:40 +0100)]
r600/sfn: Add more tests and update to use address splits
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Mon, 6 Mar 2023 12:01:23 +0000 (13:01 +0100)]
r600/sfn: scheduled instructions are always ready
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Tue, 7 Mar 2023 16:53:08 +0000 (17:53 +0100)]
r600/sfn: Fix copy-prop with array access
We will have to check whether there is access to an array between the
instructions involved with the copy prop, so for now do not allow it.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Sun, 19 Feb 2023 18:05:02 +0000 (19:05 +0100)]
r600/sfn: Override Array access handling in backend assembler
Since we do thi sin the scheduler, there is no need to do this in the
backend again.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Sun, 19 Feb 2023 17:29:07 +0000 (18:29 +0100)]
r600/sfn: Add handling for R600 indirect access alias handling
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Sun, 19 Feb 2023 16:06:13 +0000 (17:06 +0100)]
r600/sfn: Add chip family to shader class
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Tue, 14 Feb 2023 16:35:33 +0000 (17:35 +0100)]
r600/sfn: Start a new ALU CF on index use, not on index emission
With that we can use the two IDX registers in parallel any might
save some CF instructions.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Tue, 14 Feb 2023 16:34:04 +0000 (17:34 +0100)]
r600/sfn: set CF force flag always when starting a new block
There is no reason not to do this, because we only start a new
block if a new CF block must be started.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Tue, 14 Feb 2023 15:46:33 +0000 (16:46 +0100)]
r600/sfn: Add test for multiple index load
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:57:43 +0000 (16:57 +0100)]
r600/sfn: Don't copy-propagate indirect access into LDS instr
Propagating array elements has the problem that we would have to
check whether the last load is not overwritten by an indirect store.
Indirect kcache buffer loads require starting a new CF, and we would
have to make sure that we don't split the LDS fetch/read group with
that, so don't do this.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:40:04 +0000 (16:40 +0100)]
r600/sfn: Add more tests and update to use address splits
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:38:04 +0000 (16:38 +0100)]
r600/sfn: take address loads into account when scheduling
Also change a bit the instruction priority handling
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:36:24 +0000 (16:36 +0100)]
r600/sfn: Add function to check whether a group loads a index register
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:22:38 +0000 (16:22 +0100)]
r600/sfn: Add pass to split addess and index register loads
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:18:57 +0000 (16:18 +0100)]
r600/sfn: Add interface to count AR uses in ALU op
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:17:49 +0000 (16:17 +0100)]
r600/sfn: Add a RW get function of IF predicate access
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:15:34 +0000 (16:15 +0100)]
r600/sfn: AR and IDX don't need the write flag, but haev a parent
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:14:16 +0000 (16:14 +0100)]
r600/sfn: Be able to track expected AR uses
Because AR emission and AR use must be in the same CF we have to
be able to track whether all AR ready are emitted.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:13:04 +0000 (16:13 +0100)]
r600/sfn: Update resource based instruction index mode check
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:12:05 +0000 (16:12 +0100)]
r600/sfn: Add function to insert op in block
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:09:29 +0000 (16:09 +0100)]
r600/sfn: add method to update indirect address to all instrution types
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 15:03:07 +0000 (16:03 +0100)]
r600/sfn: handle AR and IDX register in shader from string
This is needed for testing
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 14:58:52 +0000 (15:58 +0100)]
r600/sfn: Prepare uniforms and local arrays for better address handling
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 10 Feb 2023 14:52:41 +0000 (15:52 +0100)]
r600: Allow both index registers for all CF types
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Sat, 28 Jan 2023 16:53:03 +0000 (17:53 +0100)]
r600/sfn: don't allow more than one AR per instruction
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 27 Jan 2023 10:33:17 +0000 (11:33 +0100)]
r600/sfn: Rework query for indirect access in alu instr and opt
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Fri, 27 Jan 2023 10:31:45 +0000 (11:31 +0100)]
r600/sfn: Add address and index registers creation to ValueFactory
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Thu, 26 Jan 2023 16:25:14 +0000 (17:25 +0100)]
r600/sfn/tests: Cleanup and move some code around
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Thu, 26 Jan 2023 16:11:02 +0000 (17:11 +0100)]
r600/sfn: Handle MOVA_INT in sfn assembler
To properly emit ALU clauses we have to make sure the backend doesn't
add instructions for the address emission.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Thu, 26 Jan 2023 16:09:41 +0000 (17:09 +0100)]
r600/sfn: don't track address registers in live ranges
There is only one address register, and for the index registers we
don't do a special register allocation, so no need to track these
either.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Gert Wollny [Thu, 26 Jan 2023 16:07:20 +0000 (17:07 +0100)]
r600/sfn: Add a type for address registers
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21347>
Matt Coster [Tue, 25 Apr 2023 12:27:28 +0000 (13:27 +0100)]
pvr: Fully declare support for VK_EXT_private_data
Fixes: dEQP-VK.api.info.get_physical_device_properties2.features
.private_data_features
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22738>
Karmjit Mahil [Thu, 20 Apr 2023 08:14:54 +0000 (09:14 +0100)]
pvr: Fix static assert check
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22595>
Karmjit Mahil [Tue, 25 Apr 2023 14:06:26 +0000 (15:06 +0100)]
pvr: Change push_constants_shader_stages to type pvr_stage_allocation
Previously the code was saving the mask as a VkShaderStageFlags
but when allocating shareds it checked against pvr_stage_allocation.
This causes problems as only the vertex bit matches the
VkShaderStageFlagBits so the push constants utilized in fragment
shaders weren't picked up properly.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22731>
Karmjit Mahil [Thu, 20 Apr 2023 08:34:49 +0000 (09:34 +0100)]
pvr: Fix pvr_csb_bake() list return.
The list logic checks for list->next->next (+ some other checks)
to point to the list itself to determine that there is just one
single element.
┌───────────────────────┐
└< { HEAD } >─< { E0 } >┘
When the list_head is copied as was being done previously, the
list element's next pointer still points at the old head so
the `list_is_singular()` check fails.
Fixes pvr_cmd_buffer.c:605:`list_is_singular(&bo_list)` assertion
dEQP-VK.api.image_g.core.clear_color_attachment.cube_layers.b8g8r8a8_unorm
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22730>
Felix DeGrood [Mon, 24 Apr 2023 21:02:27 +0000 (21:02 +0000)]
docs: Add INTEL_DEBUG_BATCH_FRAME_START/_STOP
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
Felix DeGrood [Mon, 24 Apr 2023 21:02:09 +0000 (21:02 +0000)]
iris: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
Felix DeGrood [Mon, 24 Apr 2023 21:00:56 +0000 (21:00 +0000)]
anv: Enable INTEL_DEBUG_BATCH_FRAME_START/_STOP
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
Felix DeGrood [Mon, 24 Apr 2023 20:59:15 +0000 (20:59 +0000)]
intel/debug: Control start/stop frame of batch debug
When using INTEL_DEBUG=bat, INTEL_DEBUG_BATCH_FRAME_START and
INTEL_DEBUG_BATCH_FRAME_STOP can limit dumping of batches for
particular frame ranges. Batch dumps are huge. Smart filtering
allows debugging of single frames during game play. Initial
commit to debug infrastructure.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22564>
Qiang Yu [Sun, 23 Apr 2023 08:39:11 +0000 (16:39 +0800)]
aco: allow no export instruction for gfx10+ fs
radeonsi will generate no export instruction when no
discard and no output.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>
Qiang Yu [Wed, 26 Apr 2023 06:58:58 +0000 (14:58 +0800)]
aco: get scratch addr from symbol for radeonsi
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>
Qiang Yu [Tue, 25 Apr 2023 12:50:48 +0000 (20:50 +0800)]
aco,radv: support symbol relocation in aco
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22727>
Jesse Natalie [Thu, 27 Apr 2023 23:24:56 +0000 (16:24 -0700)]
dzn: Expose core VK1.2 extensions that aren't optional
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22745>
Jesse Natalie [Thu, 27 Apr 2023 23:19:17 +0000 (16:19 -0700)]
dzn: Expose core VK1.1 extensions that aren't optional
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22745>
Lone_Wolf [Thu, 27 Apr 2023 17:46:29 +0000 (19:46 +0200)]
clc: Add clang frontendhlsl module to fix build of microsoft-clc with llvm 16+
Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>
Lone_Wolf [Thu, 27 Apr 2023 17:44:55 +0000 (19:44 +0200)]
clc: Add clangASTMatchers to fix static llvm build of microsoft-clc with LLVM 16+
Cc: mesa-stable
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>
Lone_Wolf [Thu, 27 Apr 2023 17:42:02 +0000 (19:42 +0200)]
compiler/clc: Fix embedded clang headers (microsoft-clc) for LLVM 16+
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7742
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22741>
Eric Engestrom [Thu, 27 Apr 2023 16:16:22 +0000 (17:16 +0100)]
v3d: fix tfu_supports_tex_format() param type, and document why
tex_format should be `enum V3DX(Texture_Data_Formats)`, but using that enum
type in the header requires including `v3dx_pack.h`, which triggers circular
include dependencies issues, so use a `uint32_t` for now.
"fix" the one place that was using the correct enum, because doing so
triggers `-Wenum-int-mismatch` in GCC 13 as the function declaration
doesn't match the function definition.
Reported-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22739>
Danylo Piliaiev [Mon, 24 Apr 2023 14:09:10 +0000 (16:09 +0200)]
ir3: documents (ss) flag for cat7 instructions
Blob produces "lock" instructions with (ss), so our past guess that
cat7 supports (ss) is true.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Mark Collins [Wed, 12 Apr 2023 09:04:01 +0000 (09:04 +0000)]
ir3/a7xx: Add definitions for (last) src GPR attribute
A new attribute on source GPRs reflecting if a certain usage of a
value is the last usage of it was added in A7xx. This is seemingly
a performance hint and doesn't affect anything when not applied.
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Thu, 23 Feb 2023 16:50:47 +0000 (17:50 +0100)]
ir3/a7xx: Document "alias" instruction
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Wed, 22 Feb 2023 18:34:54 +0000 (19:34 +0100)]
ir3: Document that stc has higher DST upper bound than we defined
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Tue, 21 Feb 2023 18:47:58 +0000 (19:47 +0100)]
ir3/a7xx: Add STSC definition
STore Shared Const - loads SIZE dwords from HLSQ_SHARED_CONSTS_IMM
starting from HLSQ_SHARED_CONSTS_IMM[SRC] and writing them to c[DST]
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Tue, 21 Feb 2023 14:50:52 +0000 (15:50 +0100)]
ir3/a7xx: Add new form of stg.a/ldg.a addressing
The new stg.a/ldg.a addressing form supersedes the a6xx's one.
The new form is:
ldg.a.f32 r4.y, g[c0.z+r4.y+2], 4
There are no shift comparing to the a6xx:
ldg.a.f32 r4.y, g[r0.z+(r4.y)<<2], 4
Also on a7xx the first src is allowed to be both const and gpr.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Thu, 16 Feb 2023 19:34:33 +0000 (20:34 +0100)]
ir3/a7xx: Add new lock/unlock CS instructions
Seen at the end of every compuite shader:
%shader_assmebly%
lock
unlock
end
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Thu, 16 Feb 2023 19:33:14 +0000 (20:33 +0100)]
ir3/a7xx: NOPs may have some no-op bits set
[00000001x_00000000x] nop ; dontcare bits in nop:
0000000100000000
[00000002x_00000000x] nop ; dontcare bits in nop:
0000000200000000
Doesn't seem to make them different from ordinary nops.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Danylo Piliaiev [Thu, 27 Apr 2023 20:33:19 +0000 (22:33 +0200)]
freedreno: Early exit in device matching if id doesn't have chip_id
Assert was wrong and caused issues when there are devices defined
after devices that are matched by chip_id.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21498>
Lionel Landwerlin [Tue, 25 Apr 2023 21:20:37 +0000 (00:20 +0300)]
intel/fs: fix per vertex input clamping
Only apply the clamp in multi patch mode (where the input vertices
vary between [1, 32]).
The clamp NIR pass operates on lowered intrinsics so we need to call
it after the inputs have been lowered.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
e25e17dd0c ("intel/fs: clamp per vertex input accesses to patchControlPoints")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8912
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22701>
Mike Blumenkrantz [Wed, 26 Apr 2023 19:37:31 +0000 (15:37 -0400)]
draw: fix robust ubo size calc
if the size of the constant buffer + stride overflows UINT32_MAX,
DIV_ROUND_UP will return 0, which is, in some sense, extremely robust,
but for general functionality it's not actually very robust
cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22720>
Rob Clark [Wed, 26 Apr 2023 17:37:58 +0000 (10:37 -0700)]
dri/android: Fix MSAA resolve
Commit
f9a074dd550 ("dri2/android: Bypass throttling") dropped
unnecessary throtting in the SwapBuffers() path for android. But
unfortunately MSAA resolve got tangled up in the throttle reason
flag. So add a new flag that indicates "no throttingling, but yes
please do MSAA resolve".
Fixes:
f9a074dd550 ("dri2/android: Bypass throttling")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22719>
antonino [Thu, 27 Apr 2023 13:55:39 +0000 (15:55 +0200)]
zink: set when pipeline dirty flag when multisample changes
Sets `gfx_pipeline_state.dirty` appropriately when
`gfx_pipeline_state.multisample` changes
Fixes:
14d58926099 ("zink: add to multisample field to `zink_gfx_pipeline_state`")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22736>
Thong Thai [Tue, 25 Apr 2023 20:05:34 +0000 (16:05 -0400)]
tgsi: use locale independent float and double parsing
The atof and strtod functions use the locale of the user when
determining if a decimal is a comma, ',' or a period, '.'. Thanks to
@fzwoch for helping find the cause of a shader-related issue.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5760
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>
Thong Thai [Tue, 25 Apr 2023 20:12:53 +0000 (16:12 -0400)]
util: check and initialize locale before using it
Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>
Thong Thai [Wed, 26 Apr 2023 18:57:43 +0000 (14:57 -0400)]
mesa/main: rework locale setup/teardown
Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22699>
Ruijing Dong [Wed, 19 Apr 2023 18:04:14 +0000 (14:04 -0400)]
frontends/va: define va av1 encoding caps
by having va av1 caps enabled, av1 vaapi encoding
is enabled.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 01:44:07 +0000 (21:44 -0400)]
radeonsi/vcn: use PIPE_ENC_FEATURE enum
Merge PIPE_H265_ENC_FEATURE into PIPE_ENC_FEATURE enum
because those are common flags, and it will be
used in AV1 encoder as well.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 18:01:50 +0000 (14:01 -0400)]
frontends/va: adding va av1 encoding functions
supported features:
- 8/10 bit encoding
- multi-layer (up to 4) encoding
- vbr/cbr rate control mode
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 02:33:29 +0000 (22:33 -0400)]
radeonsi/vcn: add av1 encoding ib packages and get_info
add av1 encoding ib packages and enable the
get_info functions.
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 02:24:06 +0000 (22:24 -0400)]
radeonsi/vcn: add some av1 encoding function
preparation for enabling av1 encoding in radeonsi,
adding the entropy related functioin.
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 02:21:24 +0000 (22:21 -0400)]
radeonsi/vcn: add av1 enc data structure
add av1 encoding related data structure.
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 02:28:38 +0000 (22:28 -0400)]
gallium/pipe: add av1 encoding data structure in pipe
add pipe av1 encoding data structure
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 02:06:43 +0000 (22:06 -0400)]
radeonsi/vcn: add av1 dpb variables and cdf table
add av1 dpb variables and cdf table.
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
Ruijing Dong [Wed, 19 Apr 2023 01:19:35 +0000 (21:19 -0400)]
radeonsi/vcn: remove extra zero bytes from bitstream
reason:
extra bytes are not needed and not necessary
in h264/h265 bitstreams, because they are in
between NALs, the only problem is they consumed
extra bits. And for av1 streams, that could be
explained to something else, especially in
multi-layer cases, that can cause syntax errors.
ptr[6] represents the bitstream size,
ptr[8] represents the extra zero bytes.
The total number of bytes of the output
should be ptr[6] - ptr[8]
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22585>
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