Alex Deucher [Tue, 9 Oct 2018 20:50:38 +0000 (15:50 -0500)]
drm/amdgpu/powerplay: endian fixes for vega20_processpptables.c
Properly swap data from vbios.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 9 Oct 2018 20:33:16 +0000 (15:33 -0500)]
drm/amdgpu/powerplay: endian fixes for vega12_processpptables.c
Properly swap data from vbios.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 9 Oct 2018 20:23:15 +0000 (15:23 -0500)]
drm/amdgpu/powerplay: endian fixes for vega10_processpptables.c
Properly swap data from vbios.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Wed, 26 Sep 2018 14:15:34 +0000 (14:15 +0000)]
drm/amdgpu: remove set but not used variable 'header'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo':
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning:
variable 'header' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Sat, 29 Sep 2018 11:39:14 +0000 (11:39 +0000)]
drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stop
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop':
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning:
variable 'ring' set but not used [-Wunused-but-set-variable]
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Tue, 9 Oct 2018 01:53:00 +0000 (01:53 +0000)]
drm/amdkfd: Remove set but not used variable 'preempt_all_queues'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c: In function 'destroy_queue_cpsch':
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:1366:7: warning:
variable 'preempt_all_queues' set but not used [-Wunused-but-set-variable]
It never used since introduct in
commit
992839ad64f2 ("drm/amdkfd: Add static user-mode queues support")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Mon, 8 Oct 2018 16:22:28 +0000 (17:22 +0100)]
drm/amdgpu/powerplay: fix missing break in switch statements
There are several switch statements that are missing break statements.
Add missing breaks to handle any fall-throughs corner cases.
Detected by CoverityScan, CID#1457175 ("Missing break in switch")
Fixes:
18aafc59b106 ("drm/amd/powerplay: implement fw related smu interface for iceland.")
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lyude Paul [Sat, 22 Sep 2018 00:43:44 +0000 (20:43 -0400)]
drm/amdgpu: Suppress keypresses from ACPI_VIDEO events
Currently we return NOTIFY_DONE for any event which we don't think is
ours. However, many laptops will send more then just an ATIF event and
will also send an ACPI_VIDEO_NOTIFY_PROBE event as well. Since we don't
check for this, we return NOTIFY_DONE which causes a keypress for the
ACPI event to be propogated to userspace. This is the equivalent of
someone pressing the display key on a laptop every time there's a
hotplug event.
So, check for ACPI_VIDEO_NOTIFY_PROBE events and suppress keypresses
from them.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 9 Oct 2018 10:46:12 +0000 (18:46 +0800)]
drm/amdgpu: Remove the direct fw loading support for sdma2.4
sdma2.4 is only for iceland. For Vi, we don't maintain the
direct fw loading.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 10 Oct 2018 13:04:14 +0000 (21:04 +0800)]
drm/amdgpu: Remove wrong fw loading type warning
Remove the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 10 Oct 2018 12:41:32 +0000 (20:41 +0800)]
drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2
Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 10 Oct 2018 11:28:30 +0000 (19:28 +0800)]
drm/amdgpu: split ip hw_init into 2 phases
We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.
Will do fw loading via smu/psp between the two phases.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 9 Oct 2018 06:22:04 +0000 (14:22 +0800)]
drm/amdgpu: Remove amdgpu_ucode_fini_bo
The variable clean is unnecessary.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 9 Oct 2018 05:55:49 +0000 (13:55 +0800)]
drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading
the ucode bo only need to be created when load driver
and free when driver unload.
when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.
Suggested by Christian.
v2: Return error when bo create failed.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 3 Oct 2018 08:19:50 +0000 (16:19 +0800)]
drm/amdgpu: Check late_init status before set cg/pg state
Fix cg/pg unexpected set in hw init failed case.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Wed, 3 Oct 2018 08:10:45 +0000 (16:10 +0800)]
drm/amdgpu: Refine function amdgpu_device_ip_late_init
1. only call late_init when hw_init successful,
so check status.hw instand of status.valid in late_init.
2. set status.late_initialized true if late_init was not implemented.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 30 Sep 2018 09:37:27 +0000 (17:37 +0800)]
drm/amdgpu: Change AI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 30 Sep 2018 09:32:36 +0000 (17:32 +0800)]
drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Wed, 10 Oct 2018 07:43:47 +0000 (15:43 +0800)]
drm/amdgpu: Limit the max mc address to hole start
For the vram_start is 0 case, the gart range will be from 0x0000FFFF00000000
to 0x0000FFFF1FFFFFFF, which will cause the engine hang.
So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 9 Oct 2018 03:40:31 +0000 (11:40 +0800)]
drm/amdgpu: fix CPDMA hang in PRT mode
Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX
Affected ASICs: Vega10 Vega12 Raven
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Tested-by: Yukun.Li <yukun1.li@amd.com>
Tested-by: Maciej.Jesionowski <maciej.jesionowski@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 9 Oct 2018 03:30:36 +0000 (11:30 +0800)]
drm/amdgpu: add CP_DEBUG register definition for GC9.0
Add CP_DEBUG register definition.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu [Tue, 9 Oct 2018 17:50:10 +0000 (13:50 -0400)]
drm/amd/display: RV2 DP MST 2nd display within daisy chain not light up
RV2 resource is limit to 3 pipes. Limitation should apply to all HW
blocks instead of front pipe.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Tue, 9 Oct 2018 17:50:09 +0000 (13:50 -0400)]
drm/amd/display: Fix warning storm on Raven2
[Why]
Wrong index for pstate debug test register
[How]
Add correct index value for dcn1_01 in hubbub1_construct()
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 30 Sep 2018 09:35:12 +0000 (17:35 +0800)]
drm/amdgpu: Change VI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 07:57:31 +0000 (15:57 +0800)]
drm/amdgpu: Add fw load in gfx_v8 and sdma_v3
gfx and sdma can be initialized before smu.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 12:28:14 +0000 (20:28 +0800)]
drm/amd/pp: Implement load_firmware interface
with this interface, gfx/sdma can be initialized
before smu.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 07:42:52 +0000 (15:42 +0800)]
drm/amd/pp: Allocate ucode bo in request_smu_load_fw
ucode bo is needed by request_smu_load_fw,
the request_smu_load_fw maybe called by gfx/sdma
before smu hw init.
so move amdgpu_ucode_bo_init to request_smu_lowd_fw
from smu hw init.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 07:30:11 +0000 (15:30 +0800)]
drm/amdgpu: Don't reallocate ucode bo when suspend
driver don't release the ucode memory when suspend. so don't
need to allocate bo when resume back.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 12:09:00 +0000 (20:09 +0800)]
drm/amdgpu: Remove FW_LOAD_DIRECT type support on VI
AMDGPU_FW_LOAD_DIRECT is used for bring up.
Now it don't work any more. so remove the support.
v2: Add warning message if user select
AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 2 Oct 2018 17:31:31 +0000 (13:31 -0400)]
drm/amdgpu/vcn:Correct VCN cache window definition
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 2 Oct 2018 16:56:32 +0000 (12:56 -0400)]
drm/amdgpu/vcn:Replace value with defined macro
Replace value with defined macro to make
code more readable
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 2 Oct 2018 15:44:50 +0000 (11:44 -0400)]
drm/amdgpu/vcn:fix dpg pause mode hang issue
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 1 Oct 2018 22:18:59 +0000 (18:18 -0400)]
drm/amdgpu/vcn:Remove unused code
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nick Alcock [Thu, 4 Oct 2018 19:58:09 +0000 (20:58 +0100)]
drm/radeon: ratelimit bo warnings
So a few days ago I started getting sprays of these warnings --
sorry, but because it was a few days ago I'm not sure what I was
running at the time (but it was probably either Stellaris or Chromium).
Sep 25 22:06:34 mutilate err: : [ 544.718905] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc
Sep 25 22:06:34 mutilate err: : [ 544.718909] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2!
Sep 25 22:06:34 mutilate err: : [ 544.719710] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc
Sep 25 22:06:34 mutilate err: : [ 544.719714] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2!
Sep 25 22:06:34 mutilate err: : [ 544.719862] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc
Sep 25 22:06:34 mutilate err: : [ 544.719865] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2!
Sep 25 22:06:34 mutilate err: : [ 544.720772] [drm:radeon_cs_parser_relocs] *ERROR* gem object lookup failed 0xc
Sep 25 22:06:34 mutilate err: : [ 544.720778] [drm:radeon_cs_ioctl] *ERROR* Failed to parse relocation -2!
Sep 25 22:06:34 mutilate warning: : [ 544.721415] radeon 0000:01:00.0: vbo resource seems too big for the bo
followed by a massive stream of "vbo resource seems too big for the bo".
The most extreme flood ran from 23:01:58 to 23:02:47 and emitted 91,000
lines of log in that time. This... seems excessive, given that each log
message after the first contains more or less no information.
So ratelimit these messages. (We probably want to see at least *some* so
that the underlying bug can be fixed -- always assuming the bug isn't in
unfixable closed-source game code somewhere.)
Signed-off-by: Nick Alcock <nick.alcock@oracle.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 26 Sep 2018 14:15:44 +0000 (16:15 +0200)]
drm/amdgpu: fix incorrect use of amdgpu_irq_add_id in si_dma.c
Adding a second irq source because of a different src_id is actually a
bug.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 4 Oct 2018 08:27:48 +0000 (10:27 +0200)]
drm/amdgpu: fix AGP location with VRAM at 0x0
That also simplifies handling quite a bit.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Fri, 5 Oct 2018 05:24:21 +0000 (10:54 +0530)]
drm/amdgpu: remove the intterupt handling for the KIQ events
[Why]
1. we never submit IBs to the KIQ
2. there seems to be ~500ms delay during amdgpu resume spent in KIQ,
hence pointing toward interrupts are not working correctly.
[How]
remove interrupt handling for KIQ.
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>i
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 22 Aug 2018 19:28:44 +0000 (15:28 -0400)]
drm/amdkfd: Fix incorrect use of process->mm
This mm_struct pointer should never be dereferenced. If running in
a user thread, just use current->mm. If running in a kernel worker
use get_task_mm to get a safe reference to the mm_struct.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pratik Vishwakarma [Wed, 3 Oct 2018 15:15:11 +0000 (20:45 +0530)]
drm/amdgpu: skip IB tests for KIQ in general
[Why]
1. We never submit IBs to KIQ.
2. Ring test pass without KIQ's ring also.
3. By skipping we see an improvement of around 500ms
in the amdgpu's resume time.
[How]
skip IB tests for KIQ ring type.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Tue, 2 Oct 2018 06:41:24 +0000 (23:41 -0700)]
drm/scheduler: Simplify spsc_queue_count check in drm_sched_entity_select_rq
Clang generates a warning when it sees a logical not followed by a
conditional operator like ==, >, or <.
drivers/gpu/drm/scheduler/sched_entity.c:470:6: warning: logical not is
only applied to the left hand side of this comparison
[-Wlogical-not-parentheses]
if (!spsc_queue_count(&entity->job_queue) == 0 ||
^ ~~
drivers/gpu/drm/scheduler/sched_entity.c:470:6: note: add parentheses
after the '!' to evaluate the comparison first
if (!spsc_queue_count(&entity->job_queue) == 0 ||
^
( )
drivers/gpu/drm/scheduler/sched_entity.c:470:6: note: add parentheses
around left hand side expression to silence this warning
if (!spsc_queue_count(&entity->job_queue) == 0 ||
^
( )
1 warning generated.
It assumes the author might have made a mistake in their logic:
if (!a == b) -> if (!(a == b))
Sometimes that is the case; other times, it's just a super convoluted
way of saying 'if (a)' when b = 0:
if (!1 == 0) -> if (0 == 0) -> if (true)
Alternatively:
if (!1 == 0) -> if (!!1) -> if (1)
Simplify this comparison so that Clang doesn't complain.
Fixes:
35e160e781a0 ("drm/scheduler: change entities rq even earlier")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 05:54:33 +0000 (13:54 +0800)]
drm/amd/pp: Refine smu7/8 request_smu_load_fw callback function
The request_smu_load_fw of VI is used to load gfx/sdma
ip's firmware.
Check whether the gfx/sdma firmware have been loaded successfully
in this callback function.
if failed, driver can exit to avoid gpu hard hung.
if successful, clean the flag reload_fw to avoid duplicated fw load.
when suspend/resume, driver need to reload fw.
so in suspend, reset the reload_fw flag to true to enable load fw when
resume.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 06:32:47 +0000 (14:32 +0800)]
drm/amd/pp: Setup SoftRegsStart before request smu load fw
need to know SoftRegsStart value to visit the register
UcodeLoadStatus to check fw loading state.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 05:28:20 +0000 (13:28 +0800)]
drm/amd/pp: Refine function iceland_start_smu
if upload firmware failed, no matter how many times
the function runs again, the same error will be encountered.
so remove the duplicated code.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 07:27:02 +0000 (15:27 +0800)]
drm/amdgpu: Move gfx flag in_suspend to adev
Move in_suspend flag to adev from gfx, so
can be used in other ip blocks, also keep
consistent with gpu_in_reset flag.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 06:52:31 +0000 (14:52 +0800)]
drm/amd/pp: Fix memory leak on CI/AI
On CI/AI, fw was not loaded by smu, but
smu's fw still need to be released
when driver fini.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sat, 29 Sep 2018 09:07:48 +0000 (17:07 +0800)]
drm/amdgpu: Drop dead define in amdgpu.h
the struct was not in use any more.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 5 Oct 2018 16:11:25 +0000 (00:11 +0800)]
drm/amdgpu: Always enable fan sensors for read
don't need to set fan1_enable to read fan sensors.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 28 Sep 2018 08:01:48 +0000 (16:01 +0800)]
drm/amdgpu: Disable sysfs pwm1 if not in manual fan control
Following lm-sensors 3.0.0,
Only enable pwm1 sysfs when fan control mode(pwm1_enable)
in manual
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 20 Sep 2018 06:30:55 +0000 (14:30 +0800)]
drm/amdgpu: Add fan RPM setting via sysfs
Add fan1_target for get/set fan speed in RPM unit
Add fan1_min/fan1_max for get min, max fan speed in RPM unit
Add fan1_enable to enable/disable the fan1 sensor
v3: drop the hardcode value of min/max rpm in comments pointed
out by Alex.
v2: query the min/max rpm gpu support instand of hardcode value.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 30 Sep 2018 05:19:00 +0000 (13:19 +0800)]
drm/amd/pp: Implement AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM
so user can query the RPM range
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 30 Sep 2018 05:18:17 +0000 (13:18 +0800)]
drm/amdgpu: Add new AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM sensor
For getting the min/max fan speed in RPM units.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 28 Sep 2018 07:25:06 +0000 (15:25 +0800)]
drm/amdgpu: Refine uvd_v6/7_0_enc_get_destroy_msg
1. make uvd_v7_0_enc_get_destroy_msg static
2. drop a function variable that always true
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Mon, 24 Sep 2018 13:31:47 +0000 (19:01 +0530)]
drm/amd/display: Signal hw_done() after waiting for flip_done()
In amdgpu_dm_commit_tail(), wait until flip_done() is signaled before
we signal hw_done().
[Why]
This is to temporarily address a paging error that occurs when a
nonblocking commit contends with another commit, particularly in a
mirrored display configuration where at least 2 CRTCs are updated.
The error occurs in drm_atomic_helper_wait_for_flip_done(), when we
attempt to access the contents of new_crtc_state->commit.
Here's the sequence for a mirrored 2 display setup (irrelevant steps
left out for clarity):
**THREAD 1** | **THREAD 2**
|
Initialize atomic state for flip |
|
Queue worker |
...
| Do work for flip
|
| Signal hw_done() on CRTC 1
| Signal hw_done() on CRTC 2
|
| Wait for flip_done() on CRTC 1
<---- **PREEMPTED BY THREAD 1**
Initialize atomic state for cursor |
update (1) |
|
Do cursor update work on both CRTCs |
|
Clear atomic state (2) |
**DONE** |
...
|
| Wait for flip_done() on CRTC 2
| *ERROR*
|
The issue starts with (1). When the atomic state is initialized, the
current CRTC states are duplicated to be the new_crtc_states, and
referenced to be the old_crtc_states. (The new_crtc_states are to be
filled with update data.)
Some things to note:
* Due to the mirrored configuration, the cursor updates on both CRTCs.
* At this point, the pflip IRQ has already been handled, and flip_done
signaled on all CRTCs. The cursor commit can therefore continue.
* The old_crtc_states used by the cursor update are the **same states**
as the new_crtc_states used by the flip worker.
At (2), the old_crtc_state is freed (*), and the cursor commit
completes. We then context switch back to the flip worker, where we
attempt to access the new_crtc_state->commit object. This is
problematic, as this state has already been freed.
(*) Technically, 'state->crtcs[i].state' is freed, which was made to
reference old_crtc_state in drm_atomic_helper_swap_state()
[How]
By moving hw_done() after wait_for_flip_done(), we're guaranteed that
the new_crtc_state (from the flip worker's perspective) still exists.
This is because any other commit will be blocked, waiting for the
hw_done() signal.
Note that both the i915 and imx drivers have this sequence flipped
already, masking this problem.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Thu, 27 Sep 2018 18:06:33 +0000 (11:06 -0700)]
drm/amd/display: Use proper enums in process_channel_reply
Clang warns when one enumerated type is implicitly converted to another.
drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.c:315:19: warning:
implicit conversion from enumeration type 'enum
aux_channel_operation_result' to different enumeration type 'enum
aux_transaction_reply' [-Wenum-conversion]
reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/i2caux/dce110/aux_engine_dce110.c:349:19:
warning: implicit conversion from enumeration type 'enum
aux_channel_operation_result' to different enumeration type 'enum
aux_transaction_reply' [-Wenum-conversion]
reply->status = AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON;
~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The current enum is incorrect, it should be from aux_transaction_reply,
so use AUX_TRANSACTION_REPLY_HPD_DISCON.
Reported-by: Nick Desaulniers <ndesaulniers@google.com>
Suggested-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 21 Sep 2018 13:35:24 +0000 (09:35 -0400)]
drm/amd/display: Raise dispclk value for dce_update_clocks
[Why]
The DISPCLK value was previously requested to be 15% higher for all
ASICS that went through the dce110 bandwidth code path. As part of a
refactoring of dce_clocks and dce110 set_bandwidth this was removed
for power saving considerations.
This changed caused corruption under certain display configurations.
Originally thought to be Vega specific, it was also observed on Polaris.
[How]
The 15% is brought back but its placement differs from the original
patch. This boost should only be enable while DFS bypass is inactive.
This (like the Vega patch) is also a workaround that should be
removed after the root cause is identified.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Murton Liu [Wed, 19 Sep 2018 18:31:12 +0000 (14:31 -0400)]
drm/amd/display: HLK Periodic Frame Notification test failed
[Why]
Due to a small pre-fetch window, the active vline timing is a couple
of lines off when compared to what it should be.
[How]
Changed the calculation for the start vline to account for this window.
Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Tue, 18 Sep 2018 17:23:42 +0000 (13:23 -0400)]
drm/amd/display: fix Interlace video timing.
[Description] interlace mode shows wrong vertical timing.
Interface timing in Edid is half vertical timing as progressive timing.
driver doubled the vertical timing in edid_paser,
no need to double in optc again.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Tue, 18 Sep 2018 14:21:35 +0000 (10:21 -0400)]
drm/amd/display: Flatten irq handler data struct
[Why]
There is no reason why the common data needs to be kept separate.
[How]
Flatten the struct by moving common data into the DM IRQ struct.
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Tue, 18 Sep 2018 13:38:20 +0000 (09:38 -0400)]
drm/amd/display: fix memory leak in resource pools
[why]
ddc engines were recently changed to be independently tracked
from pipe count. the change was reflected in resource constructor
but not in destructor. this manifests as a memory leak when
pipe harvesting is enabled, since not all constructed ddc engines
are freed
[how]
make destructor symmetric with constructor for all dcX_resource
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Mon, 10 Sep 2018 15:30:52 +0000 (11:30 -0400)]
drm/amd/display: dc 3.1.68
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Mon, 17 Sep 2018 14:05:51 +0000 (10:05 -0400)]
drm/amd/display: WA for DF keeps awake after S0i3.
[Why]
DF keeps awake after S0i3 resume due to DRAM_STATE_CNTL
is set by bios command table during dcn init_hw.
[How]
As a work around, check STATE_CNTL status before init_hw,
if it is 0 before init_hw and set to 1 after init_hw,
change it to 0.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Fri, 14 Sep 2018 19:55:01 +0000 (15:55 -0400)]
drm/amd/display: clean up encoding checks
[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Fri, 14 Sep 2018 17:53:14 +0000 (13:53 -0400)]
drm/amd/display: block DP YCbCr420 modes
[why]
Currently not supported, will black screen when set.
[How]
Fail validate timing helper for those modes.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eryk Brol [Fri, 7 Sep 2018 17:24:28 +0000 (13:24 -0400)]
drm/amd/display: Add function to fetch clock requirements
Also add dram clock to clocks struct, for systems that uses them.
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Su Sung Chung [Thu, 13 Sep 2018 19:26:08 +0000 (15:26 -0400)]
drm/amd/display: Calculate swizzle mode using bpp during validation
[Why]
Previously bandwidth validation was failing because swizzle mode was not
initialized during plane_state allocation. The swizzle mode was
calculated using pixed format which is how swizzle mode is initially
calculated in addrlib.
[How]
* Set default swizzle mode for validation to DC_SW_UNKNOWN
* Created new function in dcn10_assign_swizzle_mode which sets the
plane swizzle mode based on selected pixed format
* Added the call of assign_swizzle_mode into dc_validate_global_state
* Set failsafe swizzle mode back to DC_SW_LINEAR
Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Wed, 12 Sep 2018 19:17:51 +0000 (15:17 -0400)]
drm/amd/display: Add a check-function for virtual signal type
[why]
Same functions exist for all other signal types.
[how]
Add a function that checks against virtual signal type.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 12 Sep 2018 22:22:16 +0000 (18:22 -0400)]
drm/amd/display: fix 4K stereo screen flash issue
[Why]
HDMI_scramber is not enabled for pixel rate >340Mhz.
[How]
Calculate the phy clock to include the Hw frame packing factor.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Thu, 13 Sep 2018 13:32:26 +0000 (09:32 -0400)]
drm/amd/display: Add DC build_id to determine build type
[why]
Sometimes there are indications that the incorrect driver is being
loaded in automated tests. This change adds the ability for builds to
be tagged with a string, and picked up by the test infrastructure.
[how]
dc.c will allocate const for build id, which is init-ed with default
value, indicating production build. For test builds, build server will
find/replace this value. The test machine will then verify this value.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Akshu Agrawal [Mon, 24 Sep 2018 10:18:02 +0000 (15:48 +0530)]
drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
Multiple runs of power measurement shows no imapct.
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Rex Zhu [Wed, 26 Sep 2018 04:17:52 +0000 (12:17 +0800)]
drm/amd/pp: Remove wrong code in fiji_start_smu
HW CG feature will be enabled after hw ip initialized
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 28 Sep 2018 08:57:34 +0000 (16:57 +0800)]
drm/amd/pp: Remove uncessary extra vcn pg cntl in smu
the vcn power will be controlled by VCN.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 25 Sep 2018 11:53:30 +0000 (19:53 +0800)]
drm/amdgpu: Move out power up/down sdma out of smu
smu only expose interface to other ip blocks.
in order to reduce dependence between smu and other ip blocks
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 25 Sep 2018 11:45:46 +0000 (19:45 +0800)]
drm/amd/pp: Expose the smu support for SDMA PG cntl
SDMA IP can be power up/down via smu message
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 20 Sep 2018 03:50:26 +0000 (11:50 +0800)]
drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpm
The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 20 Sep 2018 07:11:08 +0000 (15:11 +0800)]
drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10
set the target rpm value to wrong register.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Tue, 25 Sep 2018 05:27:00 +0000 (13:27 +0800)]
drm/amdgpu: Fix comments error in sdma_v4_1_update_power_gating
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 27 Sep 2018 05:48:45 +0000 (13:48 +0800)]
drm/amd/powerplay: enable MGPU fan boost feature on Vega20
Added Vega20 specific implementation for MGPU fan boost
feature.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 27 Sep 2018 05:43:16 +0000 (13:43 +0800)]
drm/amd/powerplay: helper interfaces for MGPU fan boost feature
MGPU fan boost feature is enabled only when two or more dGPUs
in the system.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 27 Sep 2018 05:26:58 +0000 (13:26 +0800)]
drm/amdgpu: added AMD GPU instance counting V2
Count all GPU instances from AMD(including iGPUs and
dGPUs) in the system.
V2: drop unnecessary initialization for other gpu_info
members except mutex
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 27 Sep 2018 03:55:47 +0000 (22:55 -0500)]
drm/amdgpu/vega20: make power profile output more consistent
Make the profile name line match previous generations more closely.
E.g.,
0 3D_FULL_SCREEN :
vs:
0(3D_FULL_SCREEN )
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 19 Sep 2018 11:07:19 +0000 (19:07 +0800)]
drm/amdgpu: change Raven always on CUs to 4
For Vega10 and Vega20, the always on CUs are 12.
For Raven, it's 4.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 24 Aug 2018 08:40:03 +0000 (16:40 +0800)]
drm/amdgpu: added vega20 LBPW support v2
Enable LBPW support on vega20.
v2: squash in warning fix (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Sep 2018 10:04:44 +0000 (18:04 +0800)]
drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2
Manual fan RPM and pwm setting on vega20 are
available now.
V2: correct the register for fan speed setting and
avoid divide-by-zero
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 17 Sep 2018 10:41:28 +0000 (18:41 +0800)]
drm/amd/powerplay/vega20: tell the correct gfx voltage V2
Export the correct gfx voltage by hwmon interface.
V2: update the register naming for consistency
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 17 Sep 2018 07:05:54 +0000 (15:05 +0800)]
drm/amd/powerplay/vega20: correct the hwmon interface ppt limit output
The ppt limit read out by hwmon interface is always 0.
Correct this hwmon interface output.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Thu, 4 Oct 2018 01:30:58 +0000 (11:30 +1000)]
Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next
misc mali-dp updates.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Liviu Dudau <Liviu.Dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003105009.GD1156@e110455-lin.cambridge.arm.com
Dave Airlie [Thu, 4 Oct 2018 01:28:54 +0000 (11:28 +1000)]
Merge tag 'tilcdc-4.20' of https://github.com/jsarha/linux into drm-next
drm/tilcdc changes for Linux v4.20
suspend/resume update.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jyri Sarha <jsarha@ti.com>
Link: https://patchwork.freedesktop.org/patch/msgid/bd8d6b40-d3d6-8e24-9d48-6201b860aceb@ti.com
Dave Airlie [Thu, 4 Oct 2018 01:03:34 +0000 (11:03 +1000)]
BackMerge v4.19-rc6 into drm-next
I have some pulls based on rc6, and I prefer to have an explicit backmerge.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 4 Oct 2018 00:40:35 +0000 (10:40 +1000)]
Merge tag 'exynos-drm-next-for-v4.20' of git://git./linux/kernel/git/daeinki/drm-exynos into drm-next
Add out-bridge support
- This patch series enables out-bridge for LVDS bridge device support,
and also includes two cleanups and one relevant dt binding update
for this.
Add Samsung 16x16 tiled format support
- This patch series adds Samsung 16x16 tiled format to scaler and
gsc drivers. As for this, it adds Samsung specific format to
drm_forcc.h header. For the git-pull request with relevant patches,
I requested ack-by[1] to relevant maintainers but there was no any response.
I'm pretty sure no problem to go to mainline though Exynos tree
because the only user of it is Exynos.
(airlied: this looked fine to me)
[1] https://patchwork.freedesktop.org/patch/243921/
Add configurable plane alpha and pixel blend mode support
- This patch series makes mixer driver to be configuragle for
pixel blend mode and plane alpha, which also includes one fixup
to set all default values correctly after reset.
One cleanup
- This patch replaces drm_atomic_helper_suspend/resume() with
drm_mode_config_helper_suspend/resume() to remove exynos specific
suspend_state.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Inki Dae <inki.dae@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1538380891-24040-1-git-send-email-inki.dae@samsung.com
Dave Airlie [Thu, 4 Oct 2018 00:38:23 +0000 (10:38 +1000)]
Merge tag 'omapdrm-4.20-2' of git://git./linux/kernel/git/tomba/linux into drm-next
omapdrm fixes and cleanups for 4.20
- fix memory barrier bug in DMM driver
- fix interrupt management in DMM driver
- partial workaround for errata i878
- fix use of freed memory
- some cleanups
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Tomi Valkeinen <tomi.valkeinen@ti.com>
Link: https://patchwork.freedesktop.org/patch/msgid/36bdd576-2b5c-d69e-24af-05572652b08e@ti.com
Dave Airlie [Thu, 4 Oct 2018 00:37:30 +0000 (10:37 +1000)]
Merge tag 'drm-misc-next-fixes-2018-10-03' of git://anongit.freedesktop.org/drm/drm-misc into drm-next
- Add EXPERT config option to allow phys mem leak from fbdev for blob drivers (Neil)
Cc: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Sean Paul <sean@poorly.run>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003195957.GA64584@art_vandelay
Dave Airlie [Thu, 4 Oct 2018 00:19:33 +0000 (10:19 +1000)]
Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next
Mostly code reorganizations and optimizations for vmwgfx.
- Move TTM code that's only used by vmwgfx to vmwgfx
- Break out the vmwgfx buffer- and resource validation code to a separate source file
- Get rid of a number of atomic operations during command buffer validation.
From: Thomas Hellstrom <thellstrom@vmware.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180928131157.2810-1-thellstrom@vmware.com
Neil Armstrong [Fri, 28 Sep 2018 12:05:55 +0000 (14:05 +0200)]
drm/fb_helper: Allow leaking fbdev smem_start
Since "drm/fb: Stop leaking physical address", the default behaviour of
the DRM fbdev emulation is to set the smem_base to 0 and pass the new
FBINFO_HIDE_SMEM_START flag.
The main reason is to avoid leaking physical addresse to user-space, and
it follows a general move over the kernel code to avoid user-space to
manipulate physical addresses and then use some other mechanisms like
dma-buf to transfer physical buffer handles over multiple subsystems.
But, a lot of devices depends on closed sources binaries to enable
OpenGL hardware acceleration that uses this smem_start value to
pass physical addresses to out-of-tree modules in order to render
into these physical adresses. These should use dma-buf buffers allocated
from the DRM display device instead and stop relying on fbdev overallocation
to gather DMA memory (some HW vendors delivers GBM and Wayland capable
binaries, but older unsupported devices won't have these new binaries
and are doomed until an Open Source solution like Lima finalizes).
Since these devices heavily depends on this kind of software and because
the smem_start population was available for years, it's a breakage to
stop leaking smem_start without any alternative solutions.
This patch adds a Kconfig depending on the EXPERT config and an unsafe
kernel module parameter tainting the kernel when enabled.
A clear comment and Kconfig help text was added to clarify why and when
this patch should be reverted, but in the meantime it's a necessary
feature to keep.
Cc: Dave Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Noralf Trønnes <noralf@tronnes.org>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Ben Skeggs <skeggsb@gmail.com>
Cc: Christian König <christian.koenig@amd.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Dave Airlie <airlied@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1538136355-15383-1-git-send-email-narmstrong@baylibre.com
Ayan Kumar Halder [Tue, 10 Jul 2018 13:18:55 +0000 (14:18 +0100)]
drm/arm/malidp: Implemented the size validation for AFBC framebuffers
AFBC buffers include additional metadata which increases the required
allocation size. Implement the appropriate size validation and sanity
checking for AFBC buffers.
Added malidp specific function for framebuffer creation. This checks
if the framebuffer has AFBC modifiers and if so, it verifies the
necessary constraints on the size, alignment, offsets and pitch.
Changes from v2:
- Replaced DRM_ERROR() with DRM_DEBUG_KMS() in
malidp_verify_afbc_framebuffer_caps() and malidp_verify_afbc_framebuffer_size()
Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>
Reviewed-by: Brian Starkey <brian.starkey@arm.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Liviu Dudau [Tue, 2 Oct 2018 11:11:00 +0000 (12:11 +0100)]
drm/arm/malidp: Validate rotations for compressed/uncompressed framebuffers for each layer
Add support for compressed framebuffers that are described using
the framebuffer's modifier field. Mali DP uses the rotation memory for
the decompressor of the format, so we need to check for space when
the modifiers are present.
Signed-off-by: Ayan Kumar Halder <ayan.halder@arm.com>
Reviewed-by: Brian Starkey <brian.starkey@arm.com>
[re-worded commit, rebased, cleaned up duplicated checks for
RGB888 and BGR888 and removed additional parameter for
rotmem_required function hook]
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Jamie Fox [Mon, 1 Oct 2018 13:39:07 +0000 (14:39 +0100)]
drm/malidp: Enable MMU prefetch on Mali-DP650
Mali-DP650 supports warming up the SMMU translations, by sending
requsts to the SMMU before a buffer is read.
There are two modes supported:
- PARTIAL: could be enabled when the buffer is composed of 4K or 64K
pages, the display hardware will send a configurable number of
requests before the actual reading.
- FULL: could be enabled when the buffer is composed of 1M or 2M
pages, the display hardware will send requests before reading for
all pages composing the buffer.
This patch adds a mechanism for detecting the page size and set the
MMU prefetch mode if possible.
Changes since v1:
- For imported buffers use the already populated
drm_gem_cma_object.sgt instead of calling
driver.gem_prime_get_sg_table, which works just for buffers
allocated through the gem_cma API.
Signed-off-by: Jamie Fox <jamie.fox@arm.com>
Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
[rebased and re-ordered functions]
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Lowry Li [Fri, 31 Aug 2018 11:35:30 +0000 (19:35 +0800)]
drm/mali-dp: Implement plane alpha and pixel blend on malidp
Checks the pixel blending mode and plane alpha value when
do the plane_check. Mali DP supports blending the current plane
with the background either based on the pixel alpha blending
mode or by using the layer's alpha value, but not both at the
same time. If both case, plane_check will return failed.
Sets the HW when doing plane_update accordingly. If plane alpha
is the 0xffff, set the pixel blending bits accordingly. If not
we'd set ALPHA bit as zero and layer alpha value.
Changes since v1:
- Introduces to use it in the malidp driver, which depends on
the plane alpha patch
Changes since v2:
- Refines the comments of drm/mali-dp patchset
Changes since v3:
- Adds hardware limitation check
Changes since v4:
- Updates on drm/malidp, hardware limitation check only when
the format has alpha pixel.
- Rebases on drm-misc-next.
Signed-off-by: Lowry Li <lowry.li@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Alexandru Gheorghe [Fri, 21 Sep 2018 13:39:44 +0000 (14:39 +0100)]
drm/malidp: Fix smart layer when doing pm_suspend/resume
Smart layer enable rectangles is set to 1 when the driver is probed,
however when doing pm_suspend the value is lost and it's not set again
making the SMART_LAYER unusable, fix that by initializing the number
of rectangles everytime we do a plane update.
Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Alexandru Gheorghe [Wed, 22 Aug 2018 15:18:19 +0000 (16:18 +0100)]
drm/malidp: Fix writeback in NV12
When we want to writeback to memory in NV12 format we need to program
the RGB2YUV coefficients. Currently, we don't program the coefficients
and NV12 doesn't work at all.
This patchset fixes that by programming a sane default(bt709, limited
range) as rgb2yuv coefficients.
In the long run, probably we need to think of a way for userspace to
be able to program that, but for now I think this is better than not
working at all or not advertising NV12 as a supported format for
memwrite.
Changes since v1:
- Write the rgb2yuv coefficients only once, since we don't change
them at all, just write them the first time NV12 is programmed,
suggested by Brian Starkey, here [1]
[1] https://lists.freedesktop.org/archives/dri-devel/2018-August/186819.html
Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Alexandru Gheorghe [Mon, 16 Jul 2018 10:07:07 +0000 (11:07 +0100)]
drm: mali-dp: Call drm_crtc_vblank_reset on device init
Currently, if userspace calls drm_wait_vblank before the crtc is
activated the crtc vblank_enable hook is called, which in case of
malidp driver triggers some warninngs. This happens because on
device init we don't inform the drm core about the vblank state
by calling drm_crtc_vblank_on/off/reset which together with
drm_vblank_get have some magic that prevents calling drm_vblank_enable
when crtc is off.
Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>