intel/dev: Add DG2 G12 PCI IDs

Ref: https://patchwork.freedesktop.org/patch/483381/?series=103098&rev=1
Ref: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>

intel/dev: Add INTEL_PLATFORM_DG2_G12

Cc: 22.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16449>

radv/winsys: allow to use RADV_FORCE_FAMILY=gfx1100

The bare minimum to play with fossils.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16446>

r600: Elide downloads for discarded and immutable compute memories.

Compute memory item demotion invokes a device to host transfer unconditionally,
but there are at least two cases where this is not necessary:

1. The item is mapped for discarding with PIPE_MAP_DISCARD_RANGE (e.g.
CL_MAP_WRITE_INVALIDATE_REGION).

2. The item cannot be written to by the device.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16116>

r600: Improve compute memory pool performance; reduce fragmentation.

The compute memory pool forced a defragmentation (a left-packing relocation)
of items prior to promoting (adding) items to the tail end of the pool.

This patch instead makes an initial pass over the fragmented pool intent on
promoting items back to where they may have been recently demoted, filling
in the gaps first before conducting the defragmentation (if at all).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16117>

r600: Fix userspace pointer support for evergreen compute.

Resources returned by r600_buffer_from_user_memory() are not compatible
with the evergreen compute memory pool, though they're added to it anyway.

This results in a segfault reproducible from Clover when the user passes
CL_MEM_USE_HOST_PTR.

This patch allows user_ptr resources to participate in the compute global
memory pool as intended. The result appears to finally allow for zero-copy
DMA out of userspace for anonymous pages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16114>

amd: fix ac_build_mbcnt_add in wave32 mode

add_src was ignored and i32_0 was always used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 1e49018cedf ("amd: Add extra source to the mbcnt_amd NIR intrinsic.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16427>

radeonsi: don't use wave32 for GE on gfx10 if culling is used

This is a workaround for issue #6457: it fixes the rendering and
prevent the hang but I can't explain why.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6457
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16427>

radeonsi: fix gs_invocation query with NGG

When NGG is active, the GS invocation counter is always incremented, even
if there's no explicit GS.

Implementing the counter manually fixes it:
  * in emit_gs_epilogue for the legacy path
  * in gfx10_ngg_gs_emit_prologue for the ngg path

This fixes piglit's arb_query_buffer_object-qbo test.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi/ngg: reuse the pipeline stats buffer when using atomics

To support PIPE_STAT_QUERY_GS_INVOCATIONS and PIPE_STAT_QUERY_GS_PRIMITIVES
being used at the same time we have to reuse the same buffer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi/query: use the qbo correct size

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi/test: update sienna_cichlid results

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi: implement GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB in shaders

Statistics only work in non-NGG mode. If screen->use_ngg is true, we can't
know if the draw will actually use NGG or not, so this commit switch
to a shader based implementation of this counter.

To avoid modifying si_query, the shader implementation behaves like the hw
one: it uses the same buffer size and offset.

The emulation path activation in the shader is controlled by vs_state_bit[31].

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi: store the pipeline stats index

Will be used in later commits.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi: deduplicate query offsets

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

gallium: deduplicate target -> stats index code

Now that target_to_index returns the correct index for
PIPE_QUERY_PIPELINE_STATISTICS we can use it in store_query_result instead
of duplicating the switch statement.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

gallium: always return the correct pipeline stats index

Drivers with PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE = 0 shouldn't care
about the value of index, but radeonsi actually needs it in some situations.

So return the correct index instead of 0.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

gallium: add a union to access queries counters

This allows to loop over counters easily.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi: implement pipeline stats workaround

DISABLE_INSTANCE_PACKING needs to be enabled when stats queries are
active to fix incorrect results.

We need to emit this for indexed and non-indexed draws.

Based on PAL's waDisableInstancePacking.

This fixes:
  KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

radeonsi: flush VGT streamout like PAL

Ported from 165b016bbeedd4e8d1517a5e95949871cc55a123.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>

zink: fix sparse texture depth calcs for arrayed textures

use the array, not the depth

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16456>

zink: remove misleading sparse comment

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16456>

zink: set sparse flag in cubemap lowering

Fixes: 2d745904ca7 ("zink: add a gently mangled version of the d3d12 cubemap -> array compiler pass")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16456>

zink: fix sparse binding for arrayed textures

this needs to set the arrayLayer, not the z offset

big thanks to Piers Daniell for catching this

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16456>

zink: clamp out min_lod operands for explicit lod ops

this is illegal (and nonsensical)

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16456>

zink: fix up sparse texture sampling for shadow samplers

the problem here is that this returns a vec2 instead of a vec5, which
throws all the existing calculations off

given that the shader is (still) expecting a vec2 return from this,
and there's no way to sanely rewrite with nir to be valid for both
sampler types as well as spirv translation, just pad out to a vec2
here and be done with it

Fixes: 73ef54e3424 ("zink: handle residency return value from sparse texture instructions")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16456>

nir: remove unreachable loop terminators

Remove the conditional break statements associated with all
terminators that are associated with a fixed iteration count,
except for the one associated with the limiting terminator.

This logic matches similiar functionality that exists in the
old GLSL IR unrolling code.

This change helps a piglit test pass on the r300 driver once
we switch off the old GLSL IR unrolling code.

Shader-db results IRIS (BDW):

total instructions in shared programs: 17538619 -> 17538595 (<.01%)
instructions in affected programs: 216 -> 192 (-11.11%)
helped: 3
HURT: 0
helped stats (abs) min: 7 max: 10 x̄: 8.00 x̃: 7
helped stats (rel) min: 10.00% max: 12.07% x̄: 11.38% x̃: 12.07%

total cycles in shared programs: 858674910 -> 858672810 (<.01%)
cycles in affected programs: 79540 -> 77440 (-2.64%)
helped: 3
HURT: 0
helped stats (abs) min: 620 max: 800 x̄: 700.00 x̃: 680
helped stats (rel) min: 2.45% max: 2.83% x̄: 2.63% x̃: 2.62%

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16399>

nir: always set the exact_trip_count_unknown loop terminator property

Previously we only cared if this was set for the limiting
terminator. However in the following patch we will make use of this
information on other terminators to decide if we can eliminate them.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16399>

ntt: make use of new samplers_used field

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

ntt: Don't gather samplers_declared twice

Prior to scanning instrucitons, we initialize it based on variables.  If
this is adding anything, we have a bug somewhere.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

lavapipe: Set images_used in lvp_lower_pipeline_layout

This mirrors what we do for textures.  Also, the current code is busted
because it sets it based on var->data.binding which
lvp_lower_pipeline_layout will change so it can get out-of-sync.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

llvmpipe: Fill out samplers even if nr_samplers = 0

Coming in from Vulkan or OpenCL, it's possible for nr_samplers to be
zero if all we ever use is texelFetch().  Annoyingly, samplers and
sampler views are handled by the same function.  Fortunately, it will
work if some of the samplers or sampler views are missing so we can just
pass the maximum.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

gallium/draw: Properly handle nr_samplers != nr_sampler_views in keys

First, make all key_size functions take nr_samplers and nr_sampler_views
separately so we ensure both get passed in.  Second, rework the offset
helpers to take MAX(nr_samplers, nr_sampler_views) so we get the image
param offset correct if nr_samplers < nr_sampler_views.  While we're
here, also re-order the size calculations to be in the same order as the
things land in memory.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

mesa/st: Set samplers_used in lower_tex_src_plane

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

ttn: Set shader_info::samplers_used

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

gallium: Set shader_info::samplers_used in pstipple_fs

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

lavapipe: Set shader_info::samplers_used

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

clover: Set images/samplers_used when lowering images

Also, stop using BITSET_SET_RANGE_INSIDE_WORD for textures so we can
handle more than 32 of them.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16435>

turnip: Add a TU_DEBUG=perf debug option.

For doing performance investigation, I often find it useful to have a "are
we tripping over any of our performance TODOs?" flag, so add it and use it
in a few of the TODOs.

This also greatly cleans up the deqp-vk logs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16316>

radv: Print task shader stage name before disasm.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Lower shared and task_payload variables in task/mesh shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Allow linking task shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Postprocess task shader configuration.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Use I/O lowering for task and mesh shaders.

We set the number of task shader ring entries in radv_device
based on the generous assumption that each CU can run task/mesh
shaders with maximum occupancy.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Enable nir_opt_offsets for task shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Implement task shader intrinsics in the ABI.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Add task ring entry argument for mesh shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Add task shader arguments.

Mostly the same as for compute shaders, but with a few extras:

task_ring_offsets:
Same as what ring_offsets is to graphics shaders.
Contains an address that points to a buffer that contains
the ring buffer descriptors.

task_ring_entry:
Index that can be used to address the draw and payload rings.

draw_id:
Same meaning as in graphics shaders.

task_ib_addr/task_ib_stride:
Indirect buffer address and stride from the draw calls.
These are used to emulate the firstTask feature of NV_mesh_shader.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Fill task shader info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Set wave size for task shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Set user data register for task shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

radv: Add radv_pipeline_has_task helper.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

ac: Add task ring entry shader argument.

This is going to be used by both task and mesh shaders for
accessing the draw and payload ring buffers.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

ac/nir: Add I/O lowering for task and mesh shaders.

Task shaders store their output payload to VRAM where mesh
shaders read from. There are two ring buffers:

1. Draw ring: this is where mesh dispatch sizes and
the ready bit are stored.

2. Payload ring: this is where the optional payload
is stored (up to 16K per task workgroup).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>

nir: Mark negative re-distribution on fadd as imprecise

Otherwise, it would mutate `fneg(fadd(-0, 0))` into `fadd(0, -0)` which
isn't correct since -0 + (+0) = +0 + (-0) = +0.

This fixes the OpenCL contraction tests on Iris.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16041>

iris: Set BindingTableEntryCount for compute shaders

This may slightly increase perf somewhere because the hardware can now
pre-cache binding tables.  The real feature is that INTEL_DEBUG=bat now
dumps out surface states for compute.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15759>

svga: workaround for unexpected double swizzle

SM5 requires swizzles for 64 bits alu source to be either .xyzw,
.xyxy, .zwxy, or .zwzw. If the swizzles are not in the valid pattern,
move the source according to the specified swizzle to a temporary register
first.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16464>

pan/bi: Ensure the end NOP isn't eliminated

Otherwise the lowering doesn't work.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Support atomics on Valhall

Atomics on Valhall work basically the same as on Bifrost, however the
instruction selection is simplified as there are no clauses. Support the
simplified set of atomic instructions.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Handle shared/scratch on Valhall

There's no .seg modifier, so we have some easy lowering to do ourselves.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Handle shared atomic exchange on Valhall

Need to lower the WLS into a segment addition, since the .seg modifier was
dropped on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Preserve AXCHG.i32 destination

dEQP-GLES31.functional.image_load_store.2d.atomic.exchange_r32f_result

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Support image loads on Valhall

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Emit LEA_TEX on Valhall

As opposed to LEA_ATTR_TEX. In principle we could do this for Bifrost too, but
let's keep the Midgard compatible path for now.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

pan/bi: Don't analyze td on Valhall

The implementation is based on clauses, so it won't work on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16410>

lavapipe: enable subgroup quad operations

Signed-off-by: Autumn on Tape <autumn@cyfox.net>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16340>

mesa: Make sure to fallback to handling the original choose texture format

It is possible for st_ChooseTextureFormat to return MESA_FORMAT_NONE when
samples is forced to 2. Always allow to fallback to the original case.

Fixes: 89c94502b6650fed222abd3588e9c927811580aa
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6441
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16432>

aco: drop unused radv include

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco: remove radv vs prolog key from aco internals.

This creates an aco specific key, and converts radv to it.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco/radv: convert to aco shader info at the radv level.

This removes the radv shader info type from aco completely.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco/info: add some more fields.

These fields are also used in aco.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco: convert vs and so info over to aco structs.

This renames the vs to vp (vertex pipeline) on the way past.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco: remove radv specific streamout info

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco/info: reduce the gs ring info to what is needed.

Only one member was being used.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco: move to a minimal aco shader info struct.

This should be kept to only things aco uses, and expanded when
radeonsi support is added. Things should be removed if lowered in NIR.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

aco: move info pointer to a copy.

This is just setup to move this to a different struct later.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16342>

radv: Don't retile read-only images.

Avoid unnessecary work on FOREIGN queue release barriers. If we can't modify
the image there can't be a situation where we need to update the presentable
dcc data.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16371>

pps: Open writable renderer node in DrmDevice::create

DrmDevice::create_all correctly opened the node with O_RDWR, while
DrmDevice::create was not, causing failure to create writable buffer.

Fixes pps-config on Freedreno.

Fixes: 1cc72b2aef82373247466c2e7b81970c867ad0fa
("pps: Gfx-pps v0.3.0")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16406>

panvk: Advertise support for logicOp

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

nir/lower_blend: Expand or shrink output variables as needed

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

midgard: Handle FB fetch from non-vec4 output variables.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

nir/builder: Add a nir_resize_vector helper

We're about to use this a couple of places.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

nir/builder: Add a nir_trim_vector helper

This pattern pops up a bunch and the semantics of nir_channels() aren't
very convenient much of the time.  Let's add a nir_trim_vector() which
matches nir_pad_vector().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

nir/lower_blend: Support SNORM and integer formats for logic ops

This fixes 158 of the dEQP-VK.pipeline.logic_op.* tests, once we turn
the feature on.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

nir/lower_blend: Stop passing the whole options object around

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

nir/lower_blend: Be more explicit about deref assumptions

Because we pull the RT from the variable location and use that to look
up formats, we need a constant RT index.  To deal with arrays (possibly
of arrays), we would either need to handle array derefs (we don't today)
or we need to require the variables to be split into one variable per
RT.  Given that we have to lower indirect derefs anyway (to get constant
indices), we may as well require the client to split output variables by
calling nir_lower_io_arrays_to_elements_no_indirect().

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

panvk: Call nir_lower_io_arrays_to_elements_no_indirects

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16309>

ci/radv: remove amdgpu.gpu_recovery=0 from the kernel cmdline

This was set as an attempt to detect when the GPU got hung, and let
our hangcheck detect this issue and kill the run. This however has
not been working so well, so let's try without it.

Suggested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16423>

v3dv: expose VK_KHR_spirv_1_4

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16424>

v3dv: expose VK_KHR_shader_float_controls

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16424>

tu: Do not flush ccu in clear/blits during renderpass

For clear/blits ccu flush not only worse for perf, but also messes up
flush_bits when executed in a conditional set of commands.

We already don't flush for 3d blits.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6419

Fixes: 487aa807bd1b70602fcb6fbdabd101d4cff7c07b
("tu: Rewrite flushing to use barriers")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16352>

radv: remove useless check against nir_texop_samples_identical

nir_texop_samples_identical is lowered to
nir_texop_fragment_mask_fetch_amd earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16426>

radeonsi: report more missing/broken texture formats as unsupported on gfx6-9

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16386>

radeonsi: report 10_10_10_2 scaled formats as unsupported on gfx6-9 as well

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16386>

radv: optimised command buffer reset of vertex bindings.

This takes the buffer ptrs out of the struct, so they can be memset
separately and optimises the memset to be minimal for them.

Removing them from the struct avoids having to loop to clear them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>

radv: only dirty line stipple when necessary.

Line stipple only cares if things changes to/from line strip.

Reduces overheads seen running pixmark volplosion with zink.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>

radv: cache the slab bo pointer in the pipeline.

Otherwise each emission has to pointer chase across cachelines.

Reduces overhead seen with zink on pixmark volplosion test.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>

zink: don't finish barriers cmd buffer if not used.

finishing has some cpu overhead, which if the cmd buffer isn't
going to be used is pointless. just let it get reset next time.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>

zink: avoid extra submits for empty wait cmdbufs.

This just avoids cpu overheads from processing that won't get used.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16393>

radeonsi: Move NULL check before dereference.

Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking desc suggests that it may be
null, but it has already been dereferenced on all paths leading to
the check.

Fixes: 2f83dce059 ("radeonsi: don't report R64_*INT as a sampler format because it doesn't work")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16380>