David Malcolm [Thu, 15 Jul 2021 19:04:07 +0000 (15:04 -0400)]
analyzer: add -fdump-analyzer-exploded-paths
gcc/analyzer/ChangeLog:
* analyzer.opt (fdump-analyzer-exploded-paths): New.
* diagnostic-manager.cc
(diagnostic_manager::emit_saved_diagnostic): Implement it.
* engine.cc (exploded_path::dump_to_pp): Add ext_state param and
use it to dump states if non-NULL.
(exploded_path::dump): Likewise.
(exploded_path::dump_to_file): New.
* exploded-graph.h (exploded_path::dump_to_pp): Add ext_state
param.
(exploded_path::dump): Likewise.
(exploded_path::dump): Likewise.
(exploded_path::dump_to_file): New.
gcc/ChangeLog:
* doc/invoke.texi (-fdump-analyzer-exploded-paths): New.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Thu, 15 Jul 2021 19:02:42 +0000 (15:02 -0400)]
analyzer: use DECL_DEBUG_EXPR on SSA names for artificial vars
gcc/analyzer/ChangeLog:
* analyzer.cc (fixup_tree_for_diagnostic_1): Use DECL_DEBUG_EXPR
if it's available.
* engine.cc (readability): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Thu, 15 Jul 2021 19:01:57 +0000 (15:01 -0400)]
analyzer: handle self-referential phis
gcc/analyzer/ChangeLog:
* state-purge.cc (self_referential_phi_p): New.
(state_purge_per_ssa_name::process_point): Don't purge an SSA name
at its def-stmt if the def-stmt is self-referential.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/phi-1.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Christophe Lyon [Thu, 15 Jul 2021 15:27:46 +0000 (15:27 +0000)]
testsuite: [arm] Remove arm_v8_2a_imm8_neon_ok_nocache
This patch removes this recently-introduced effective-target, as it
looks like a typo and duplicate for arm_v8_2a_i8mm_ok (imm8 vs i8mm),
and it is not used.
2021-07-15 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/testsuite/
* lib/target-supports.exp (arm_v8_2a_imm8_neon_ok_nocache):
Delete.
Christophe Lyon [Thu, 15 Jul 2021 15:22:19 +0000 (15:22 +0000)]
testsuite: [arm] Add missing effective-target to vusdot-autovec.c
This test fails when forcing an -mcpu option incompatible with
-march=armv8.2-a+i8mm.
This patch adds the missing arm_v8_2a_i8mm_ok effective-target, as
well as the associated dg-add-options arm_v8_2a_i8mm.
2021-07-15 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/testsuite/
* gcc.target/arm/simd/vusdot-autovec.c: Use arm_v8_2a_i8mm_ok
effective-target.
Jakub Jelinek [Thu, 15 Jul 2021 16:53:20 +0000 (18:53 +0200)]
c++: Optimize away NULLPTR_TYPE comparisons [PR101443]
Comparisons of NULLPTR_TYPE operands cause all kinds of problems in the
middle-end and in fold-const.c, various optimizations assume that if they
see e.g. a non-equality comparison with one of the operands being
INTEGER_CST and it is not INTEGRAL_TYPE_P (which has TYPE_{MIN,MAX}_VALUE),
they can build_int_cst (type, 1) to find a successor.
The following patch fixes it by making sure they don't appear in the IL,
optimize them away at cp_fold time as all can be folded.
Though, I've just noticed that clang++ rejects the non-equality comparisons
instead, foo () > 0 with
invalid operands to binary expression ('decltype(nullptr)' (aka 'nullptr_t') and 'int')
and foo () > nullptr with
invalid operands to binary expression ('decltype(nullptr)' (aka 'nullptr_t') and 'nullptr_t')
Shall we reject those too, in addition or instead of parts of this patch?
If so, wouldn't this patch be still useful for backports, I bet we don't
want to start reject it on the release branches when we used to accept it.
2021-07-15 Jakub Jelinek <jakub@redhat.com>
PR c++/101443
* cp-gimplify.c (cp_fold): For comparisons with NULLPTR_TYPE
operands, fold them right away to true or false.
* g++.dg/cpp0x/nullptr46.C: New test.
Tamar Christina [Thu, 15 Jul 2021 16:42:10 +0000 (17:42 +0100)]
testsuite: Fix testisms in scalar tests PR101457
These testcases accidentally contain the wrong signs for the expected values
for the scalar code. The vector code however is correct.
Committed as a trivial fix.
gcc/testsuite/ChangeLog:
PR middle-end/101457
* gcc.dg/vect/vect-reduc-dot-17.c: Fix signs of scalar code.
* gcc.dg/vect/vect-reduc-dot-18.c: Likewise.
* gcc.dg/vect/vect-reduc-dot-22.c: Likewise.
* gcc.dg/vect/vect-reduc-dot-9.c: Likewise.
Martin Sebor [Thu, 15 Jul 2021 16:11:23 +0000 (10:11 -0600)]
Avoid -Wvla-parameter for nontrivial bounds [PR97548].
Resolves:
PR c/101289 - bogus -Wvla-paramater warning when using const for vla param
PR c/97548 - bogus -Wvla-parameter on a bound expression involving a parameter
gcc/c-family/ChangeLog:
PR c/101289
PR c/97548
* c-warn.c (warn_parm_array_mismatch): Use OEP_DECL_NAME.
gcc/c/ChangeLog:
PR c/101289
PR c/97548
* c-decl.c (get_parm_array_spec): Strip nops.
gcc/ChangeLog:
PR c/101289
PR c/97548
* fold-const.c (operand_compare::operand_equal_p): Handle OEP_DECL_NAME.
(operand_compare::verify_hash_value): Same.
* tree-core.h (OEP_DECL_NAME): New.
gcc/testsuite/ChangeLog:
* gcc.dg/Wvla-parameter-12.c: New test.
Martin Jambor [Thu, 15 Jul 2021 15:26:45 +0000 (17:26 +0200)]
Change the type of return value of profile_count::value to uint64_t
The field in which profile_count holds the count has 61 bits but the
getter method only returns it as a 32 bit number. The getter is (and
should be) only used for dumping but even dumps are better when they
do not lie.
gcc/ChangeLog:
2021-07-13 Martin Jambor <mjambor@suse.cz>
* profile-count.h (profile_count::value): Change the return type to
uint64_t.
* gimple-pretty-print.c (dump_gimple_bb_header): Adjust print
statement.
* tree-cfg.c (dump_function_to_file): Likewise.
Jonathan Wakely [Wed, 14 Jul 2021 19:14:14 +0000 (20:14 +0100)]
libstdc++: Fix std::get<T> for std::tuple [PR101427]
The std::get<T> functions relied on deduction failing if more than one
base class existed for the type T. However the implementation of Core
DR 2303 (in r11-4693) made deduction succeed (and select the
more-derived base class).
This rewrites the implementation of std::get<T> to explicitly check for
more than one occurrence of T in the tuple elements, making it
ill-formed again. Additionally, the large wall of overload resolution
errors described in PR c++/101460 is avoided by making std::get<T> use
__get_helper<I> directly instead of calling std::get<I>, and by adding a
deleted overload of __get_helper<N> for out-of-range N.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
PR libstdc++/101427
* include/std/tuple (tuple_element): Improve static_assert text.
(__get_helper): Add deleted overload.
(get<i>(tuple<T...>&&), get<i>(const tuple<T...>&&)): Use
__get_helper directly.
(__get_helper2): Remove.
(__find_uniq_type_in_pack): New constexpr helper function.
(get<T>): Use __find_uniq_type_in_pack and __get_helper instead
of __get_helper2.
* testsuite/20_util/tuple/element_access/get_neg.cc: Adjust
expected errors.
* testsuite/20_util/tuple/element_access/101427.cc: New test.
Jonathan Wakely [Wed, 14 Jul 2021 11:25:11 +0000 (12:25 +0100)]
libstdc++: Add noexcept to __replacement_assert [PR101429]
This results in slightly smaller code when assertions are enabled when
either using Clang (because it adds code to call std::terminate when
potentially-throwing functions are called in a noexcept function) or a
freestanding or non-verbose build (because it doesn't use printf).
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
PR libstdc++/101429
* include/bits/c++config (__replacement_assert): Add noexcept.
[!_GLIBCXX_VERBOSE] (__glibcxx_assert_impl): Use __builtin_trap
instead of __replacement_assert.
Bill Schmidt [Thu, 15 Jul 2021 15:16:17 +0000 (10:16 -0500)]
rs6000: Don't let swaps pass break multiply low-part (PR101129)
2021-07-15 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
PR target/101129
* config/rs6000/rs6000-p8swap.c (has_part_mult): New.
(rs6000_analyze_swaps): Insns containing a subreg of a mult are
not swappable.
gcc/testsuite/
PR target/101129
* gcc.target/powerpc/pr101129.c: New.
Richard Biener [Thu, 15 Jul 2021 09:41:12 +0000 (11:41 +0200)]
Streamline vect_gen_while
This adjusts the vect_gen_while API to match that of
vect_gen_while_not allowing further patches to generate more
than one stmt for the while case.
2021-07-15 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_gen_while): Match up with
vect_gen_while_not.
* tree-vect-stmts.c (vect_gen_while): Adjust API to that
of vect_gen_while_not.
(vect_gen_while_not): Adjust.
* tree-vect-loop-manip.c (vect_set_loop_controls_directly): Likewise.
Aldy Hernandez [Thu, 15 Jul 2021 10:38:36 +0000 (12:38 +0200)]
Abstract out non_null adjustments in ranger.
There are 4 exact copies of the non-null range adjusting code in the
ranger. This patch abstracts the functionality into a separate method.
As a follow-up I would like to remove the varying_p check, since I have
seen incoming ranges such as [0, 0xff....ef] which are not varying, but
are not-null. Removing the varying restriction catches those.
gcc/ChangeLog:
* gimple-range-cache.cc (non_null_ref::adjust_range): New.
(ranger_cache::range_of_def): Call adjust_range.
(ranger_cache::entry_range): Same.
* gimple-range-cache.h (non_null_ref::adjust_range): New.
* gimple-range.cc (gimple_ranger::range_of_expr): Call
adjust_range.
(gimple_ranger::range_on_entry): Same.
Tamar Christina [Thu, 15 Jul 2021 12:16:15 +0000 (13:16 +0100)]
Revert "AArch32: Correct sdot RTL on aarch32"
This reverts commit
c9165e2d58bb037793c1c93e1b5633a61f88db30.
Tamar Christina [Thu, 15 Jul 2021 12:16:00 +0000 (13:16 +0100)]
Revert "AArch64: Correct dot-product auto-vect optab RTL"
This reverts commit
6d1cdb27828d2ef1ae1ab0209836646a269b9610.
Jakub Jelinek [Thu, 15 Jul 2021 08:17:06 +0000 (10:17 +0200)]
gimplify: Fix endless recursion on volatile empty type reads/writes [PR101437]
Andrew's recent change to optimize away during gimplification not just
assignments of zero sized types, but also assignments of empty types,
caused infinite recursion in the gimplifier.
If such assignment is optimized away, we gimplify separately the to_p
and from_p operands and throw away the result. When gimplifying the
operand that is volatile, we run into the gimplifier code below, which has
different handling for types with non-BLKmode mode, tries to gimplify
those as vol.N = expr, and for BLKmode just throws those away.
Zero sized types will always have BLKmode and so are fine, but for the
non-BLKmode ones like struct S in the testcase, the vol.N = expr
gimplification will reach again the gimplify_modify_expr code, see it is
assignment of empty type and will gimplify again vol.N separately
(non-volatile, so ok) and expr, on which it will recurse again.
The following patch breaks that infinite recursion by ignoring bare
volatile loads from empty types.
If a volatile load or store for aggregates are supposed to be member-wise
loads or stores, then there are no non-padding members in the empty types that
should be copied and so it is probably ok.
2021-07-15 Jakub Jelinek <jakub@redhat.com>
PR middle-end/101437
* gimplify.c (gimplify_expr): Throw away volatile reads from empty
types even if they have non-BLKmode TYPE_MODE.
* gcc.c-torture/compile/pr101437.c: New test.
Alan Modra [Tue, 29 Jun 2021 04:01:45 +0000 (13:31 +0930)]
[POWER10] __morestack calls from pcrel code
Compiling gcc/testsuite/gcc.dg/split-*.c and others with -mcpu=power10
and linking with a non-pcrel libgcc results in crashes due to the
power10 pcrel code not having r2 set for the generic-morestack.c
functions called from __morestack. There is also a problem when
non-pcrel code calls a pcrel libgcc. See the patch comments.
A similar situation theoretically occurs with ELFv1 multi-toc
executables, when __morestack might be located in a different toc
group to its caller. This patch makes no attempt to fix that, since
the gold linker does not support multi-toc (gold is needed for proper
support of -fsplit-stack code) nor does gcc emit __morestack calls
that support multi-toc.
* config/rs6000/morestack.S (R2_SAVE): Define.
(__morestack): Save and restore r2. Set up r2 for called
functions.
Richard Biener [Fri, 9 Jul 2021 09:13:11 +0000 (11:13 +0200)]
driver/101383 - handle -gtoggle in driver
The driver amends assembler options with for example --gdwarf-5
when debugging is enabled but the check for that does not consider
the effect of -gtoggle which is not handled in the common option
machinery. The following alters debug_info_level according to
-gtoggle mimicing what process_options later does in the compiler.
This in particular avoids changing of the cc1-checksum with every
bootstrap (debug) cycle as we compute that from stage2 where we
use -g -gtoggle but with --gdwarf-5 and no debug info from the
compiler the assembler will fill the line table with the temporary
assembler file names.
2021-07-09 Richard Biener <rguenther@suse.de>
PR driver/101383
* gcc.c (process_command): Process -gtoggle like process_options
would after parsing options.
Trevor Saunders [Thu, 15 Jul 2021 05:13:49 +0000 (01:13 -0400)]
add myself to DCO section
ChangeLog:
* MAINTAINERS: Add myself to DCO section.
Signed-off-by: Trevor Saunders <tbsaunde@tbsaunde.org>
Trevor Saunders [Mon, 12 Jul 2021 06:55:17 +0000 (02:55 -0400)]
pass location to md_asm_adjust
So the hook can use it as the location of diagnostics.
gcc/ChangeLog:
* cfgexpand.c (expand_asm_loc): Adjust.
(expand_asm_stmt): Likewise.
* config/arm/aarch-common-protos.h (arm_md_asm_adjust): Likewise.
* config/arm/aarch-common.c (arm_md_asm_adjust): Likewise.
* config/arm/arm.c (thumb1_md_asm_adjust): Likewise.
* config/avr/avr.c (avr_md_asm_adjust): Likewise.
* config/cris/cris.c (cris_md_asm_adjust): Likewise.
* config/i386/i386.c (ix86_md_asm_adjust): Likewise.
* config/mn10300/mn10300.c (mn10300_md_asm_adjust): Likewise.
* config/nds32/nds32.c (nds32_md_asm_adjust): Likewise.
* config/pdp11/pdp11.c (pdp11_md_asm_adjust): Likewise.
* config/rs6000/rs6000.c (rs6000_md_asm_adjust): Likewise.
* config/s390/s390.c (s390_md_asm_adjust): Likewise.
* config/vax/vax.c (vax_md_asm_adjust): Likewise.
* config/visium/visium.c (visium_md_asm_adjust): Likewise.
* doc/tm.texi: Regenerate.
* target.def: Add location argument to md_asm_adjust.
Signed-off-by: Trevor Saunders <tbsaunde@tbsaunde.org>
Trevor Saunders [Thu, 8 Jul 2021 01:30:03 +0000 (21:30 -0400)]
use diagnostic location in diagnostic_report_current_function
It appears that input_location was used here before the diagnostic's location
was available, and never updated, when the other part of the header was added
that uses it, so this makes it consistent.
gcc/ChangeLog:
* tree-diagnostic.c (diagnostic_report_current_function): Use the
diagnostic's location, not input_location.
Signed-off-by: Trevor Saunders <tbsaunde@tbsaunde.org>
Trevor Saunders [Thu, 8 Jul 2021 01:25:30 +0000 (21:25 -0400)]
use error_at and warning_at in cfgexpand.c
gcc/ChangeLog:
* cfgexpand.c (tree_conflicts_with_clobbers_p): Pass location to
diagnostics.
(expand_asm_stmt): Likewise.
Signed-off-by: Trevor Saunders <tbsaunde@tbsaunde.org>
Jason Merrill [Wed, 14 Jul 2021 21:10:49 +0000 (17:10 -0400)]
c++: fix tree_contains_struct for C++ types [PR101095]
Many of the types from cp-tree.def were only marked as having tree_common,
when actually most of them have type_non_common. This broke
g++.dg/modules/xtreme-header-2, as the modules code relies on
tree_contains_struct to know what bits it needs to stream.
We don't seem to use type_non_common for TYPE_ARGUMENT_PACK, so I bumped it
down to TS_TYPE_COMMON. I tried doing the same in cp_tree_size, but that
breaks without more extensive changes to tree_node_structure.
Why do we need the init_ts function anyway? It seems redundant with
tree_node_structure.
PR c++/101095
gcc/cp/ChangeLog:
* cp-objcp-common.c (cp_common_init_ts): Mark types as types.
(cp_tree_size): Remove redundant entries.
GCC Administrator [Thu, 15 Jul 2021 00:16:54 +0000 (00:16 +0000)]
Daily bump.
Peter Bergner [Wed, 14 Jul 2021 23:27:02 +0000 (18:27 -0500)]
rs6000: Generate an lxvp instead of two adjacent lxv instructions
The MMA build built-ins currently use individual lxv instructions to
load up the registers of a __vector_pair or __vector_quad. If the
memory addresses of the built-in operands are to adjacent locations,
then we can use an lxvp in some cases to load up two registers at once.
The patch below adds support for checking whether memory addresses are
adjacent and emitting an lxvp instead of two lxv instructions.
2021-07-14 Peter Bergner <bergner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.c (adjacent_mem_locations): Return the lower
addressed memory rtx, if any.
(rs6000_split_multireg_move): Fix code formatting.
Handle MMA build built-ins with operands in adjacent memory locations.
gcc/testsuite/
* gcc.target/powerpc/mma-builtin-9.c: New test.
Peter Bergner [Wed, 14 Jul 2021 23:23:31 +0000 (18:23 -0500)]
rs6000: Move rs6000_split_multireg_move to later in file
An upcoming change to rs6000_split_multireg_move requires it to be
moved later in the file to fix a declaration issue.
2021-07-14 Peter Bergner <bergner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.c (rs6000_split_multireg_move): Move to later
in the file.
Patrick Palka [Wed, 14 Jul 2021 19:37:30 +0000 (15:37 -0400)]
c++: CTAD and forwarding references [PR88252]
Here during CTAD we're incorrectly treating T&& as a forwarding
reference even though T is a template parameter of the class template.
This happens because the template parameter T in the out-of-line
definition of the constructor doesn't have the flag
TEMPLATE_TYPE_PARM_FOR_CLASS set, and during duplicate_decls the
the redeclaration (which is in terms of this unflagged T) prevails.
To fix this, we could perhaps be more consistent about setting the flag,
but it appears we don't really need this flag to make the determination.
Since the template parameters of an synthesized guide consist of the
template parameters of the class template followed by those of the
constructor (if any), it should suffice to look at the index of the
template parameter to determine whether it comes from the class
template or the constructor (template). This patch replaces the
TEMPLATE_TYPE_PARM_FOR_CLASS flag with this approach.
PR c++/88252
gcc/cp/ChangeLog:
* cp-tree.h (TEMPLATE_TYPE_PARM_FOR_CLASS): Remove.
* pt.c (push_template_decl): Remove TEMPLATE_TYPE_PARM_FOR_CLASS
handling.
(redeclare_class_template): Likewise.
(forwarding_reference_p): Define.
(maybe_adjust_types_for_deduction): Use it instead. Add 'tparms'
parameter.
(unify_one_argument): Pass tparms to
maybe_adjust_types_for_deduction.
(try_one_overload): Likewise.
(unify): Likewise.
(rewrite_template_parm): Remove TEMPLATE_TYPE_PARM_FOR_CLASS
handling.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1z/class-deduction96.C: New test.
Jason Merrill [Tue, 13 Jul 2021 18:42:09 +0000 (14:42 -0400)]
vec: use auto_vec in a few more places
The uses of vec<T> in get_all_loop_exits and process_conditional were memory
leaks, as .release() was never called for them. The other changes are some
cases that did have proper release handling, but it's simpler to leave
releasing to the auto_vec destructor.
gcc/ChangeLog:
* sel-sched-ir.h (get_all_loop_exits): Use auto_vec.
gcc/cp/ChangeLog:
* class.c (struct find_final_overrider_data): Use auto_vec.
(find_final_overrider): Remove explicit release.
* coroutines.cc (process_conditional): Use auto_vec.
* cp-gimplify.c (struct cp_genericize_data): Use auto_vec.
(cp_genericize_tree): Remove explicit release.
* parser.c (cp_parser_objc_at_property_declaration): Use
auto_delete_vec.
* semantics.c (omp_reduction_lookup): Use auto_vec.
Jason Merrill [Fri, 9 Jul 2021 09:45:03 +0000 (05:45 -0400)]
c++: enable -fdelete-dead-exceptions by default
As I was discussing with richi, I don't think it makes sense to protect
calls to pure/const functions from DCE just because they aren't explicitly
declared noexcept. PR100382 indicates that there are different
considerations for Go, which has non-call exceptions. But still turn the
flag off for that specific testcase.
gcc/c-family/ChangeLog:
* c-opts.c (c_common_post_options): Set -fdelete-dead-exceptions.
gcc/ChangeLog:
* doc/invoke.texi: -fdelete-dead-exceptions is on by default for
C++.
gcc/testsuite/ChangeLog:
* g++.dg/torture/pr100382.C: Pass -fno-delete-dead-exceptions.
Tamar Christina [Wed, 14 Jul 2021 18:00:59 +0000 (19:00 +0100)]
Vect: correct rebase issue
The lines being removed have been updated and merged into a new
condition. But when resolving some conflicts I accidentally
reintroduced them causing some test failes.
This removes them.
Committed as the changes were previously approved in
https://gcc.gnu.org/pipermail/gcc-patches/2021-July/574977.html
but the hunk was misapplied during a rebase.
gcc/ChangeLog:
* tree-vect-patterns.c (vect_recog_dot_prod_pattern):
Remove erroneous line.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/vect-reduc-dot-11.c: Expect pass.
* gcc.dg/vect/vect-reduc-dot-15.c: Likewise.
* gcc.dg/vect/vect-reduc-dot-19.c: Likewise.
* gcc.dg/vect/vect-reduc-dot-21.c: Likewise.
Andrew MacLeod [Wed, 14 Jul 2021 16:47:10 +0000 (12:47 -0400)]
Turn hybrid mode off, default to ranger-only mode for EVRP.
Change the default EVRP mode to ranger-only.
gcc/
* params.opt (param_evrp_mode): Change default.
gcc/testsuite/
* gcc.dg/pr80776-1.c: Remove xfail.
Marek Polacek [Tue, 13 Jul 2021 21:16:54 +0000 (17:16 -0400)]
c++: constexpr array reference and value-initialization [PR101371]
This PR gave me a hard time: I saw multiple issues starting with
different revisions. But ultimately the root cause seems to be
the following, and the attached patch fixes all issues I've found
here.
In cxx_eval_array_reference we create a new constexpr context for the
CP_AGGREGATE_TYPE_P case, but we also have to create it for the
non-aggregate case. In this test, we are evaluating
((B *)this)->a = rhs->a
which means that we set ctx.object to ((B *)this)->a. Then we proceed
to evaluate the initializer, rhs->a. For *rhs, we eval rhs, a PARM_DECL,
for which we have (const B &) &c.arr[0] in the hash table. Then
cxx_fold_indirect_ref gives us c.arr[0]. c is evaluated to {.arr={}} so
c.arr is {}. Now we want c.arr[0], so we end up in cxx_eval_array_reference
and since we're initializing from {}, we call build_value_init which
gives us an AGGR_INIT_EXPR that calls 'constexpr B::B()'. Then we
evaluate this AGGR_INIT_EXPR and since its first argument is dummy,
we take ctx.object instead. But that is the wrong object, we're not
initializing ((B *)this)->a here. And so we wound up with an
initializer for A, and then crash in cxx_eval_component_reference:
gcc_assert (DECL_CONTEXT (part) == TYPE_MAIN_VARIANT (TREE_TYPE (whole)));
where DECL_CONTEXT (part) is B (as it should be) but the type of whole
was A.
So create a new object, if there already was one, and the element type
is not a scalar.
PR c++/101371
gcc/cp/ChangeLog:
* constexpr.c (cxx_eval_array_reference): Create a new .object
and .ctor for the non-aggregate non-scalar case too when
value-initializing.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1y/constexpr-101371-2.C: New test.
* g++.dg/cpp1y/constexpr-101371.C: New test.
Harald Anlauf [Wed, 14 Jul 2021 15:25:29 +0000 (17:25 +0200)]
Fortran - ICE in gfc_conv_expr_present initializing non-dummy class variable
gcc/fortran/ChangeLog:
PR fortran/100949
* trans-expr.c (gfc_trans_class_init_assign): Call
gfc_conv_expr_present only for dummy variables.
gcc/testsuite/ChangeLog:
PR fortran/100949
* gfortran.dg/pr100949.f90: New test.
Tamar Christina [Wed, 14 Jul 2021 14:23:23 +0000 (15:23 +0100)]
AArch64: Correct dot-product auto-vect optab RTL
The current RTL for the vectorizer patterns for dot-product are incorrect.
Operand3 isn't an output parameter so we can't write to it.
This fixes this issue and reduces the number of RTL.
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (udot, sdot): Rename to...
(sdot_prod, udot_prod): ...These.
* config/aarch64/aarch64-simd.md (<sur>dot_prod<vsi2qi>): Remove.
(aarch64_<sur>dot<vsi2qi>): Rename to...
(<sur>dot_prod<vsi2qi>): ...This.
* config/aarch64/arm_neon.h (vdot_u32, vdotq_u32, vdot_s32, vdotq_s32):
Update builtins.
Tamar Christina [Wed, 14 Jul 2021 14:22:37 +0000 (15:22 +0100)]
AArch32: Correct sdot RTL on aarch32
The RTL Generated from <sup>dot_prod<vsi2qi> is invalid as operand3 cannot be
written to, it's a normal input. For the expand it's just another operand
but the caller does not expect it to be written to.
gcc/ChangeLog:
* config/arm/neon.md (<sup>dot_prod<vsi2qi>): Drop statements.
Tamar Christina [Wed, 14 Jul 2021 14:21:40 +0000 (15:21 +0100)]
middle-end: Add tests middle end generic tests for sign differing dotproduct.
This adds testcases to test for auto-vect detection of the new sign differing
dot product.
gcc/ChangeLog:
* doc/sourcebuild.texi (arm_v8_2a_i8mm_neon_hw): Document.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_arm_v8_2a_imm8_neon_ok_nocache,
check_effective_target_arm_v8_2a_i8mm_neon_hw,
check_effective_target_vect_usdot_qi): New.
* gcc.dg/vect/vect-reduc-dot-9.c: New test.
* gcc.dg/vect/vect-reduc-dot-10.c: New test.
* gcc.dg/vect/vect-reduc-dot-11.c: New test.
* gcc.dg/vect/vect-reduc-dot-12.c: New test.
* gcc.dg/vect/vect-reduc-dot-13.c: New test.
* gcc.dg/vect/vect-reduc-dot-14.c: New test.
* gcc.dg/vect/vect-reduc-dot-15.c: New test.
* gcc.dg/vect/vect-reduc-dot-16.c: New test.
* gcc.dg/vect/vect-reduc-dot-17.c: New test.
* gcc.dg/vect/vect-reduc-dot-18.c: New test.
* gcc.dg/vect/vect-reduc-dot-19.c: New test.
* gcc.dg/vect/vect-reduc-dot-20.c: New test.
* gcc.dg/vect/vect-reduc-dot-21.c: New test.
* gcc.dg/vect/vect-reduc-dot-22.c: New test.
Tamar Christina [Wed, 14 Jul 2021 14:20:45 +0000 (15:20 +0100)]
AArch32: Add support for sign differing dot-product usdot for NEON.
This adds optabs implementing usdot_prod.
The following testcase:
#define N 480
#define SIGNEDNESS_1 unsigned
#define SIGNEDNESS_2 signed
#define SIGNEDNESS_3 signed
#define SIGNEDNESS_4 unsigned
SIGNEDNESS_1 int __attribute__ ((noipa))
f (SIGNEDNESS_1 int res, SIGNEDNESS_3 char *restrict a,
SIGNEDNESS_4 char *restrict b)
{
for (__INTPTR_TYPE__ i = 0; i < N; ++i)
{
int av = a[i];
int bv = b[i];
SIGNEDNESS_2 short mult = av * bv;
res += mult;
}
return res;
}
Generates
f:
vmov.i32 q8, #0 @ v4si
add r3, r2, #480
.L2:
vld1.8 {q10}, [r2]!
vld1.8 {q9}, [r1]!
vusdot.s8 q8, q9, q10
cmp r3, r2
bne .L2
vadd.i32 d16, d16, d17
vpadd.i32 d16, d16, d16
vmov.32 r3, d16[0]
add r0, r0, r3
bx lr
instead of
f:
vmov.i32 q8, #0 @ v4si
add r3, r2, #480
.L2:
vld1.8 {q9}, [r2]!
vld1.8 {q11}, [r1]!
cmp r3, r2
vmull.s8 q10, d18, d22
vmull.s8 q9, d19, d23
vaddw.s16 q8, q8, d20
vaddw.s16 q8, q8, d21
vaddw.s16 q8, q8, d18
vaddw.s16 q8, q8, d19
bne .L2
vadd.i32 d16, d16, d17
vpadd.i32 d16, d16, d16
vmov.32 r3, d16[0]
add r0, r0, r3
bx lr
For NEON. I couldn't figure out if the MVE instruction vmlaldav.s16 could be
used to emulate this. Because it would require additional widening to work I
left MVE out of this patch set but perhaps someone should take a look.
gcc/ChangeLog:
* config/arm/neon.md (usdot_prod<vsi2qi>): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vusdot-autovec.c: New test.
Tamar Christina [Wed, 14 Jul 2021 14:19:32 +0000 (15:19 +0100)]
AArch64: Add support for sign differing dot-product usdot for NEON and SVE.
Hi All,
This adds optabs implementing usdot_prod.
The following testcase:
#define N 480
#define SIGNEDNESS_1 unsigned
#define SIGNEDNESS_2 signed
#define SIGNEDNESS_3 signed
#define SIGNEDNESS_4 unsigned
SIGNEDNESS_1 int __attribute__ ((noipa))
f (SIGNEDNESS_1 int res, SIGNEDNESS_3 char *restrict a,
SIGNEDNESS_4 char *restrict b)
{
for (__INTPTR_TYPE__ i = 0; i < N; ++i)
{
int av = a[i];
int bv = b[i];
SIGNEDNESS_2 short mult = av * bv;
res += mult;
}
return res;
}
Generates for NEON
f:
movi v0.4s, 0
mov x3, 0
.p2align 3,,7
.L2:
ldr q1, [x2, x3]
ldr q2, [x1, x3]
usdot v0.4s, v1.16b, v2.16b
add x3, x3, 16
cmp x3, 480
bne .L2
addv s0, v0.4s
fmov w1, s0
add w0, w0, w1
ret
and for SVE
f:
mov x3, 0
cntb x5
mov w4, 480
mov z1.b, #0
whilelo p0.b, wzr, w4
mov z3.b, #0
ptrue p1.b, all
.p2align 3,,7
.L2:
ld1b z2.b, p0/z, [x1, x3]
ld1b z0.b, p0/z, [x2, x3]
add x3, x3, x5
sel z0.b, p0, z0.b, z3.b
whilelo p0.b, w3, w4
usdot z1.s, z0.b, z2.b
b.any .L2
uaddv d0, p1, z1.s
fmov x1, d0
add w0, w0, w1
ret
instead of
f:
movi v0.4s, 0
mov x3, 0
.p2align 3,,7
.L2:
ldr q2, [x1, x3]
ldr q1, [x2, x3]
add x3, x3, 16
sxtl v4.8h, v2.8b
sxtl2 v3.8h, v2.16b
uxtl v2.8h, v1.8b
uxtl2 v1.8h, v1.16b
mul v2.8h, v2.8h, v4.8h
mul v1.8h, v1.8h, v3.8h
saddw v0.4s, v0.4s, v2.4h
saddw2 v0.4s, v0.4s, v2.8h
saddw v0.4s, v0.4s, v1.4h
saddw2 v0.4s, v0.4s, v1.8h
cmp x3, 480
bne .L2
addv s0, v0.4s
fmov w1, s0
add w0, w0, w1
ret
and
f:
mov x3, 0
cnth x5
mov w4, 480
mov z1.b, #0
whilelo p0.h, wzr, w4
ptrue p2.b, all
.p2align 3,,7
.L2:
ld1sb z2.h, p0/z, [x1, x3]
punpklo p1.h, p0.b
ld1b z0.h, p0/z, [x2, x3]
add x3, x3, x5
mul z0.h, p2/m, z0.h, z2.h
sunpklo z2.s, z0.h
sunpkhi z0.s, z0.h
add z1.s, p1/m, z1.s, z2.s
punpkhi p1.h, p0.b
whilelo p0.h, w3, w4
add z1.s, p1/m, z1.s, z0.s
b.any .L2
uaddv d0, p2, z1.s
fmov x1, d0
add w0, w0, w1
ret
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_usdot<vsi2qi>): Rename to...
(usdot_prod<vsi2qi>): ... This.
* config/aarch64/aarch64-simd-builtins.def (usdot): Rename to...
(usdot_prod): ...This.
* config/aarch64/arm_neon.h (vusdot_s32, vusdotq_s32): Likewise.
* config/aarch64/aarch64-sve.md (@aarch64_<sur>dot_prod<vsi2qi>):
Rename to...
(@<sur>dot_prod<vsi2qi>): ...This.
* config/aarch64/aarch64-sve-builtins-base.cc
(svusdot_impl::expand): Use it.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/vusdot-autovec.c: New test.
* gcc.target/aarch64/sve/vusdot-autovec.c: New test.
Tamar Christina [Wed, 14 Jul 2021 13:54:26 +0000 (14:54 +0100)]
Vect: Add support for dot-product where the sign for the multiplicant changes.
This patch adds support for a dot product where the sign of the multiplication
arguments differ. i.e. one is signed and one is unsigned but the precisions are
the same.
#define N 480
#define SIGNEDNESS_1 unsigned
#define SIGNEDNESS_2 signed
#define SIGNEDNESS_3 signed
#define SIGNEDNESS_4 unsigned
SIGNEDNESS_1 int __attribute__ ((noipa))
f (SIGNEDNESS_1 int res, SIGNEDNESS_3 char *restrict a,
SIGNEDNESS_4 char *restrict b)
{
for (__INTPTR_TYPE__ i = 0; i < N; ++i)
{
int av = a[i];
int bv = b[i];
SIGNEDNESS_2 short mult = av * bv;
res += mult;
}
return res;
}
The operations are performed as if the operands were extended to a 32-bit value.
As such this operation isn't valid if there is an intermediate conversion to an
unsigned value. i.e. if SIGNEDNESS_2 is unsigned.
more over if the signs of SIGNEDNESS_3 and SIGNEDNESS_4 are flipped the same
optab is used but the operands are flipped in the optab expansion.
To support this the patch extends the dot-product detection to optionally
ignore operands with different signs and stores this information in the optab
subtype which is now made a bitfield.
The subtype can now additionally controls which optab an EXPR can expand to.
gcc/ChangeLog:
* optabs.def (usdot_prod_optab): New.
* doc/md.texi: Document it and clarify other dot prod optabs.
* optabs-tree.h (enum optab_subtype): Add optab_vector_mixed_sign.
* optabs-tree.c (optab_for_tree_code): Support usdot_prod_optab.
* optabs.c (expand_widen_pattern_expr): Likewise.
* tree-cfg.c (verify_gimple_assign_ternary): Likewise.
* tree-vect-loop.c (vectorizable_reduction): Query dot-product kind.
* tree-vect-patterns.c (vect_supportable_direct_optab_p): Take optional
optab subtype.
(vect_widened_op_tree): Optionally ignore
mismatch types.
(vect_recog_dot_prod_pattern): Support usdot_prod_optab.
H.J. Lu [Fri, 9 Jul 2021 16:16:01 +0000 (09:16 -0700)]
x86: Don't enable UINTR in 32-bit mode
UINTR is available only in 64-bit mode. Since the codegen target is
unknown when the the gcc driver is processing -march=native, to properly
handle UINTR for -march=native:
1. Pass "arch [32|64]" and "tune [32|64]" to host_detect_local_cpu to
indicate 32-bit and 64-bit codegen.
2. Change ix86_option_override_internal to enable UINTR only in 64-bit
mode for -march=CPU when PTA_CPU includes PTA_UINTR.
gcc/
PR target/101395
* config/i386/driver-i386.c (host_detect_local_cpu): Check
"arch [32|64]" and "tune [32|64]" for 32-bit and 64-bit codegen.
Enable UINTR only for 64-bit codegen.
* config/i386/i386-options.c
(ix86_option_override_internal::DEF_PTA): Skip PTA_UINTR if not
in 64-bit mode.
* config/i386/i386.h (ARCH_ARG): New.
(CC1_CPU_SPEC): Pass "[arch|tune] 32" for 32-bit codegen and
"[arch|tune] 64" for 64-bit codegen.
gcc/testsuite/
PR target/101395
* gcc.target/i386/pr101395-1.c: New test.
* gcc.target/i386/pr101395-2.c: Likewise.
* gcc.target/i386/pr101395-3.c: Likewise.
Jonathan Wakely [Wed, 14 Jul 2021 10:03:17 +0000 (11:03 +0100)]
libstdc++: Add noexcept-specifier to basic_string_view(It, End)
This adds a conditional noexcept to the C++20 constructor. The
std::to_address call cannot throw, so only taking the difference of the
two iterators can throw.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
* include/std/string_view (basic_string_view(It, End)): Add
noexcept-specifier.
* testsuite/21_strings/basic_string_view/cons/char/range.cc:
Check noexcept-specifier. Also check construction without CTAD.
Richard Biener [Wed, 14 Jul 2021 09:06:58 +0000 (11:06 +0200)]
tree-optimization/101445 - fix negative stride SLP vect with gaps
The following fixes the IV adjustment for the gap in a negative
stride SLP vectorization. The adjustment was in the wrong direction,
now fixes as in the patch.
2021-07-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/101445
* tree-vect-stmts.c (vectorizable_load): Do the gap adjustment
of the IV in the correct direction for negative stride
accesses.
* gcc.dg/vect/pr101445.c: New testcase.
Jakub Jelinek [Wed, 14 Jul 2021 08:22:50 +0000 (10:22 +0200)]
godump: Fix -fdump-go-spec= reproduceability issue [PR101407]
pot_dummy_types is a hash_set from whose traversal the code prints some type
lines. hash_set normally uses default_hash_traits which for pointer types
(the hash set hashes const char *) uses pointer_hash which hashes the
addresses of the pointers except of the least significant 3 bits.
With address space randomization, that results in non-determinism in the
-fdump-go-specs= generated file, each invocation can have different order of
the lines emitted from pot_dummy_types traversal.
This patch fixes it by hashing the string contents instead to make the
hashes reproduceable.
2021-07-14 Jakub Jelinek <jakub@redhat.com>
PR go/101407
* godump.c (godump_str_hash): New type.
(godump_container::pot_dummy_types): Use string_hash instead of
ptr_hash in the hash_set.
Richard Biener [Tue, 13 Jul 2021 11:59:15 +0000 (13:59 +0200)]
Support reduction def re-use for epilogue with different vector size
The following adds support for re-using the vector reduction def
from the main loop in vectorized epilogue loops on architectures
which use different vector sizes for the epilogue. That's only
x86 as far as I am aware.
2021-07-13 Richard Biener <rguenther@suse.de>
* tree-vect-loop.c (vect_find_reusable_accumulator): Handle
vector types where the old vector type has a multiple of
the new vector type elements.
(vect_create_partial_epilog): New function, split out from...
(vect_create_epilog_for_reduction): ... here.
(vect_transform_cycle_phi): Reduce the re-used accumulator
to the new vector type.
* gcc.target/i386/vect-reduc-1.c: New testcase.
Alexandre Oliva [Wed, 14 Jul 2021 01:25:56 +0000 (22:25 -0300)]
fix typo in attr_fnspec::verify
Odd-numbered indices describing argument access sizes in the fnspec
string can only hold 't' or a digit, as tested in the beginning of the
case. When checking that the size-supplying argument does not have
additional information associated with it, the test that excludes the
't' possibility looks for it at the even position in the fnspec
string. Oops.
This might yield false positives and negatives if a function has a
fnspec in which an argument uses a 't' access-size, and ('t' - '1')
happens to be the index of an argument described in an fnspec string.
Assuming ASCII encoding, it would take a function with at least 68
arguments described in fnspec. Still, probably worth fixing.
for gcc/ChangeLog
* tree-ssa-alias.c (attr_fnspec::verify): Fix index in
non-'t'-sized arg check.
Alexandre Oliva [Wed, 14 Jul 2021 01:25:54 +0000 (22:25 -0300)]
adjust landing pads when changing main label
If an artificial label created for a landing pad ends up being
dropped in favor of a user-supplied label, the user-supplied label
inherits the landing pad index, but the post_landing_pad field is not
adjusted to point to the new label.
This patch fixes the problem, and adds verification that we don't
remove a label that's still used as a landing pad.
The circumstance in which this problem can be hit was unusual: removal
of a block with an unreachable label moves the label to some other
unrelated block, in case its address is taken. In the case at hand
(pr42739.C, complicated by wrappers and cleanups), the chosen block
happened to be an EH landing pad. (A followup patch will change that.)
for gcc/ChangeLog
* tree-cfg.c (cleanup_dead_labels_eh): Update
post_landing_pad label upon change of landing pad block's
primary label.
(cleanup_dead_labels): Check that a removed label is not that
of a landing pad.
GCC Administrator [Wed, 14 Jul 2021 00:16:44 +0000 (00:16 +0000)]
Daily bump.
Jonathan Wright [Wed, 2 Jun 2021 15:55:00 +0000 (16:55 +0100)]
gcc: Add vec_select -> subreg RTL simplification
Add a new RTL simplification for the case of a VEC_SELECT selecting
the low part of a vector. The simplification returns a SUBREG.
The primary goal of this patch is to enable better combinations of
Neon RTL patterns - specifically allowing generation of 'write-to-
high-half' narrowing intructions.
Adding this RTL simplification means that the expected results for a
number of tests need to be updated:
* aarch64 Neon: Update the scan-assembler regex for intrinsics tests
to expect a scalar register instead of lane 0 of a vector.
* aarch64 SVE: Likewise.
* arm MVE: Use lane 1 instead of lane 0 for lane-extraction
intrinsics tests (as the move instructions get optimized away for
lane 0.)
This patch also adds new code generation tests to
narrow_high_combine.c to verify the benefit of this RTL
simplification.
gcc/ChangeLog:
2021-06-08 Jonathan Wright <jonathan.wright@arm.com>
* combine.c (combine_simplify_rtx): Add vec_select -> subreg
simplification.
* config/aarch64/aarch64.md (*zero_extend<SHORT:mode><GPI:mode>2_aarch64):
Add Neon to general purpose register case for zero-extend
pattern.
* config/arm/vfp.md (*arm_movsi_vfp): Remove "*" from *t -> r
case to prevent some cases opting to go through memory.
* cse.c (fold_rtx): Add vec_select -> subreg simplification.
* rtl.c (rtvec_series_p): Define predicate to determine
whether a vector contains a linear series of integers.
* rtl.h (rtvec_series_p): Define.
* rtlanal.c (vec_series_lowpart_p): Define predicate to
determine if a vector selection is equivalent to the low part
of the vector.
* rtlanal.h (vec_series_lowpart_p): Define.
* simplify-rtx.c (simplify_context::simplify_binary_operation_1):
Add vec_select -> subreg simplification.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/extract_zero_extend.c: Remove dump scan
for RTL pattern match.
* gcc.target/aarch64/narrow_high_combine.c: Add new tests.
* gcc.target/aarch64/simd/vmulx_laneq_f64_1.c: Update
scan-assembler regex to look for a scalar register instead of
lane 0 of a vector.
* gcc.target/aarch64/simd/vmulxd_laneq_f64_1.c: Likewise.
* gcc.target/aarch64/simd/vmulxs_lane_f32_1.c: Likewise.
* gcc.target/aarch64/simd/vmulxs_laneq_f32_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmullh_laneq_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqdmulls_laneq_s32.c: Likewise.
* gcc.target/aarch64/sve/dup_lane_1.c: Likewise.
* gcc.target/aarch64/sve/extract_1.c: Likewise.
* gcc.target/aarch64/sve/extract_2.c: Likewise.
* gcc.target/aarch64/sve/extract_3.c: Likewise.
* gcc.target/aarch64/sve/extract_4.c: Likewise.
* gcc.target/aarch64/sve/live_1.c: Update scan-assembler regex
cases to look for 'b' and 'h' registers instead of 'w'.
* gcc.target/arm/crypto-vsha1cq_u32.c: Update scan-assembler
regex to reflect lane 0 vector extractions being simplified
to scalar register moves.
* gcc.target/arm/crypto-vsha1h_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1mq_u32.c: Likewise.
* gcc.target/arm/crypto-vsha1pq_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c: Extract
lane 1 as the moves for lane 0 now get optimized away.
* gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c: Likewise.
Paul A. Clarke [Tue, 29 Jun 2021 14:23:39 +0000 (09:23 -0500)]
rs6000: Add tests for SSE4.1 "test" intrinsics
Copy the test for _mm_testz_si128, _mm_testc_si128,
_mm_testnzc_si128, _mm_test_all_ones, _mm_test_all_zeros,
_mm_test_mix_ones_zeros from gcc/testsuite/gcc.target/i386.
2021-07-13 Paul A. Clarke <pc@us.ibm.com>
gcc/testsuite
* gcc.target/powerpc/sse4_1-ptest-1.c: Copy from
gcc/testsuite/gcc.target/i386.
Paul A. Clarke [Tue, 29 Jun 2021 14:18:55 +0000 (09:18 -0500)]
rs6000: Add support for SSE4.1 "test" intrinsics
2021-07-13 Paul A. Clarke <pc@us.ibm.com>
gcc
* config/rs6000/smmintrin.h (_mm_testz_si128, _mm_testc_si128,
_mm_testnzc_si128, _mm_test_all_ones, _mm_test_all_zeros,
_mm_test_mix_ones_zeros): New.
Jonathan Wakely [Tue, 13 Jul 2021 11:21:27 +0000 (12:21 +0100)]
libstdc++: Simplify basic_string_view::ends_with [PR 101361]
The use of npos triggers a diagnostic as described in PR c++/101361.
This change replaces the use of npos with the exact length, which is
already known. We can further simplify it by inlining the effects of
compare and substr, avoiding the redundant range checks in the latter.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
PR c++/101361
* include/std/string_view (ends_with): Use traits_type::compare
directly.
Andrew MacLeod [Tue, 13 Jul 2021 13:41:30 +0000 (09:41 -0400)]
Adjust testcase to test the call is removed.
Ranger now handles the test.
gcc/testsuite
PR tree-optimization/93781
* gcc.dg/tree-ssa/pr93781-1.c: Check that call is removed.
Roger Sayle [Tue, 13 Jul 2021 13:01:41 +0000 (14:01 +0100)]
Make gimple_could_trap_p const-safe.
Allow gimple_could_trap_p (which previously took a non-const gimple)
to be called from functions that take a const gimple (such as
gimple_has_side_effects), and update its prototypes. Pre-approved
as obvious.
2021-07-13 Roger Sayle <roger@nextmovesoftware.com>
Richard Biener <rguenther@suse.de>
gcc/ChangeLog
* gimple.c (gimple_could_trap_p_1): Make S argument a
"const gimple*". Preserve constness in call to
gimple_asm_volatile_p.
(gimple_could_trap_p): Make S argument a "const gimple*".
* gimple.h (gimple_could_trap_p_1, gimple_could_trap_p):
Update function prototypes.
Jonathan Wakely [Tue, 13 Jul 2021 11:09:37 +0000 (12:09 +0100)]
libstdc++: Remove duplicate #include in <string_view>
When I added the new C++23 constructor I added a conditional include of
<bits/ranges_base.h>, which was already being included unconditionally.
This removes the unconditional include but changes the condition for the
other one, so it's used for C++20 as well.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
* include/std/string_view: Only include <bits/ranges_base.h>
once, and only for C++20 and later.
Richard Sandiford [Tue, 13 Jul 2021 09:17:43 +0000 (10:17 +0100)]
vect: Reuse reduction accumulators between loops
This patch adds support for reusing a main loop's reduction accumulator
in an epilogue loop. This in turn lets the loops share a single piece
of vector->scalar reduction code.
The patch has the following restrictions:
(1) The epilogue reduction can only operate on a single vector
(e.g. ncopies must be 1 for non-SLP reductions, and the group size
must be <= the element count for SLP reductions).
(2) Both loops must use the same vector mode for their accumulators.
This means that the patch is restricted to targets that support
--param vect-partial-vector-usage=1.
(3) The reduction must be a standard “tree code” reduction.
However, these restrictions could be lifted in future. For example,
if the main loop operates on 128-bit vectors and the epilogue loop
operates on 64-bit vectors, we could in future reduce the 128-bit
vector by one stage and use the 64-bit result as the starting point
for the epilogue result.
The patch tries to handle chained SLP reductions, unchained SLP
reductions and non-SLP reductions. It also handles cases in which
the epilogue loop is entered directly (rather than via the main loop)
and cases in which the epilogue loop can be skipped.
vect_get_main_loop_result is a bit more general than the current
patch needs.
gcc/
* tree-vectorizer.h (vect_reusable_accumulator): New structure.
(_loop_vec_info::main_loop_edge): New field.
(_loop_vec_info::skip_main_loop_edge): Likewise.
(_loop_vec_info::skip_this_loop_edge): Likewise.
(_loop_vec_info::reusable_accumulators): Likewise.
(_stmt_vec_info::reduc_scalar_results): Likewise.
(_stmt_vec_info::reused_accumulator): Likewise.
(vect_get_main_loop_result): Declare.
* tree-vectorizer.c (vec_info::new_stmt_vec_info): Initialize
reduc_scalar_inputs.
(vec_info::free_stmt_vec_info): Free reduc_scalar_inputs.
* tree-vect-loop-manip.c (vect_get_main_loop_result): New function.
(vect_do_peeling): Fill an epilogue loop's main_loop_edge,
skip_main_loop_edge and skip_this_loop_edge fields.
* tree-vect-loop.c (INCLUDE_ALGORITHM): Define.
(vect_emit_reduction_init_stmts): New function.
(get_initial_def_for_reduction): Use it.
(get_initial_defs_for_reduction): Likewise. Change the vinfo
parameter to a loop_vec_info.
(vect_create_epilog_for_reduction): Store the scalar results
in the reduc_info. If an epilogue loop is reusing an accumulator
from the main loop, and if the epilogue loop can also be skipped,
try to place the reduction code in the join block. Record
accumulators that could potentially be reused by epilogue loops.
(vect_transform_cycle_phi): When vectorizing epilogue loops,
try to reuse accumulators from the main loop. Record the initial
value in reduc_info for non-SLP reductions too.
gcc/testsuite/
* gcc.target/aarch64/sve/reduc_9.c: New test.
* gcc.target/aarch64/sve/reduc_9_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_10.c: Likewise.
* gcc.target/aarch64/sve/reduc_10_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_11.c: Likewise.
* gcc.target/aarch64/sve/reduc_11_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_12.c: Likewise.
* gcc.target/aarch64/sve/reduc_12_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_13.c: Likewise.
* gcc.target/aarch64/sve/reduc_13_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_14.c: Likewise.
* gcc.target/aarch64/sve/reduc_14_run.c: Likewise.
* gcc.target/aarch64/sve/reduc_15.c: Likewise.
* gcc.target/aarch64/sve/reduc_15_run.c: Likewise.
Richard Sandiford [Tue, 13 Jul 2021 09:17:42 +0000 (10:17 +0100)]
vect: Simplify get_initial_def_for_reduction
After previous patches, we can now easily provide the neutral op
as an argument to get_initial_def_for_reduction. This in turn
allows the adjustment calculation to be moved outside of
get_initial_def_for_reduction, which is the main motivation
of the patch.
gcc/
* tree-vect-loop.c (get_initial_def_for_reduction): Remove
adjustment handling. Take the neutral value as an argument,
in place of the code argument.
(vect_transform_cycle_phi): Update accordingly. Handle the
initial values of cond reductions separately from code reductions.
Choose the adjustment here rather than in
get_initial_def_for_reduction. Sink the splat of vec_initial_def.
Richard Sandiford [Tue, 13 Jul 2021 09:17:41 +0000 (10:17 +0100)]
vect: Generalise neutral_op_for_slp_reduction
This patch generalises the interface to neutral_op_for_slp_reduction
so that it can be used for non-SLP reductions too. This isn't much
of a win on its own, but it helps later patches.
gcc/
* tree-vect-loop.c (neutral_op_for_slp_reduction): Replace with...
(neutral_op_for_reduction): ...this, providing a more general
interface.
(vect_create_epilog_for_reduction): Update accordingly.
(vectorizable_reduction): Likewise.
(vect_transform_cycle_phi): Likewise.
Richard Sandiford [Tue, 13 Jul 2021 09:17:40 +0000 (10:17 +0100)]
vect: Pass reduc_info to get_initial_def_for_reduction
Similarly to the previous patch, this one passes the reduc_info
to get_initial_def_for_reduction, rather than a stmt_vec_info that
lacks the metadata. This again becomes useful later.
gcc/
* tree-vect-loop.c (get_initial_def_for_reduction): Take the
reduc_info instead of the original stmt_vec_info.
(vect_transform_cycle_phi): Update accordingly.
Richard Sandiford [Tue, 13 Jul 2021 09:17:39 +0000 (10:17 +0100)]
vect: Pass reduc_info to get_initial_defs_for_reduction
This patch passes the reduc_info to get_initial_defs_for_reduction,
so that the function can get general information from there rather
than from the first SLP statement. This isn't a win on its own,
but it becomes important with later patches.
gcc/
* tree-vect-loop.c (get_initial_defs_for_reduction): Take the
reduc_info as an additional parameter.
(vect_transform_cycle_phi): Update accordingly.
Richard Sandiford [Tue, 13 Jul 2021 09:17:39 +0000 (10:17 +0100)]
vect: Add a vect_phi_initial_value helper function
This patch adds a helper function called vect_phi_initial_value
for returning the incoming value of a given loop phi. The main
reason for adding it is to ensure that the right preheader edge
is used when vectorising nested loops. (PHI_ARG_DEF_FROM_EDGE
itself doesn't assert that the given edge is for the right block,
although I guess that would be good to add separately.)
gcc/
* tree-vectorizer.h: Include tree-ssa-operands.h.
(vect_phi_initial_value): New function.
* tree-vect-loop.c (neutral_op_for_slp_reduction): Use it.
(get_initial_defs_for_reduction, info_for_reduction): Likewise.
(vect_create_epilog_for_reduction, vectorizable_reduction): Likewise.
(vect_transform_cycle_phi, vectorizable_induction): Likewise.
Richard Sandiford [Tue, 13 Jul 2021 09:17:38 +0000 (10:17 +0100)]
vect: Ensure reduc_inputs always have vectype
Vector reduction accumulators can differ in signedness from the
final scalar result. The conversions to handle that case were
distributed through vect_create_epilog_for_reduction; this patch
does the conversion up-front instead.
gcc/
* tree-vect-loop.c (vect_create_epilog_for_reduction): Convert
the phi results to vectype after creating them. Remove later
conversion code that thus becomes redundant.
Richard Sandiford [Tue, 13 Jul 2021 09:17:37 +0000 (10:17 +0100)]
vect: Remove new_phis from vect_create_epilog_for_reduction
vect_create_epilog_for_reduction had a variable called new_phis.
It collected the statements that produce the exit block definitions
of the vector reduction accumulators. Although those statements
are indeed phis initially, they are often replaced with normal
statements later, leading to puzzling code like:
FOR_EACH_VEC_ELT (new_phis, i, new_phi)
{
int bit_offset;
if (gimple_code (new_phi) == GIMPLE_PHI)
vec_temp = PHI_RESULT (new_phi);
else
vec_temp = gimple_assign_lhs (new_phi);
Also, although the array collects statements, in practice all users want
the lhs instead.
This patch therefore replaces new_phis with a vector of gimple values
called “reduc_inputs”.
Also, reduction chains and ncopies>1 were handled with identical code
(and there was a comment saying so). The patch unites them into
a single “if”.
gcc/
* tree-vect-loop.c (vect_create_epilog_for_reduction): Replace
the new_phis vector with a reduc_inputs vector. Combine handling
of reduction chains and ncopies > 1.
Richard Sandiford [Tue, 13 Jul 2021 09:17:36 +0000 (10:17 +0100)]
vect: Create array_slice of live-out stmts
This patch constructs an array_slice of the scalar statements that
produce live-out reduction results in the original unvectorised loop.
There are three cases:
- SLP reduction chains: the final SLP stmt is live-out
- full SLP reductions: all SLP stmts are live-out
- non-SLP reductions: the single scalar stmt is live-out
This is a slight simplification on its own, mostly because it maans
“group_size” has a consistent meaning throughout the function.
The main justification though is that it helps with later patches.
gcc/
* tree-vect-loop.c (vect_create_epilog_for_reduction): Truncate
scalar_results to group_size elements after reducing down from
N*group_size elements. Construct an array_slice of the live-out
stmts and assert that there is one stmt per scalar result.
Richard Sandiford [Tue, 13 Jul 2021 09:17:35 +0000 (10:17 +0100)]
vect: Simplify epilogue reduction code
vect_create_epilog_for_reduction only handles two cases: single-loop
reductions and double reductions. “nested cycles” (i.e. reductions
in the inner loop when vectorising an outer loop) are handled elsewhere
and don't need a vector->scalar reduction.
The function had variables called nested_in_vect_loop and double_reduc
and asserted that nested_in_vect_loop implied double_reduc, but it
still had code to handle nested_in_vect_loop && !double_reduc.
This patch removes that and uses double_reduc everywhere.
gcc/
* tree-vect-loop.c (vect_create_epilog_for_reduction): Remove
nested_in_vect_loop and use double_reduc everywhere. Remove dead
assignment to "loop".
Richard Sandiford [Tue, 13 Jul 2021 09:17:34 +0000 (10:17 +0100)]
ifcvt: Improve tests for predicated operations
-msve-vector-bits=128 causes the AArch64 port to list 128-bit Advanced
SIMD as the first-choice mode for vectorisation, with SVE being used for
things that Advanced SIMD can't handle as easily. However, ifcvt would
not then try to use SVE's predicated FP arithmetic, leading to tests
like TSVC ControlFlow-flt failing to vectorise.
The mask load/store code did try other vector modes, but could also be
improved to make sure that SVEness sticks when computing derived modes.
(Unlike mode_for_vector, related_vector_mode always returns a vector
mode, so there's no need to check VECTOR_MODE_P as well.)
gcc/
* internal-fn.c (vectorized_internal_fn_supported_p): Handle
vector types first. For scalar types, consider both the preferred
vector mode and the alternative vector modes.
* optabs-query.c (can_vec_mask_load_store_p): Use the same
structure as above, in particular using related_vector_mode
for modes provided by autovectorize_vector_modes.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_arith_6.c: New test.
Jakub Jelinek [Tue, 13 Jul 2021 09:04:22 +0000 (11:04 +0200)]
passes: Fix up subobject __bos [PR101419]
The following testcase is miscompiled, because VN during cunrolli changes
__bos argument from address of a larger field to address of a smaller field
and so __builtin_object_size (, 1) then folds into smaller value than the
actually available size.
copy_reference_ops_from_ref has a hack for this, but it was using
cfun->after_inlining as a check whether the hack can be ignored, and
cunrolli is after_inlining.
This patch uses a property to make it exact (set at the end of objsz
pass that doesn't do insert_min_max_p) and additionally based on discussions
in the PR moves the objsz pass earlier after IPA.
2021-07-13 Jakub Jelinek <jakub@redhat.com>
Richard Biener <rguenther@suse.de>
PR tree-optimization/101419
* tree-pass.h (PROP_objsz): Define.
(make_pass_early_object_sizes): Declare.
* passes.def (pass_all_early_optimizations): Rename pass_object_sizes
there to pass_early_object_sizes, drop parameter.
(pass_all_optimizations): Move pass_object_sizes right after pass_ccp,
drop parameter, move pass_post_ipa_warn right after that.
* tree-object-size.c (pass_object_sizes::execute): Rename to...
(object_sizes_execute): ... this. Add insert_min_max_p argument.
(pass_data_object_sizes): Move after object_sizes_execute.
(pass_object_sizes): Likewise. In execute method call
object_sizes_execute, drop set_pass_param method and insert_min_max_p
non-static data member and its initializer in the ctor.
(pass_data_early_object_sizes, pass_early_object_sizes,
make_pass_early_object_sizes): New.
* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Use
(cfun->curr_properties & PROP_objsz) instead of cfun->after_inlining.
* gcc.dg/builtin-object-size-10.c: Pass -fdump-tree-early_objsz-details
instead of -fdump-tree-objsz1-details in dg-options and adjust names
of dump file in scan-tree-dump.
* gcc.dg/pr101419.c: New test.
Jakub Jelinek [Tue, 13 Jul 2021 07:50:49 +0000 (09:50 +0200)]
libgomp: Don't include limits.h instead of hidden visibility block
sem.h is included in between # pragma GCC visibility push(hidden)
and # pragma GCC visibility pop and includes limits.h there, which
since the introduction of sysconf declaration in recent glibcs
in there causes trouble. libgomp assumes it is compiled by gcc,
so we don't really need to include limits.h there and can use
-__INT_MAX__ - 1 instead (which clang and icc support too for years).
2021-07-13 Jakub Jelinek <jakub@redhat.com>
Florian Weimer <fweimer@redhat.com>
* config/linux/sem.h: Don't include limits.h.
(SEM_WAIT): Define to -__INT_MAX__ - 1 instead of INT_MIN.
* config/linux/affinity.c: Include limits.h.
Kito Cheng [Fri, 2 Jul 2021 02:19:30 +0000 (10:19 +0800)]
docs: Add 'S' to Machine Constraints for RISC-V
It was undocument before, but it might used in linux kernel for resolve
code model issue, so LLVM community suggest we should document that,
so that make it become supported/documented/non-internal machine constraints.
gcc/ChangeLog:
PR target/101275
* config/riscv/constraints.md ("S"): Update description and remove
@internal.
* doc/md.texi (Machine Constraints): Document the 'S' constraints
for RISC-V.
Richard Biener [Tue, 13 Jul 2021 06:04:34 +0000 (08:04 +0200)]
Revert "Display the number of components BB vectorized"
This reverts commit
c03cae4e066066278c8435c409829a9bf851e49f.
Michael Meissner [Tue, 13 Jul 2021 04:36:43 +0000 (00:36 -0400)]
Deal with prefixed loads/stores in tests, PR testsuite/100166
This patch updates the various tests in the testsuite to treat plxv
and pstxv as being vector loads/stores. This shows up if you run the
testsuite with a compiler configured with the option: --with-cpu=power10.
2021-07-13 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
PR testsuite/100166
* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c: Update
insn counts to account for power10 prefixed loads and stores.
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c:
Likewise.
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_xl-char.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_xl-double.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_xl-float.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_xl-int.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c: Likewise.
* gcc.target/powerpc/fold-vec-load-vec_xl-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-floatdouble.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-longlong.c: Likewise.
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c:
Likewise.
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_xst-char.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_xst-double.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_xst-float.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_xst-int.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c: Likewise.
* gcc.target/powerpc/fold-vec-store-vec_xst-short.c: Likewise.
* gcc.target/powerpc/lvsl-lvsr.c: Likewise.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Likewise.
Michael Meissner [Tue, 13 Jul 2021 03:51:24 +0000 (23:51 -0400)]
Fix vec-splati-runnable.c test.
I noticed that the vec-splati-runnable.c did not have an abort after one
of the tests. If the test was run with optimization, the optimizer could
delete some of the tests and throw off the count. However, due to the
fact that the value being loaded in that test is undefined, I did not
check what value was loaded, but I just stored it into a volatile global
variable.
2021-07-12 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
* gcc.target/powerpc/vec-splati-runnable.c: Run test with -O2
optimization. Do not check what XXSPLTIDP generates if the value
is undefined.
Michael Meissner [Tue, 13 Jul 2021 03:50:38 +0000 (23:50 -0400)]
Change rs6000_const_f32_to_i32 return type.
The function rs6000_const_f32_to_i32 called REAL_VALUE_TO_TARGET_SINGLE
with a long long type and returns it. This patch changes the type to long
which is the proper type for REAL_VALUE_TO_TARGET_SINGLE.
2021-07-12 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/altivec.md (xxspltiw_v4sf): Change local variable
value to to long.
* config/rs6000/rs6000-protos.h (rs6000_const_f32_to_i32): Change
return type to long.
* config/rs6000/rs6000.c (rs6000_const_f32_to_i32): Change return
type to long.
GCC Administrator [Tue, 13 Jul 2021 00:16:30 +0000 (00:16 +0000)]
Daily bump.
Andrew MacLeod [Mon, 12 Jul 2021 18:38:42 +0000 (14:38 -0400)]
Add relation processing to ubsan builtins.
Ubsan builtins call the plus/minus/multiple fold routines, but did not
use any relation information between the 2 operands that is available.
query and pass any relations.
This resolves gcc.dg/pr97505.c when operating in ranger-only mode.
* gimple-range-fold.cc (fold_using_range::range_of_builtin_ubsan_call):
Query relation between the 2 operands and use it.
Sergei Trofimovich [Mon, 12 Jul 2021 22:45:38 +0000 (23:45 +0100)]
docs: fix s/ei_safe_safe/ei_safe_edge/ typo
gcc/ChangeLog:
* doc/cfg.texi: Fix s/ei_safe_safe/ei_safe_edge/ typo.
Patrick Palka [Mon, 12 Jul 2021 20:35:18 +0000 (16:35 -0400)]
c++: permit deduction guides at class scope [PR79501]
This adds support for declaring (class-scope) deduction guides for a
member class template. Fortunately it seems only a couple of changes
are needed in order for the existing CTAD machinery to handle them
properly: we need to make sure to give them a FUNCTION_TYPE instead of a
METHOD_TYPE, and we need to avoid using a BASELINK when looking them up.
PR c++/79501
PR c++/100983
gcc/cp/ChangeLog:
* decl.c (grokfndecl): Don't require that deduction guides are
declared at namespace scope. Check that class-scope deduction
guides have the same access as the member class template.
(grokdeclarator): Pretend class-scope deduction guides are static.
* search.c (lookup_member): Don't use a BASELINK for (class-scope)
deduction guides.
gcc/testsuite/ChangeLog:
* g++.dg/cpp1z/class-deduction92.C: New test.
* g++.dg/cpp1z/class-deduction93.C: New test.
* g++.dg/cpp1z/class-deduction94.C: New test.
* g++.dg/cpp1z/class-deduction95.C: New test.
Uros Bizjak [Mon, 12 Jul 2021 19:06:32 +0000 (21:06 +0200)]
i386: Fix vec_set<mode> expanders [PR101424]
AVX does not support 32-byte integer compares, required by
ix86_expand_vector_set_var. The following patch fixes vec_set<mode>
expanders by introducing new vec_setm_avx2_operand predicate for AVX
vector modes.
gcc/
2021-07-12 Uroš Bizjak <ubizjak@gmail.com>
PR target/101424
* config/i386/predicates.md (vec_setm_sse41_operand):
Rename from vec_setm_operand.
(vec_setm_avx2_operand): New predicate.
* config/i386/sse.md (vec_set<V_128:mode>): Use V_128 mode iterator.
Use vec_setm_sse41_operand as operand 2 predicate.
(vec_set<V_256_512:mode): New expander.
* config/i386/mmx.md (vec_setv2hi): Use vec_setm_sse41_operand
as operand 2 predicate.
gcc/testsuite/
2021-07-12 Uroš Bizjak <ubizjak@gmail.com>
PR target/101424
* gcc.target/i386/pr101424.c: New test.
Andrew MacLeod [Mon, 12 Jul 2021 15:38:17 +0000 (11:38 -0400)]
Do not register a cast as an equivalence.
Registering an equivalence between objects of the same size in a cast can
cause other relations to be incorrect.
gcc/
PR tree-optimization/101335
* range-op.cc (operator_cast::lhs_op1_relation): Delete.
gcc/testsuite/
* gcc.dg/tree-ssa/pr101335.c: New.
Jonathan Wakely [Mon, 12 Jul 2021 15:09:34 +0000 (16:09 +0100)]
libstdc++: Constrain std::as_writable_bytes [PR101411]
The std::as_writable_bytes function should be constrained to only accept
writable spans. Currently it can be called but then gives an error in
the function body.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
PR libstdc++/101411
* include/std/span (as_writable_bytes): Add requires-clause.
* testsuite/23_containers/span/101411.cc: New test.
Andrew Pinski [Fri, 9 Jul 2021 02:23:35 +0000 (19:23 -0700)]
[PHIOPT/MATCH] Remove the statement to move if not used
Instead of waiting for DCE to remove the unused statement,
and maybe optimize another conditional, it is better if
we don't move the statement and have the statement
removed.
OK? Bootstrapped and tested on x86_64-linux-gnu.
Changes from v1:
* v2: Change the order of insertation and check to see if the lhs
is used rather than see if the lhs was used in the sequence.
gcc/ChangeLog:
* tree-ssa-phiopt.c (match_simplify_replacement): Move
insert of the sequence before the movement of the
statement. Check if to see if the statement is used
outside of the original phi to see if we should move it.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr96928-1.c: Update to similar as pr96928.c.
Richard Biener [Mon, 12 Jul 2021 13:13:17 +0000 (15:13 +0200)]
produce simple DOT graphs from SLP trees
This adds a dot_slp_tree debug function producing a simple DOT
graph from a starting node down the graph. There's no fancy
direct invocation of dot but the output is directed to a specified
file. It re-uses vect_print_slp_tree, naming nodes as their
address.
2021-07-12 Richard Biener <rguenther@suse.de>
* dump-context.h (debug_dump_context::debug_dump_context):
Add FILE * parameter defaulted to stderr.
* dumpfile.c (debug_dump_context::debug_dump_context): Adjust.
* tree-vect-slp.c (dot_slp_tree): New functions.
Richard Biener [Thu, 8 Jul 2021 07:52:49 +0000 (09:52 +0200)]
tree-optimization/101373 - avoid PRE across externally throwing call
PRE already tries to avoid hoisting possibly trapping expressions
across calls that might not return normally but fails to consider
const calls that throw externally. The following fixes that and
also plugs the hole of trapping references not pruned in case
they are not catched by the actuall call clobbering it.
At -Os we hit the same issue in RTL PRE and postreload-gcse has
even more incomplete checks so the patch adjusts both of those
as well.
2021-07-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/101373
* tree-ssa-pre.c (prune_clobbered_mems): Also prune trapping
references when the BB may not return.
(compute_avail): Pass in the function we're working on and
replace cfun references with it. Externally throwing
const calls also possibly terminate the function.
(pass_pre::execute): Pass down the function we're working on.
* gcse.c (compute_hash_table_work): Externally throwing
const/pure calls also need record_last_mem_set_info.
* postreload-gcse.c (record_opr_changes): Looping or externally
throwing const/pure calls also need record_last_mem_set_info.
* g++.dg/torture/pr101373.C: New testcase, XFAILed.
* gnat.dg/opt95.adb: Likewise.
Uros Bizjak [Mon, 12 Jul 2021 14:34:41 +0000 (16:34 +0200)]
Change the type of memory classification functions to bool
2021-07-12 Uroš Bizjak <ubizjak@gmail.com>
gcc/
* recog.c (memory_address_addr_space_p): Change the type to bool.
Return true/false instead of 1/0.
(offsettable_memref_p): Ditto.
(offsettable_nonstrict_memref_p): Ditto.
(offsettable_address_addr_space_p): Ditto.
Change the type of addressp indirect function to bool.
* recog.h (memory_address_addr_space_p): Change the type to bool.
(strict_memory_address_addr_space_p): Ditto.
(offsettable_memref_p): Ditto.
(offsettable_nonstrict_memref_p): Ditto.
(offsettable_address_addr_space_p): Ditto.
* reload.c (maybe_memory_address_addr_space_p): Ditto.
(strict_memory_address_addr_space_p): Change the type to bool.
Return true/false instead of 1/0.
(maybe_memory_address_addr_space_p): Change the type to bool.
Pierre-Marie de Rodat [Fri, 25 Jun 2021 09:22:19 +0000 (09:22 +0000)]
[Ada] adaint.c minor reformatting
gcc/ada/
* adaint.c (__gnat_number_of_cpus): Replace "#ifdef" by "#if
defined".
Eric Botcazou [Fri, 4 Jun 2021 16:22:17 +0000 (18:22 +0200)]
[Ada] Use GNAT encodings only when -fgnat-encodings=all is specified
gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_entity) <discrete_type>: Add a
parallel type only when -fgnat-encodings=all is specified.
<E_Array_Type>: Use the PAT name and special suffixes only when
-fgnat-encodings=all is specified.
<E_Array_Subtype>: Build a special type for debugging purposes only
when -fgnat-encodings=all is specified. Add a parallel type or use
the PAT name only when -fgnat-encodings=all is specified.
<E_Record_Type>: Generate debug info for the inner record types only
when -fgnat-encodings=all is specified.
<E_Record_Subtype>: Use a debug type for an artificial subtype only
except when -fgnat-encodings=all is specified.
(elaborate_expression_1): Reset need_for_debug when possible only
except when -fgnat-encodings=all is specified.
(components_to_record): Use XV encodings for variable size only
when -fgnat-encodings=all is specified.
(associate_original_type_to_packed_array): Add a parallel type only
when -fgnat-encodings=all is specified.
* gcc-interface/misc.c (gnat_get_array_descr_info): Do not return
full information only when -fgnat-encodings=all is specified.
* gcc-interface/utils.c (make_packable_type): Add a parallel type
only when -fgnat-encodings=all is specified.
(maybe_pad_type): Make the inner type a debug type only except when
-fgnat-encodings=all is specified. Create an XVS type for variable
size only when -fgnat-encodings=all is specified.
(rest_of_record_type_compilation): Add a parallel type only when
-fgnat-encodings=all is specified.
Eric Botcazou [Tue, 27 Apr 2021 19:18:12 +0000 (21:18 +0200)]
[Ada] Implement support for unconstrained array types with FLB
gcc/ada/
* gcc-interface/decl.c (gnat_to_gnu_entity) <E_Array_Type>: Use a
fixed lower bound if the index subtype is marked so, as well as a
more efficient formula for the upper bound if the array cannot be
superflat.
(flb_cannot_be_superflat): New predicate.
(cannot_be_superflat): Rename into...
(range_cannot_be_superfla): ...this. Minor tweak.
Bob Duff [Tue, 15 Jun 2021 13:12:36 +0000 (09:12 -0400)]
[Ada] Clean up Uint fields
gcc/ada/
* uintp.ads, types.h: New subtypes of Uint: Valid_Uint, Unat,
Upos, Nonzero_Uint with predicates. These correspond to new
field types in Gen_IL.
* gen_il-types.ads (Valid_Uint, Unat, Upos, Nonzero_Uint): New
field types.
* einfo-utils.ads, einfo-utils.adb, fe.h (Known_Alignment,
Init_Alignment): Use the initial zero value to represent
"unknown". This will ensure that if Alignment is called before
Set_Alignment, the compiler will blow up (if assertions are
enabled).
* atree.ads, atree.adb, atree.h, gen_il-gen.adb
(Get_Valid_32_Bit_Field): New generic low-level getter for
subtypes of Uint.
(Copy_Alignment): New procedure to copy Alignment field even
when Unknown.
(Init_Object_Size_Align, Init_Size_Align): Do not bypass the
Init_ procedures.
* exp_pakd.adb, freeze.adb, layout.adb, repinfo.adb,
sem_util.adb: Protect calls to Alignment with Known_Alignment.
Use Copy_Alignment when it might be unknown.
* gen_il-gen-gen_entities.adb (Alignment,
String_Literal_Length): Use type Unat instead of Uint, to ensure
that the field is always Set_ before we get it, and that it is
set to a nonnegative value.
(Enumeration_Pos): Unat.
(Enumeration_Rep): Valid_Uint. Can be negative, but must be
valid before fetching.
(Discriminant_Number): Upos.
(Renaming_Map): Remove.
* gen_il-gen-gen_nodes.adb (Char_Literal_Value, Reason): Unat.
(Intval, Corresponding_Integer_Value): Valid_Uint.
* gen_il-internals.ads: New functions for dealing with special
defaults and new subtypes of Uint.
* scans.ads: Correct comments.
* scn.adb (Post_Scan): Do not set Intval to No_Uint; that is no
longer allowed.
* sem_ch13.adb (Analyze_Enumeration_Representation_Clause): Do
not set Enumeration_Rep to No_Uint; that is no longer allowed.
(Offset_Value): Protect calls to Alignment with Known_Alignment.
* sem_prag.adb (Set_Atomic_VFA): Do not use Uint_0 to mean
"unknown"; call Init_Alignment instead.
* sinfo.ads: Minor comment fix.
* treepr.adb: Deal with printing of new field types.
* einfo.ads, gen_il-fields.ads (Renaming_Map): Remove.
* gcc-interface/decl.c (gnat_to_gnu_entity): Use Known_Alignment
before calling Alignment. This preserve some probably buggy
behavior: if the alignment is not set, it previously defaulted
to Uint_0; we now make that explicit. Use Copy_Alignment,
because "Set_Alignment (Y, Alignment (X));" no longer works when
the Alignment of X has not yet been set.
* gcc-interface/trans.c (process_freeze_entity): Use
Copy_Alignment.
Eric Botcazou [Fri, 18 Jun 2021 14:47:48 +0000 (16:47 +0200)]
[Ada] Add DWARF 5 support to System.Dwarf_Line
gcc/ada/
* libgnat/s-dwalin.ads: Adjust a few comments left and right.
(Line_Info_Register): Comment out unused components.
(Line_Info_Header): Add DWARF 5 support.
(Dwarf_Context): Likewise. Rename "prologue" into "header".
* libgnat/s-dwalin.adb: Alphabetize "with" clauses.
(DWARF constants): Add DWARF 5 support and reorder.
(For_Each_Row): Adjust.
(Initialize_Pass): Likewise.
(Initialize_State_Machine): Likewise and fix typo.
(Open): Add DWARF 5 support.
(Parse_Prologue): Rename into...
(Parse_Header): ...this and add DWARF 5 support.
(Read_And_Execute_Isn): Rename into...
(Read_And_Execute_Insn): ...this and adjust.
(To_File_Name): Change parameter name and add DWARF 5 support.
(Read_Entry_Format_Array): New procedure.
(Skip_Form): Add DWARF 5 support and reorder.
(Seek_Abbrev): Do not count entries and add DWARF 5 support.
(Debug_Info_Lookup): Add DWARF 5 support.
(Symbolic_Address.Set_Result): Likewise.
(Symbolic_Address): Adjust.
Bob Duff [Wed, 16 Jun 2021 10:47:57 +0000 (06:47 -0400)]
[Ada] Duplicate Size/Value_Size clause
gcc/ada/
* sem_ch13.adb (Duplicate_Clause): Add a helper routine
Check_One_Attr, with a parameter for the attribute_designator we
are looking for, and one for the attribute_designator of the
current node (which are usually the same). For Size and
Value_Size, call it twice, once for each.
* errout.ads: Fix a typo.
Piotr Trojanek [Thu, 17 Jun 2021 16:49:11 +0000 (18:49 +0200)]
[Ada] Avoid unnecessary work when expanding 'Image into 'Put_Image
gcc/ada/
* exp_imgv.adb (Expand_Image_Attribute): Move rewriting to
attribute Put_Image to the beginning of expansion of attribute
Image.
Richard Biener [Wed, 7 Jul 2021 09:45:43 +0000 (11:45 +0200)]
Display the number of components BB vectorized
This amends the optimization message printed when a basic-block
part is vectorized to mention the number of SLP graph entries.
This helps when debugging vectorization differences and we end up
merging SLP instances for costing purposes.
2021-07-07 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_slp_region): Show the number of
SLP graph entries in the optimization message.
* g++.dg/vect/slp-pr87105.cc: Adjust.
* gcc.dg/vect/bb-slp-pr54400.c: Likewise.
Richard Biener [Mon, 12 Jul 2021 08:49:03 +0000 (10:49 +0200)]
tree-optimization/101394 - fix PRE full redundancy wrt abnormals
This avoids adding a copy from an abnormal picked up from PHI
translation much like we'd avoid inserting the translated
expression on pred edges.
2021-07-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/101394
* tree-ssa-pre.c (do_pre_regular_insertion): Avoid inserting
copies from abnormals for a full redundancy.
* gcc.dg/torture/pr101394.c: New testcase.
Richard Biener [Mon, 12 Jul 2021 08:26:25 +0000 (10:26 +0200)]
middle-end/101423 - internal calls do not trap
This adjusts gimple_could_trap_p to not consider internal function
calls to trap compared to indirect calls or calls to weak functions.
2021-07-12 Richard Biener <rguenther@suse.de>
PR middle-end/101423
* gimple.c (gimple_could_trap_p_1): Internal function calls
do not trap.
* tree-eh.c (tree_could_trap_p): Likewise.
Roger Sayle [Mon, 12 Jul 2021 09:59:08 +0000 (10:59 +0100)]
Tweak testcase for PR tree-optimization/101403.
Initialize unused variable u in compound expression. Committed as obvious.
2021-07-12 Roger Sayle <roger@nextmovesoftware.com>
Jakub Jelinek <jakub@redhat.com>
gcc/testsuite/ChangeLog
PR tree-optimization/101403
* gcc.dg/pr101403.c: Avoid (unimportant) uninitialized variable.
prathamesh.kulkarni [Mon, 12 Jul 2021 09:48:21 +0000 (15:18 +0530)]
arm/66791: Replace builtins for unsigned and fp vmul_n intrinsics.
gcc/ChangeLog:
PR target/66791
* config/arm/arm_neon.h (vmul_n_u32): Replace call to builtin with
__a * __b.
(vmulq_n_u32): Likewise.
(vmul_n_f32): Gate __a * __b on __FAST_MATH__.
(vmulq_n_f32): Likewise.
(vmul_n_f16): Likewise.
(vmulq_n_f16): Likewise.
gcc/testsuite/ChangeLog:
PR target/66791
* gcc.target/arm/armv8_2-fp16-neon-2.c: Adjust.
Martin Liska [Mon, 12 Jul 2021 08:59:06 +0000 (10:59 +0200)]
offloading: fix -foffload hinting
PR sanitizer/101425
gcc/ChangeLog:
* gcc.c (check_offload_target_name): Call
candidates_list_and_hint only if we have a candidate.
prathamesh.kulkarni [Mon, 12 Jul 2021 07:53:06 +0000 (13:23 +0530)]
arm/98435: Missed optimization in expanding vector constructor.
The patch moves vec_init pattern from neon.md to vec-common.md,
and adjusts the mode to VDQX to accomodate binary floats. Also,
the pattern is additionally gated on VALID_MVE_MODE.
gcc/ChangeLog:
PR target/98435
* config/arm/neon.md (vec_init): Move to ...
* config/arm/vec-common.md (vec_init): ... here.
Change the pattern's mode to VDQX and gate it on VALID_MVE_MODE.
gcc/testsuite/ChangeLog:
PR target/98435
* gcc.target/arm/simd/pr98435.c: New test.
Roger Sayle [Mon, 12 Jul 2021 07:24:27 +0000 (08:24 +0100)]
PR tree-optimization/101403: Incorrect folding of ((T)bswap(x))>>C
My sincere apologies for the breakage. My recent patch to fold
bswapN(x)>>C where the constant C was large enough that the result
only contains bits from the low byte, and can therefore avoid
the byte swap contains a minor logic error. The pattern contains
a convert? allowing an extension to occur between the bswap and
the shift. The logic is correct if there's no extension, or the
extension has the same sign as the shift, but I'd mistakenly
convinced myself that these couldn't have different signedness.
(T)bswap16(x)>>12 is (T)((unsigned char)x>>4) or (T)((signed char)x>>4).
The bug is that for zero-extensions to signed type T, we need to use
the unsigned char variant [the signedness of the byte shift is not
(always) the same as the signedness of T and the original shift].
Then because I'm now paranoid, I've also added a clause to handle
the hypothetical (but in practice impossible) sign-extension to an
unsigned type T, which can implemented as (T)(x<<8)>>12.
2021-07-12 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR tree-optimization/101403
* match.pd ((T)bswap(X)>>C): Correctly handle cases where
signedness of the shift is not the same as the signedness of
the type extension.
gcc/testsuite/ChangeLog
PR tree-optimization/101403
* gcc.dg/pr101403.c: New test case.
GCC Administrator [Mon, 12 Jul 2021 00:16:29 +0000 (00:16 +0000)]
Daily bump.