Alyssa Rosenzweig [Sat, 23 Oct 2021 14:13:51 +0000 (10:13 -0400)]
panfrost: Flush resources when shadowing
When we shadow a resource, the backing BO is changed; as such,
existing references to the resource become invalid. So batches accessing the
resource need to be flushed (or otherwise have their references invalidated).
The wrong behaviour change (not flushing) was introduced when we started
tracking resources instead of BOs. The issue manifested as a severe performance
regression in glmark2's -bbuffer test, particular the subdata subtest. The issue
is magnified on slow CPUs; without the fix, the test becomes completely CPU
bound
Relevant glmark2 -bbuffer test from 43fps to 84fps.
Apparently, this causes functional issues too -- this performance-minded change
also fixes a few piglits.
Fixes:
cecb889481d ("panfrost: Do tracking of resources, not BOs")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Chris Healy <cphealy@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13502>
Alyssa Rosenzweig [Tue, 28 Sep 2021 00:26:54 +0000 (20:26 -0400)]
panfrost: Handle NULL samplers
Fixes a NULL dereference in Piglit fp-fragment-position, getting the
test to pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
Alyssa Rosenzweig [Tue, 28 Sep 2021 00:24:01 +0000 (20:24 -0400)]
panfrost: Handle NULL sampler views
Fixes a NULL dereference in Piglit fp-fragment-position.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
Alyssa Rosenzweig [Tue, 28 Sep 2021 00:24:38 +0000 (20:24 -0400)]
panfrost: Fix set_sampler_views for big GL
Roughly use the freedreno logic to handle all the extra things that will
come up in our Piglit sooner than later.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
Alyssa Rosenzweig [Thu, 24 Feb 2022 22:43:31 +0000 (17:43 -0500)]
panfrost/ci: Update xfails list
These tests seem to be passing now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13203>
Kenneth Graunke [Thu, 24 Feb 2022 18:16:27 +0000 (10:16 -0800)]
blorp: Add blorp_measure hooks to the blitter codepaths
I had missed these when hooking up the original support.
Fixes:
31eeb72e45b ("blorp: Add support for blorp_copy via XY_BLOCK_COPY_BLT")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15157>
Kenneth Graunke [Fri, 18 Feb 2022 11:02:53 +0000 (03:02 -0800)]
iris: Set MI_FLUSH_DW::PostSyncOperation correctly
The MI_FLUSH_DW post-sync operation uses the same encoding as the
PIPE_CONTROL one so we can use the same helper. Write PS Depth Count
is not supported, of course, as the blitter has no depth pipeline.
This means that we can write the timestamp register from the blitter.
Fixes:
604d97671b6 ("iris: Add support for flushing the blitter (hackily)")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15157>
Pavel Ondračka [Fri, 18 Feb 2022 10:48:23 +0000 (11:48 +0100)]
r300: add predicate instructions to statistics of vertex shaders
All of IF, ELSE, ENDIF, BREAK and CONTINUE were already translated
to the predication instructions in rc_vert_fc so all the flow control
we count at the moment is just BGNLOOP and ENDLOOP.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
Pavel Ondračka [Fri, 18 Feb 2022 08:32:00 +0000 (09:32 +0100)]
r300: report number of loops in shader statistics
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
Pavel Ondračka [Fri, 18 Feb 2022 07:53:53 +0000 (08:53 +0100)]
r300: use %u specifiers when printing unsigned stats values
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6019
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
Pavel Ondračka [Fri, 18 Feb 2022 07:48:23 +0000 (08:48 +0100)]
r300: only print shader statistics when compilation succeeds
This allows to disregard the huge shaders that won't run anyway
and hopefully make catching shader regressions that result in a
compile failure easier.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15077>
Mike Blumenkrantz [Wed, 23 Feb 2022 02:11:46 +0000 (21:11 -0500)]
zink: add a flake channel
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15129>
Alyssa Rosenzweig [Thu, 24 Feb 2022 18:36:24 +0000 (13:36 -0500)]
pan/bi: Unit test message preloading optimization
To make sure it is applied in the cases we expect it to be, to avoid code
generation regressions. Functional regressions are expected to be caught by
integration-testing, so that is not focused on here.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Alyssa Rosenzweig [Wed, 23 Feb 2022 18:50:54 +0000 (13:50 -0500)]
pan/bi: Support message preloading
Preload LD_VAR_IMM or VAR_TEX instructions in the first block of fragment
shaders on v7. Preloaded messages write to fixed registers; when replacing
instructions we insert moves from the registers at the start of the program and
hope coalescing goes to town. (Admittedly we don't do any coalescing yet...)
The extra moves hurts instruction count in some cases; the win for cycle count
should cancel this out. When we get smarter copy prop or RA, those moves should
go away anyway.
This optimization may hurt register pressure by extending the lifetime of up to
eight registers written in the first block. This is expected to be acceptable:
on a large shader-db, there are no additional spills/fills, and only two shaders
are hurt on thread count.
This optimization only applies to v7, as the hardware was not introduced on v6
and was removed for Valhall.
total instructions in shared programs: 2451624 -> 2454286 (0.11%)
instructions in affected programs: 909046 -> 911708 (0.29%)
helped: 4719
HURT: 3341
helped stats (abs) min: 1.0 max: 10.0 x̄: 1.49 x̃: 1
helped stats (rel) min: 0.08% max: 33.33% x̄: 6.79% x̃: 3.92%
HURT stats (abs) min: 1.0 max: 50.0 x̄: 2.90 x̃: 2
HURT stats (rel) min: 0.12% max: 66.67% x̄: 6.39% x̃: 3.45%
95% mean confidence interval for instructions value: 0.27 0.39
95% mean confidence interval for instructions %-change: -1.55% -1.11%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total tuples in shared programs: 1969529 -> 1963429 (-0.31%)
tuples in affected programs: 601327 -> 595227 (-1.01%)
helped: 5907
HURT: 1297
helped stats (abs) min: 1.0 max: 8.0 x̄: 1.41 x̃: 1
helped stats (rel) min: 0.07% max: 33.33% x̄: 7.25% x̃: 5.26%
HURT stats (abs) min: 1.0 max: 40.0 x̄: 1.73 x̃: 1
HURT stats (rel) min: 0.16% max: 31.75% x̄: 3.38% x̃: 2.02%
95% mean confidence interval for tuples value: -0.88 -0.81
95% mean confidence interval for tuples %-change: -5.52% -5.15%
Tuples are helped.
total clauses in shared programs: 401689 -> 387830 (-3.45%)
clauses in affected programs: 136944 -> 123085 (-10.12%)
helped: 8427
HURT: 4
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.65 x̃: 2
helped stats (rel) min: 0.49% max: 50.00% x̄: 19.88% x̃: 18.18%
HURT stats (abs) min: 1.0 max: 4.0 x̄: 2.50 x̃: 2
HURT stats (rel) min: 1.96% max: 19.05% x̄: 14.18% x̃: 17.86%
95% mean confidence interval for clauses value: -1.66 -1.63
95% mean confidence interval for clauses %-change: -20.15% -19.58%
Clauses are helped.
total cycles in shared programs: 202735.83 -> 201862.21 (-0.43%)
cycles in affected programs: 16295.46 -> 15421.83 (-5.36%)
helped: 3349
HURT: 1962
helped stats (abs) min: 0.
041665999999999315 max: 1.0 x̄: 0.32 x̃: 0
helped stats (rel) min: 0.24% max: 100.00% x̄: 40.77% x̃: 33.33%
HURT stats (abs) min: 0.
041665999999999315 max: 1.
5833329999999997 x̄: 0.10 x̃: 0
HURT stats (rel) min: 0.09% max: 31.40% x̄: 2.95% x̃: 1.94%
95% mean confidence interval for cycles value: -0.17 -0.16
95% mean confidence interval for cycles %-change: -25.48% -23.76%
Cycles are helped.
total arith in shared programs: 74665.50 -> 74920.00 (0.34%)
arith in affected programs: 16059.92 -> 16314.42 (1.58%)
helped: 860
HURT: 3409
helped stats (abs) min: 0.
041665999999999315 max: 0.25 x̄: 0.06 x̃: 0
helped stats (rel) min: 0.24% max: 37.50% x̄: 4.73% x̃: 2.56%
HURT stats (abs) min: 0.
041665999999999315 max: 1.
5833329999999997 x̄: 0.09 x̃: 0
HURT stats (rel) min: 0.09% max: 100.00% x̄: 8.99% x̃: 4.21%
95% mean confidence interval for arith value: 0.06 0.06
95% mean confidence interval for arith %-change: 5.83% 6.62%
Arith are HURT.
total texture in shared programs: 13083.50 -> 11877 (-9.22%)
texture in affected programs: 1663 -> 456.50 (-72.55%)
helped: 2377
HURT: 3
helped stats (abs) min: 0.5 max: 1.0 x̄: 0.51 x̃: 0
helped stats (rel) min: 6.25% max: 100.00% x̄: 87.12% x̃: 100.00%
HURT stats (abs) min: 0.5 max: 0.5 x̄: 0.50 x̃: 0
HURT stats (rel) min: 0.00% max: 25.00% x̄: 16.67% x̃: 25.00%
95% mean confidence interval for texture value: -0.51 -0.50
95% mean confidence interval for texture %-change: -87.98% -86.00%
Texture are helped.
total vary in shared programs: 10220.62 -> 4183.88 (-59.06%)
vary in affected programs: 10126.50 -> 4089.75 (-59.61%)
helped: 8538
HURT: 0
helped stats (abs) min: 0.125 max: 1.0 x̄: 0.71 x̃: 0
helped stats (rel) min: 7.14% max: 100.00% x̄: 74.74% x̃: 87.50%
95% mean confidence interval for vary value: -0.71 -0.70
95% mean confidence interval for vary %-change: -75.32% -74.16%
Vary are helped.
total quadwords in shared programs: 1766717 -> 1757161 (-0.54%)
quadwords in affected programs: 553801 -> 544245 (-1.73%)
helped: 6760
HURT: 711
helped stats (abs) min: 1.0 max: 11.0 x̄: 1.58 x̃: 1
helped stats (rel) min: 0.09% max: 29.41% x̄: 5.31% x̃: 4.84%
HURT stats (abs) min: 1.0 max: 33.0 x̄: 1.54 x̃: 1
HURT stats (rel) min: 0.10% max: 31.13% x̄: 2.53% x̃: 1.61%
95% mean confidence interval for quadwords value: -1.31 -1.25
95% mean confidence interval for quadwords %-change: -4.67% -4.46%
Quadwords are helped.
total threads in shared programs: 52899 -> 52897 (<.01%)
threads in affected programs: 4 -> 2 (-50.00%)
helped: 0
HURT: 2
total preloads in shared programs: 0 -> 116492
preloads in affected programs: 0 -> 116492
helped: 0
HURT: 8604
HURT stats (abs) min: 2.0 max: 24.0 x̄: 13.54 x̃: 14
HURT stats (rel) min: 0.00% max: 0.00% x̄: 0.00% x̃: 0.00%
95% mean confidence interval for preloads value: 13.45 13.63
95% mean confidence interval for preloads %-change: 0.00% 0.00%
Preloads are HURT.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Alyssa Rosenzweig [Wed, 23 Feb 2022 18:49:54 +0000 (13:49 -0500)]
pan/bi: Account for message preloading in shaderdb
If a message-passing instruction like LD_VAR is preloaded, it will no longer be
counted in the shader cycle counts. Add a special message preload counter that
approximates the cost of preloading, so this information doesn't get a lost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Alyssa Rosenzweig [Wed, 23 Feb 2022 18:47:08 +0000 (13:47 -0500)]
pan/bi: Add bi_before_nonempty_block helper
To be used in the message preloading pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Alyssa Rosenzweig [Wed, 23 Feb 2022 18:49:16 +0000 (13:49 -0500)]
panfrost: Pack message preloads from compiler
Include full message preload descriptors in the RSD on v7, and do the obvious
packing for fragment shader message preloads.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Alyssa Rosenzweig [Wed, 23 Feb 2022 18:47:37 +0000 (13:47 -0500)]
panfrost: Add an unpacked message preload struct
The compiler will soon produce preloaded messages, but it should not pack them
itself, as this would require depending on GenXML or handcoding bitfields / bit
packs in the compiler. Instead, add a struct encoding the unpacked form of the
message, used as ABI between the compiler and the common driver.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Alyssa Rosenzweig [Tue, 22 Feb 2022 21:01:17 +0000 (16:01 -0500)]
panfrost: Remove Message Preload Descriptor from v6.xml
It is an anachronism, as this descriptor was added in v7 and, seemingly, removed
immediately after. Good work.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9438>
Igor Torrente [Thu, 17 Feb 2022 13:57:51 +0000 (10:57 -0300)]
venus: add macros to help with future extensions
Currently we have to add almost the same code to the
`vn_physical_device_init_{features, properties}` to add
the extension to the `physical_dev->{features, properties}`
list.
These macros improves the code reusage.
Signed-off-by: Igor Torrente <igor.torrente@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15059>
Alyssa Rosenzweig [Thu, 24 Feb 2022 14:49:13 +0000 (09:49 -0500)]
panfrost/ci: Move T860 flake to skip
Actually an xfail but occassionally passes and gives us no new information, only
noise.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-and-acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15154>
Alyssa Rosenzweig [Thu, 24 Feb 2022 14:47:05 +0000 (09:47 -0500)]
panfrost/ci: Move T720 flakes to skips
Doesn't seem like these will be resolved anytime soon..
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-and-acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15154>
Tomeu Vizoso [Thu, 24 Feb 2022 12:44:09 +0000 (13:44 +0100)]
Revert "ci: Disable jobs to the Collabora lab"
This reverts commit
f692bda484384a5932dc42ce940ad3ea6b9a8741.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15153>
Iago Toral Quiroga [Thu, 17 Feb 2022 09:29:14 +0000 (10:29 +0100)]
broadcom/compiler: move uniforms right before their first use after scheduling
On V3D the quality of the code we generate is significantly affected by
how we decide to assign accumulators during register allocation, which
is determined by liveness, favoring short-lived temps.
There are many shaders that end up doing a whole lot of uniform loads
first, and using them later, which is very inconvenient for our register
allocation process because this increases uniform liveness and causes
us to use accumulators less efficientely, leading to significant churn.
To fix this, we move uniforms right before their first use in the same
block, but we need to do this after NIR scheduling, which means we are
doing it in non-SSA form, since the scheduler has a tendency to undo
this optimization and it is not easy to modify it to avoid it, since it
works in more abstract terms, using instruction dependencies, estimated
register pressure and instruction delay information to do its work,
which are very different concepts.
total instructions in shared programs:
13316738 ->
13033613 (-2.13%)
instructions in affected programs:
10389172 ->
10106047 (-2.73%)
helped: 55442
HURT: 16144
total threads in shared programs: 413722 -> 415048 (0.32%)
threads in affected programs: 1428 -> 2754 (92.86%)
helped: 680
HURT: 17
total loops in shared programs: 1716 -> 1690 (-1.52%)
loops in affected programs: 26 -> 0
helped: 26
HURT: 0
total uniforms in shared programs: 3704313 -> 3705181 (0.02%)
uniforms in affected programs: 687730 -> 688598 (0.13%)
helped: 2920
HURT: 7384
total max-temps in shared programs: 2364785 -> 2175190 (-8.02%)
max-temps in affected programs: 1215387 -> 1025792 (-15.60%)
helped: 49667
HURT: 1556
total spills in shared programs: 4241 -> 4248 (0.17%)
spills in affected programs: 642 -> 649 (1.09%)
helped: 11
HURT: 19
total fills in shared programs: 6115 -> 6125 (0.16%)
fills in affected programs: 1276 -> 1286 (0.78%)
helped: 11
HURT: 21
total sfu-stalls in shared programs: 34381 -> 36578 (6.39%)
sfu-stalls in affected programs: 16055 -> 18252 (13.68%)
helped: 3647
HURT: 5206
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
Iago Toral Quiroga [Fri, 18 Feb 2022 10:23:32 +0000 (11:23 +0100)]
nir/nir_opt_move: handle non-SSA defs
We just skip register defs and avoid moving register reads across them.
This allows us to run this pass in non-SSA form.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
Iago Toral Quiroga [Thu, 17 Feb 2022 09:25:48 +0000 (10:25 +0100)]
nir: add a nir_instr_def_is_register helper
This returns true if the instruction has a dest that is not an SSA value.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
Iago Toral Quiroga [Thu, 17 Feb 2022 09:14:45 +0000 (10:14 +0100)]
nir/nir_opt_move: allow to move uniform loads
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15056>
Tomeu Vizoso [Thu, 24 Feb 2022 06:34:09 +0000 (07:34 +0100)]
ci: Disable jobs to the Collabora lab
In anticipation of infrastructure work.
This commit is to be reverted later in the day.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15150>
Tomeu Vizoso [Thu, 24 Feb 2022 05:40:20 +0000 (06:40 +0100)]
ci: Allow disabling the whole of the Collabora farm
Add a global-level variable that allows disabling all jobs that would
have gone to the Collabora lab, to be used in case of outages.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15150>
Emma Anholt [Wed, 23 Feb 2022 01:46:55 +0000 (17:46 -0800)]
ci/lvp: Update the asan fails list.
Many tests had been fixed but weren't being run due to test reshuffles
from uprevs. Add some explanations for what remains.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15133>
Alyssa Rosenzweig [Sat, 11 Dec 2021 17:54:01 +0000 (12:54 -0500)]
pan/bi: Reorder pushed uniforms to avoid moves
On Bifrost and Valhall, push uniforms are loaded into Fast Access Uniform
Random Access Memory (FAU-RAM). FAU-RAM is organized as an array of 64-bit
slots. A given tuple (Bifrost) or instruction (Valhall) may access at most a
single 64-bit slot. If an instruction requires uniforms from multiple 64-bit
slots, a uniform-to-register move must be inserted to avoid the hazard. However,
if an instruction requires a pair of 32-bit uniforms from the same 64-bit slot,
no move is required.
To reduce the number of moves we emit, this commit adds an optimization pass
that reorders pushed uniforms, trying to group uniforms used by the same
instruction. The pass works by creating a graph of pushed uniforms, where edges
denote the "both 32-bit uniforms required by the same instruction" relationship.
We perform depth-first search on this graph to find the connected components,
where each connected component is a cluster of uniforms that are used together.
We then select pairs of uniforms from each connected component. The remaining
unpaired uniforms (from components of odd sizes) are paired together
arbitrarily.
In principle, we should weight the graph by number of occurences and choose
pairs that maximize the total selected edge weight. This is left for
future work, as it is nontrivial -- selecting these edges optimally appears to
be NP-hard at first blush.
Implementation note: As position and varying shaders share FAU on Bifrost, extra
care is taken with a `push_offset` shader stage info parameter that ensures
varying shaders do not reorder uniforms selected by the previous position
shader.
total instructions in shared programs: 2503343 -> 2451758 (-2.06%)
instructions in affected programs: 1553309 -> 1501724 (-3.32%)
helped: 14256
HURT: 8
helped stats (abs) min: 1.0 max: 80.0 x̄: 3.62 x̃: 3
helped stats (rel) min: 0.06% max: 36.36% x̄: 7.31% x̃: 6.67%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.38 x̃: 1
HURT stats (rel) min: 1.30% max: 12.50% x̄: 4.99% x̃: 3.85%
95% mean confidence interval for instructions value: -3.66 -3.58
95% mean confidence interval for instructions %-change: -7.41% -7.20%
Instructions are helped.
total tuples in shared programs: 2008399 -> 1969627 (-1.93%)
tuples in affected programs: 1146344 -> 1107572 (-3.38%)
helped: 12867
HURT: 147
helped stats (abs) min: 1.0 max: 61.0 x̄: 3.03 x̃: 2
helped stats (rel) min: 0.17% max: 42.86% x̄: 6.79% x̃: 4.65%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.20 x̃: 1
HURT stats (rel) min: 0.29% max: 20.00% x̄: 2.12% x̃: 1.19%
95% mean confidence interval for tuples value: -3.03 -2.93
95% mean confidence interval for tuples %-change: -6.82% -6.57%
Tuples are helped.
total clauses in shared programs: 408005 -> 401708 (-1.54%)
clauses in affected programs: 90760 -> 84463 (-6.94%)
helped: 6006
HURT: 164
helped stats (abs) min: 1.0 max: 9.0 x̄: 1.08 x̃: 1
helped stats (rel) min: 0.45% max: 33.33% x̄: 12.44% x̃: 14.29%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 1.64% max: 25.00% x̄: 9.81% x̃: 5.26%
95% mean confidence interval for clauses value: -1.03 -1.01
95% mean confidence interval for clauses %-change: -12.03% -11.66%
Clauses are helped.
total cycles in shared programs: 203308.37 -> 202737.83 (-0.28%)
cycles in affected programs: 19264.71 -> 18694.17 (-2.96%)
helped: 3024
HURT: 41
helped stats (abs) min: 0.
041665999999999315 max: 2.
5416680000000014 x̄: 0.19 x̃: 0
helped stats (rel) min: 0.17% max: 33.33% x̄: 3.83% x̃: 2.83%
HURT stats (abs) min: 0.
041665999999999315 max: 0.125 x̄: 0.06 x̃: 0
HURT stats (rel) min: 0.30% max: 5.88% x̄: 1.41% x̃: 0.93%
95% mean confidence interval for cycles value: -0.19 -0.18
95% mean confidence interval for cycles %-change: -3.89% -3.64%
Cycles are helped.
total arith in shared programs: 76265.67 -> 74669.25 (-2.09%)
arith in affected programs: 45001.50 -> 43405.08 (-3.55%)
helped: 12945
HURT: 97
helped stats (abs) min: 0.
041665999999999315 max: 2.
5416680000000014 x̄: 0.12 x̃: 0
helped stats (rel) min: 0.17% max: 50.00% x̄: 8.06% x̃: 4.88%
HURT stats (abs) min: 0.
041665999999999315 max: 0.125 x̄: 0.05 x̃: 0
HURT stats (rel) min: 0.21% max: 33.33% x̄: 2.16% x̃: 0.96%
95% mean confidence interval for arith value: -0.12 -0.12
95% mean confidence interval for arith %-change: -8.16% -7.81%
Arith are helped.
total quadwords in shared programs: 1796563 -> 1766803 (-1.66%)
quadwords in affected programs: 948830 -> 919070 (-3.14%)
helped: 12078
HURT: 219
helped stats (abs) min: 1.0 max: 42.0 x̄: 2.49 x̃: 2
helped stats (rel) min: 0.10% max: 33.33% x̄: 5.57% x̃: 5.26%
HURT stats (abs) min: 1.0 max: 4.0 x̄: 1.21 x̃: 1
HURT stats (rel) min: 0.33% max: 6.67% x̄: 2.00% x̃: 1.14%
95% mean confidence interval for quadwords value: -2.46 -2.38
95% mean confidence interval for quadwords %-change: -5.52% -5.36%
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14163>
Timothy Arceri [Wed, 16 Feb 2022 03:41:45 +0000 (14:41 +1100)]
glsl/nir: free GLSL IR right after we convert to NIR
Gives us memory back faster which is useful for pathalogical CTS
tests.
The GLSL IR was previously used after converting to NIR for things
like building the GL resource list but we have had a NIR version
for this for some time and I don't believe there are any other
use cases left for keeping the old IR hanging around this long.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15127>
Emma Anholt [Wed, 9 Feb 2022 21:56:31 +0000 (13:56 -0800)]
ci/virgl: Drop the bvec4_from_mat4x2_vs xfail.
The fix has landed in VK-GL-CTS 1.3.1.0, we were just not noticing it
because this is also in the flakes list.
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14962>
Emma Anholt [Tue, 8 Feb 2022 21:48:52 +0000 (13:48 -0800)]
ci/softpipe: Move most of testing to shared 64-core runners at Google.
The single job takes about 3:30 of runner time. I don't have a good
explanation for the crash->fail test changes.
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14962>
Emma Anholt [Tue, 8 Feb 2022 21:12:42 +0000 (13:12 -0800)]
ci/lavapipe: Test 1/3 of lavapipe on the shared 64-core google runners.
Now we can get through 1/3 of the testsuite in about 3:30, while
previously we did 1/10th.
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14962>
Emma Anholt [Tue, 8 Feb 2022 20:37:37 +0000 (12:37 -0800)]
ci/llvmpipe: Move most of testing to shared 64-core runners at Google.
These runners are configured to have a single job take up the whole
runner, which means we get to use threads to our hearts content. The pile
of cores means we don't need to spawn separate jobs to try to load-balance
across fdo's shared runner capacity. Having dedicated runners means we
won't get our MRs blocked as much waiting on non-Mesa testing happening on
fd.o.
We manage to complete all of this llvmpipe testing in about 6:15.
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14962>
Emma Anholt [Tue, 8 Feb 2022 20:52:56 +0000 (12:52 -0800)]
ci: Stash the ldd and ccache stats output under collapsed sections.
You rarely need to look at these, they're just nice to have sometimes.
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14962>
Samuel Pitoiset [Thu, 28 Oct 2021 13:50:31 +0000 (15:50 +0200)]
radv: initialize extra state for internal pipelines at one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14650>
Samuel Pitoiset [Thu, 28 Oct 2021 12:50:10 +0000 (14:50 +0200)]
radv: remove useless radv_blend_state::single_cb_enable field
This was only used for meta operations. DCC/FMASK/FCE pipelines
only declare one color attachment and the color writemask of the
second color attachment is 0 for the HW CB resolve.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14650>
Samuel Pitoiset [Thu, 28 Oct 2021 13:27:38 +0000 (15:27 +0200)]
radv: initialize VGT_GS_OUT_PRIM_TYPE earlier
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14650>
Samuel Pitoiset [Thu, 28 Oct 2021 13:17:59 +0000 (15:17 +0200)]
radv: initialize more depth/stencil states earlier
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14650>
Dmitry Baryshkov [Wed, 16 Feb 2022 22:15:12 +0000 (01:15 +0300)]
freedreno/regs: remove 5nm DSI PHY regs
5nm PHY is a variation of 7nm PHY, they use the same register
definitions. To remove duplication, drop 5nm defs.
Cc: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15051>
Eric Engestrom [Wed, 23 Feb 2022 19:05:20 +0000 (19:05 +0000)]
docs: update calendar and link releases notes for 21.3.7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15149>
Eric Engestrom [Wed, 23 Feb 2022 18:19:19 +0000 (18:19 +0000)]
docs: add release notes for 21.3.7
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15149>
Dave Airlie [Wed, 23 Feb 2022 01:35:52 +0000 (11:35 +1000)]
draw/so: don't use pre clip pos if we have a tes either.
This check for geom shader needed to be expanded for tess support.
dEQP-VK.transform_feedback.simple.depth_clip_control_tese with lvp
Fixes:
dacf8f5f5c82 ("draw: hook up final bits of tessellation")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15128>
Alyssa Rosenzweig [Wed, 23 Feb 2022 14:29:28 +0000 (09:29 -0500)]
pan/mdg: Fix overflow in intra-bundle interference
There are up to 4 instructions in the latter stage (if a branch is included),
not 3. Bump the limit to fix memory corruption.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15147>
Jordan Justen [Tue, 15 Feb 2022 18:45:37 +0000 (10:45 -0800)]
anv: Align state pools to 2MiB on XeHP
Suggested-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Fixes:
c17e2216dd5 ("anv: Align buffer VMA to 2MiB for XeHP")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15054>
Jordan Justen [Tue, 15 Feb 2022 18:43:23 +0000 (10:43 -0800)]
anv: Align GENERAL_STATE_POOL_MIN_ADDRESS to 2MiB
Fixes:
c17e2216dd5 ("anv: Align buffer VMA to 2MiB for XeHP")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15054>
Alyssa Rosenzweig [Tue, 22 Feb 2022 14:49:32 +0000 (09:49 -0500)]
iris,crocus,i915g: Don't stub flush_frontbuffer
This callback is only intended for software rasterizers, layered drivers, and
other special drivers that go through the software winsys path. Remove the
unimplemented stubs from the Intel drivers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Dave Airlie <airlied@redhat.com> [crocus]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15118>
Alyssa Rosenzweig [Tue, 22 Feb 2022 16:30:05 +0000 (11:30 -0500)]
panfrost: Simplify panfrost_resource_get_handle
Unify the exit paths to clean up the logic. There are logically three modes we
support (KMS without renderonly, KMS with renderonly, and FD); these each
correspond to a leg of a small if statement. Outside of the small if's,
everything else should be identical.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: James Jones <jajones@nvidia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15120>
Alyssa Rosenzweig [Tue, 22 Feb 2022 16:24:58 +0000 (11:24 -0500)]
panfrost: Fix FD resource_get_handle
When handle->type is WINSYS_HANDLE_TYPE_FD, the caller wants a file descriptor
for the BO backing the resource. We previously had two paths for this:
1. If rsrc->scanout is available, we prime the GEM handle from the KMS device
(rsrc->scanout->handle) to a file descriptor via the KMS device.
2. If rsrc->scanout is not available, we prime the GEM handle from the GPU
(bo->gem_handle) to a file descriptor via the GPU device.
In both cases, the caller passes in a resource (with BO) and expects out a file
descriptor. There are no direct GEM handles in the function signature; the
caller doesn't care which GEM handle we prime to get the file descriptor. In
principle, both paths produce the same file descriptor for the same BO, since
both GEM handles represent the same underlying resource (viewed from different
devices).
On grounds of redundancy alone, it makes sense to remove the rsrc->scanout path.
Why have a path that only works sometimes, when we have another path that works
always?
In fact, the issues with the rsrc->scanout path are deeper. rsrc->scanout is
populated by renderonly_create_gpu_import_for_resource, which does the
following:
1. Get a file descriptor for the resource by resource_get_handle with
WINSYS_HANDLE_TYPE_FD
2. Prime the file descriptor to a GEM handle via the KMS device.
Here comes strike number 2: in order to get a file descriptor via the KMS
device, we had to /already/ get a file descriptor via the GPU device. If we go
down the KMS device path, we effectively round trip:
GPU handle -> fd -> KMS handle -> fd
There is no good reason to do this; if everything works, the fd is the same in
each case. If everything works. If.
The lifetimes of the GPU handle and the KMS handle are not necessarily bound. In
principle, a resource can be created with scanout (constructing a KMS handle).
Then the KMS view can be destroyed (invalidating the GEM handle for the KMS
device), even though the underlying resource is still valid. Notice the GPU
handle is still valid; its lifetime is tied to the resource itself. Then a
caller can ask for the FD for the resource; as the resource is still valid, this
is sensible. Under the scanout path, we try to get the FD by priming the GEM
handle on the KMS device... but that GEM handle is no longer valid, causing the
PRIME ioctl to fail with ENOENT. On the other hand, if we primed the GPU GEM
handle, everything works as expected.
These edge cases are not theoretical; recent versions of Xwayland trigger this
ENOENT, causing issue #5758 on all Panfrost devices. As far as I can tell, no
other kmsro driver has this 'special' kmsro path; the only part of
resource_get_handle that needs special handling for kmsro is getting a KMS
handle.
Let's remove the broken, useless path, fix Xwayland, bring us in line with other
drivers, and delete some code.
Thank you for coming to my ted talk.
Closes: #5758
Fixes:
7da251fc721 ("panfrost: Check in sources for command stream")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-and-tested-by: Jan Palus <jpalus@fastmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: James Jones <jajones@nvidia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Tested-by: Dan Johansen <strit@manjaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15120>
Dmitry Baryshkov [Wed, 16 Feb 2022 22:18:43 +0000 (01:18 +0300)]
freedreno/registers: add new register for 7nm DSI PHY v4.3 (sm8450)
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15052>
Alyssa Rosenzweig [Wed, 23 Feb 2022 15:04:44 +0000 (10:04 -0500)]
ci: Disable windows-vs2019
Currently down.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15148>
Rhys Perry [Fri, 18 Feb 2022 15:49:57 +0000 (17:49 +0200)]
anv: Enable nir_opt_access
This commit will enable pass for searching readonly / writeonly
access when it's missing.
We don't support shaderStorageImageReadWithoutFormat
and the optimization pass causes those shaders to
take the write-only path which does support formatless.
Following games are affected with positive result:
- Wolfenstein: Youngblood
- Wolfenstein II: The New Colossus https://gitlab.freedesktop.org/mesa/mesa/-/issues/3138
- Rage 2 https://gitlab.freedesktop.org/mesa/mesa/-/issues/5791
- The Surge 2 https://gitlab.freedesktop.org/mesa/mesa/-/issues/5805
- Metro Exodus https://gitlab.freedesktop.org/mesa/mesa/-/issues/4703
- DOOM Eternal https://gitlab.freedesktop.org/mesa/mesa/-/issues/4273
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3138,https://gitlab.freedesktop.org/mesa/mesa/-/issues/5791,https://gitlab.freedesktop.org/mesa/mesa/-/issues/4273
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15082>
Alyssa Rosenzweig [Sat, 12 Feb 2022 15:33:54 +0000 (10:33 -0500)]
panfrost: Inline pan_emit_sfbd_tiler
Easier to read, the common code was already common.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 15:31:40 +0000 (10:31 -0500)]
panfrost: Remove pan_emit_fbd thunking
Use a common interface.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 15:26:14 +0000 (10:26 -0500)]
panfrost: Remove unrelated comment
Not sure what this was supposed to describe, but it's not the code here.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 19:15:17 +0000 (14:15 -0500)]
panfrost: Use txl instead of tex in the blitter
We always blit from a particular level, so it's a waste to compute the LOD.
This corresponds to a simple texture instruction with implement 0 LOD, which is
the optimal texturing path on Bifrost -- it maps to TEXS_2D but does not require
helper invocations.
Functional change on Bifrost: Blit shaders no longer set .computed_lod or
shader_contains_barrier.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 14:59:28 +0000 (09:59 -0500)]
panfrost: Inline pan_blit_emit_dcd
Easier to follow the logic without having a million arguments passed around.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 14:57:45 +0000 (09:57 -0500)]
panfrost: Decouple tiler job and DCD emit
We can share the "emit quad" logic, even though the DCDs differ.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Tue, 8 Feb 2022 19:31:07 +0000 (14:31 -0500)]
panfrost: Annotate slow clears as such
We should realistically be using the clear shaders from PanVK once they're moved
to common.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Tue, 8 Feb 2022 18:49:40 +0000 (13:49 -0500)]
panfrost: Set defaults for deprecated DCD fields
There are always set to true. Don't pollute the driver code with them, make
their existence a local detail to pre-Valhall XML and that's it.
Functional change: "four components per vertex" is now set on vertex job DCDs.
This should be a no-op.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Tue, 8 Feb 2022 18:44:38 +0000 (13:44 -0500)]
panfrost: Use pan_shader_prepare_rsd in blitter
This reduces code duplication and will ease Valhall porting. Functional changes
on v7:
* Shader contains barrier is now set (perf loss, fixed later in series)
* Shader register allocation is now set (perf win)
* Point sprite inverted, no-op for blit shaders
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Alyssa Rosenzweig [Sat, 12 Feb 2022 21:43:36 +0000 (16:43 -0500)]
pan/mdg: Fix partial execution mode names
cont -> skip, last -> kill, and fix the special case handling. It's just an
enum. Makes the disassembly easier to read and closer to Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15123>
Danylo Piliaiev [Thu, 17 Feb 2022 15:02:06 +0000 (17:02 +0200)]
turnip: Always use GMEM for feedback loops in autotuner
For ordinary feedback loops GMEM is a lot faster than sysmem since
we don't set SINGLE_PRIM mode.
For feedback loops with ordered rasterization GMEM should also be
faster.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Danylo Piliaiev [Fri, 18 Feb 2022 17:15:03 +0000 (19:15 +0200)]
turnip: Implement VK_ARM_rasterization_order_attachment_access
Trivially implemented by using A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE.
This extension is useful for emulators e.g. AetherSX2 PS2 emulator and
could drastically improve performance when blending is emulated.
Relevant tests:
dEQP-VK.rasterization.rasterization_order_attachment_access.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Danylo Piliaiev [Tue, 22 Feb 2022 17:35:18 +0000 (19:35 +0200)]
turnip: Merge LRZ and DEPTH_PLANE draw states
They were emitted at the same time. Frees 1 draw state for us to use.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Danylo Piliaiev [Wed, 23 Feb 2022 09:44:23 +0000 (11:44 +0200)]
turnip: Use LATE_Z when there might be depth/stencil feedback loop
Otherwise a shader invocation would read the value which should have
been set AFTER this shader invocation.
Fixes tests:
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers
Fixes:
71595a189a0c372efd520ad51866ca57aa83298c
("tu: Fix feedback loops in sysmem mode")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15106>
Paulo Zanoni [Thu, 17 Feb 2022 01:15:01 +0000 (17:15 -0800)]
iris: fix register spilling on compute shaders on XeHP
XeHP scratch space is handled differently. Commit
ae18e1e707c4
implemented support for it, but handled it differently between render
and compute shaders: it calculates scratch_addr differently and
doesn't pin the buffer on compute. Make it work on compute shaders by
calling pin_scratch_space() from iris_compute_walker(), which fixes
both the address and the pinning.
This commit can be verified by the two-year-old-but-still-unreviewed
Piglit MR 234. You can also verify this by running a very simple
compute shader with INTEL_DEBUG=spill_fs.
References: https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/234
Fixes:
ae18e1e707c4 ("iris: Add support for scratch on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15070>
Kenneth Graunke [Thu, 10 Feb 2022 23:45:23 +0000 (15:45 -0800)]
anv: Raise vertex input bindings and attributes limits slightly
This raises our vertex input bindings limit from 28 to 31, and our
vertex input attribute limit from 28 to 29. We could theoretically
go higher, but it will take additional work.
The 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS limits are 33
vertex buffers, and 34 vertex elements. But we need up to two vertex
elements for system values (FirstVertex, BaseVertex, BaseInstance,
DrawID), and we currently use two vertex bindings for those.
There is another hidden limit: our compiler backend only supports the
push model for VS inputs currently. 3DSTATE_VS only allows URB Read
Lengths between [0, 15], which is measured in pairs of inputs, which
means we can theoretically push no more than 32 vertex elements. This
is no artifical limit either, as a vec4 element takes up 4 registers
in the payload, and 32 * 4 = 128, the entire size of our register file.
Plus, the VS Thread payload needs at least g0 and g1 for other things,
so we can really only push 31.
We can theoretically support one additional binding, by combining our
two SGV bindings into a single upload. In order to support additional
vertex elements, we would need to add support to the backend compiler
for the pull model for VS inputs.
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5917
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14991>
Mike Blumenkrantz [Tue, 22 Feb 2022 01:53:21 +0000 (20:53 -0500)]
zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15067>
Mike Blumenkrantz [Mon, 31 Jan 2022 17:26:52 +0000 (12:26 -0500)]
zink: remove zink_descriptor_util_init_null_set()
no longer used
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15067>
Mike Blumenkrantz [Mon, 31 Jan 2022 17:23:22 +0000 (12:23 -0500)]
zink: allow null descriptor set layouts
I got confused while writing this somehow because of the null descriptor
feature, which enables drivers to consume a null descriptor, which has no
relation to a descriptor layout containing no descriptors
failing to accurately use zero descriptors can put layouts over the maximum
per-stage limits, which causes tests to crash
fixes (lavapipe):
KHR-GL46.shading_language_420pack.binding_uniform_block_array
KHR-GL46.multi_bind.dispatch_bind_buffers_base
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15067>
Timur Kristóf [Thu, 17 Feb 2022 09:57:47 +0000 (10:57 +0100)]
ac/nir/ngg: Fix mixed up primitive ID after culling.
When NGG culling is enabled, make sure that the correct
primitive ID is exported by each lane.
Fixes:
e97f0463a8f55d5d407178f74b0cdb916a42aef8 "ac/nir: Implement NGG deferred attribute culling in NIR."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6050
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15055>
Mike Blumenkrantz [Tue, 15 Feb 2022 03:50:14 +0000 (22:50 -0500)]
zink: prune ci lists
I don't know why I thought running GL3.2 and GL4.6 was a good idea,
but it wasn't
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15065>
Emma Anholt [Tue, 1 Feb 2022 06:13:29 +0000 (22:13 -0800)]
turnip: Request no implicit sync when we have no implicit-sync WSI BOs.
I chose to implement this as a global flag in the device, because
otherwise we would end up with extra draw overhead trying to avoid it in
the implicit-sync WSI case, and you're probably going to end up needing
implicit sync anyway because you used one of the BOs in any of the
submitted cmdbufs. To do better than this, we would probably want a
skip-implicit-sync flag on the BOs in the BO list, rather than global on
the submit.
Reports about venus on turnip say that this flag reduces worst-case
QueueSubmit time in a game workload from ~10ms to ~4ms.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14838>
Samuel Pitoiset [Mon, 21 Feb 2022 11:54:48 +0000 (12:54 +0100)]
radv: fix build on BSD
Just disable inotify for BDS systems.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6060
Fixes:
c50557d9612 ("radv: allow applications to dynamically change RADV_FORCE_VRS")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15105>
Alyssa Rosenzweig [Fri, 18 Feb 2022 21:41:24 +0000 (16:41 -0500)]
pan/bi: Add BIFROST_MESA_DEBUG=nosb option
To disable the new scoreboarding optimizations when debugging.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:09:42 +0000 (11:09 -0500)]
pan/bi: Implement basic scoreboarding pass
Extend our existing bi_scoreboard infrastructure with a simple data flow
analysis pass that calculates which dependency slots need waiting. We
still lack a heuristic for selecting dependency slots.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:09:15 +0000 (11:09 -0500)]
pan/bi: Print scoreboarding state
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Fri, 18 Feb 2022 20:28:38 +0000 (15:28 -0500)]
pan/bi: Add scoreboard state to IR
To a limited degree, scoreboarding must be global, so add the data
structures for tracking this to the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:08:03 +0000 (11:08 -0500)]
pan/bi: Clean up nits in liveness analysis
Fix minor silly things.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:07:35 +0000 (11:07 -0500)]
pan/bi: Use bi_exit_block
The "generic" one is a vestige of Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 16:06:59 +0000 (11:06 -0500)]
pan/bi: Add bi_{start, exit}_block helpers
Useful for data flow analysis.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 17:14:41 +0000 (12:14 -0500)]
pan/bi: Do not cull post-RA staging writes
Bifrost post-RA dead code elimination can cull the destinations of
regular ALU instructions, by weakening from a register write to a
temporary write. However, there is no way to suppress staging writes, so
culling the destinations will result in invalid code generation.
Fixes a regression in
dEQP-GLES3.functional.shaders.switch.switch_in_for_loop_static_vertex
with scoreboarding. The root cause there is the backend dead code
elimination not being sufficiently aggressive in the presence of control
flow. Usually this does not matter, since the backend optimizations are
intended to be local with global optimizations happening in NIR.
Unfortunately, our implementation of IDVS hits this hard. That will need
to be optimized (probably by specializing IDVS shaders in NIR instead of
the backend). In the mean time, let's fix the actual bug affecting
scoreboarding.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Thu, 23 Dec 2021 18:12:19 +0000 (13:12 -0500)]
pan/bi: Cull DTSEL_IMM dests in post-RA DCE
They are useless (given the semantics of DTSEL_IMM) and complicate
scoreboarding. Just remove them in the pass that removes all the other silly
register destinations.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Alyssa Rosenzweig [Tue, 22 Feb 2022 16:45:54 +0000 (11:45 -0500)]
pan/bi: Clarify requirement for barriers
Barriers need to wait on all outstanding messages. This is more of an API
requirement than a hardware requirement, but it's still an invariant the
scoreboarding pass must respect.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14298>
Erik Faye-Lund [Thu, 27 Jan 2022 08:52:56 +0000 (09:52 +0100)]
docs: add license to the redirects script
I always intended this to be covered by the MIT license like with the
rest of my contributions, but somehow forgot to add it.
Let's add that license to make things clear.
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14751>
Adam Jackson [Thu, 10 Feb 2022 16:11:38 +0000 (11:11 -0500)]
mesa: Enable GL_NV_pack_subimage
This just legalizes a few of the pixelstore pack parameters in GLES2
that are already legal in desktop and GLES3. glamor takes advantage of
this in the GetImage and software-fallback paths.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14977>
Alyssa Rosenzweig [Fri, 18 Feb 2022 14:47:30 +0000 (09:47 -0500)]
pan/bi: Enable nir_opt_shrink_vectors
total instructions in shared programs: 1939513 -> 1935815 (-0.19%)
instructions in affected programs: 809066 -> 805368 (-0.46%)
helped: 3195
HURT: 865
helped stats (abs) min: 1.0 max: 15.0 x̄: 1.99 x̃: 1
helped stats (rel) min: 0.10% max: 25.00% x̄: 2.26% x̃: 1.28%
HURT stats (abs) min: 1.0 max: 22.0 x̄: 3.09 x̃: 2
HURT stats (rel) min: 0.10% max: 83.33% x̄: 2.67% x̃: 1.39%
95% mean confidence interval for instructions value: -1.00 -0.82
95% mean confidence interval for instructions %-change: -1.34% -1.08%
Instructions are helped.
total tuples in shared programs: 1523194 -> 1521789 (-0.09%)
tuples in affected programs: 745526 -> 744121 (-0.19%)
helped: 2947
HURT: 1844
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.06 x̃: 1
helped stats (rel) min: 0.15% max: 25.00% x̄: 2.65% x̃: 1.59%
HURT stats (abs) min: 1.0 max: 29.0 x̄: 2.54 x̃: 1
HURT stats (rel) min: 0.09% max: 40.00% x̄: 2.32% x̃: 1.52%
95% mean confidence interval for tuples value: -0.39 -0.20
95% mean confidence interval for tuples %-change: -0.85% -0.62%
Tuples are helped.
total clauses in shared programs: 329158 -> 325350 (-1.16%)
clauses in affected programs: 111654 -> 107846 (-3.41%)
helped: 2787
HURT: 498
helped stats (abs) min: 1.0 max: 17.0 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.76% max: 40.00% x̄: 6.92% x̃: 5.26%
HURT stats (abs) min: 1.0 max: 3.0 x̄: 1.14 x̃: 1
HURT stats (rel) min: 0.87% max: 50.00% x̄: 4.73% x̃: 3.77%
95% mean confidence interval for clauses value: -1.21 -1.10
95% mean confidence interval for clauses %-change: -5.39% -4.93%
Clauses are helped.
total cycles in shared programs: 172084.50 -> 166827.62 (-3.05%)
cycles in affected programs: 74698.83 -> 69441.96 (-7.04%)
helped: 3706
HURT: 568
helped stats (abs) min: 0.
041665999999999315 max: 19.0 x̄: 1.44 x̃: 1
helped stats (rel) min: 0.24% max: 75.00% x̄: 9.48% x̃: 6.90%
HURT stats (abs) min: 0.
041665999999999315 max: 1.0 x̄: 0.15 x̃: 0
HURT stats (rel) min: 0.25% max: 50.00% x̄: 2.21% x̃: 1.42%
95% mean confidence interval for cycles value: -1.28 -1.18
95% mean confidence interval for cycles %-change: -8.18% -7.67%
Cycles are helped.
total arith in shared programs: 57145.04 -> 57211.37 (0.12%)
arith in affected programs: 27595.12 -> 27661.46 (0.24%)
helped: 1933
HURT: 2259
helped stats (abs) min: 0.
041665999999999315 max: 0.75 x̄: 0.09 x̃: 0
helped stats (rel) min: 0.16% max: 33.33% x̄: 2.74% x̃: 1.52%
HURT stats (abs) min: 0.
04166399999999726 max: 1.
3333329999999997 x̄: 0.11 x̃: 0
HURT stats (rel) min: 0.10% max: 100.00% x̄: 2.79% x̃: 1.62%
95% mean confidence interval for arith value: 0.01 0.02
95% mean confidence interval for arith %-change: 0.07% 0.40%
Arith are HURT.
total texture in shared programs: 12857 -> 12857 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0
total vary in shared programs: 11157.75 -> 10222 (-8.39%)
vary in affected programs: 5643 -> 4707.25 (-16.58%)
helped: 3196
HURT: 0
helped stats (abs) min: 0.125 max: 1.875 x̄: 0.29 x̃: 0
helped stats (rel) min: 2.78% max: 75.00% x̄: 18.49% x̃: 15.00%
95% mean confidence interval for vary value: -0.30 -0.29
95% mean confidence interval for vary %-change: -18.88% -18.11%
Vary are helped.
total ldst in shared programs: 146420 -> 140270 (-4.20%)
ldst in affected programs: 66027 -> 59877 (-9.31%)
helped: 2942
HURT: 10
helped stats (abs) min: 1.0 max: 19.0 x̄: 2.09 x̃: 2
helped stats (rel) min: 0.90% max: 100.00% x̄: 16.81% x̃: 8.33%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 2.22% max: 50.00% x̄: 13.03% x̃: 3.33%
95% mean confidence interval for ldst value: -2.15 -2.02
95% mean confidence interval for ldst %-change: -17.53% -15.89%
Ldst are helped.
total quadwords in shared programs: 1398329 -> 1392117 (-0.44%)
quadwords in affected programs: 704641 -> 698429 (-0.88%)
helped: 3677
HURT: 1299
helped stats (abs) min: 1.0 max: 26.0 x̄: 2.51 x̃: 1
helped stats (rel) min: 0.10% max: 26.92% x̄: 2.64% x̃: 1.89%
HURT stats (abs) min: 1.0 max: 20.0 x̄: 2.31 x̃: 1
HURT stats (rel) min: 0.11% max: 44.44% x̄: 2.34% x̃: 1.55%
95% mean confidence interval for quadwords value: -1.34 -1.16
95% mean confidence interval for quadwords %-change: -1.44% -1.25%
Quadwords are helped.
total threads in shared programs: 35234 -> 35311 (0.22%)
threads in affected programs: 119 -> 196 (64.71%)
helped: 91
HURT: 14
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.60 0.87
95% mean confidence interval for threads %-change: 70.08% 89.92%
Threads are helped.
total loops in shared programs: 125 -> 125 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 149 -> 144 (-3.36%)
spills in affected programs: 22 -> 17 (-22.73%)
helped: 1
HURT: 0
total fills in shared programs: 966 -> 956 (-1.04%)
fills in affected programs: 44 -> 34 (-22.73%)
helped: 1
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
Alyssa Rosenzweig [Sat, 19 Feb 2022 00:20:27 +0000 (19:20 -0500)]
pan/bi: Specialize IDVS in NIR
It's a bit more code, but it's needed to chew through control flow since we
don't have a backend version of dead_cf. Results are really good, meaning I
really screwed this up the first time around (hence the cc mesa-stable).
total instructions in shared programs: 1963576 -> 1939513 (-1.23%)
instructions in affected programs: 671053 -> 646990 (-3.59%)
helped: 4436
HURT: 729
helped stats (abs) min: 1.0 max: 43.0 x̄: 5.75 x̃: 6
helped stats (rel) min: 0.21% max: 100.00% x̄: 6.47% x̃: 5.17%
HURT stats (abs) min: 1.0 max: 22.0 x̄: 2.01 x̃: 1
HURT stats (rel) min: 0.50% max: 50.00% x̄: 10.45% x̃: 9.09%
95% mean confidence interval for instructions value: -4.77 -4.55
95% mean confidence interval for instructions %-change: -4.36% -3.80%
Instructions are helped.
total tuples in shared programs: 1533335 -> 1523194 (-0.66%)
tuples in affected programs: 483167 -> 473026 (-2.10%)
helped: 3414
HURT: 1288
helped stats (abs) min: 1.0 max: 20.0 x̄: 3.73 x̃: 2
helped stats (rel) min: 0.27% max: 100.00% x̄: 4.87% x̃: 3.03%
HURT stats (abs) min: 1.0 max: 19.0 x̄: 2.02 x̃: 1
HURT stats (rel) min: 0.24% max: 38.10% x̄: 8.10% x̃: 5.88%
95% mean confidence interval for tuples value: -2.28 -2.03
95% mean confidence interval for tuples %-change: -1.62% -1.02%
Tuples are helped.
total clauses in shared programs: 351432 -> 329158 (-6.34%)
clauses in affected programs: 142237 -> 119963 (-15.66%)
helped: 5328
HURT: 3
helped stats (abs) min: 1.0 max: 43.0 x̄: 4.18 x̃: 4
helped stats (rel) min: 0.74% max: 100.00% x̄: 19.44% x̃: 17.24%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 9.09% max: 12.50% x̄: 10.90% x̃: 11.11%
95% mean confidence interval for clauses value: -4.25 -4.11
95% mean confidence interval for clauses %-change: -19.72% -19.12%
Clauses are helped.
total cycles in shared programs: 202830.92 -> 172084.50 (-15.16%)
cycles in affected programs: 117078.42 -> 86332 (-26.26%)
helped: 5450
HURT: 1
helped stats (abs) min: 0.083333 max: 49.0 x̄: 5.64 x̃: 5
helped stats (rel) min: 1.42% max: 100.00% x̄: 27.94% x̃: 25.64%
HURT stats (abs) min: 0.25 max: 0.25 x̄: 0.25 x̃: 0
HURT stats (rel) min: 2.46% max: 2.46% x̄: 2.46% x̃: 2.46%
95% mean confidence interval for cycles value: -5.74 -5.54
95% mean confidence interval for cycles %-change: -28.30% -27.58%
Cycles are helped.
total arith in shared programs: 57274.29 -> 57145.04 (-0.23%)
arith in affected programs: 16418.33 -> 16289.08 (-0.79%)
helped: 2442
HURT: 1784
helped stats (abs) min: 0.
041665999999999315 max: 0.75 x̄: 0.14 x̃: 0
helped stats (rel) min: 0.23% max: 100.00% x̄: 5.51% x̃: 2.87%
HURT stats (abs) min: 0.
041665999999999315 max: 0.
9166670000000003 x̄: 0.12 x̃: 0
HURT stats (rel) min: 0.00% max: 100.00% x̄: 25.13% x̃: 9.09%
95% mean confidence interval for arith value: -0.04 -0.03
95% mean confidence interval for arith %-change: 6.61% 8.24%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total texture in shared programs: 12857 -> 12857 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0
total vary in shared programs: 11157.75 -> 11157.75 (0.00%)
vary in affected programs: 0 -> 0
helped: 0
HURT: 0
total ldst in shared programs: 177208 -> 146420 (-17.37%)
ldst in affected programs: 117098 -> 86310 (-26.29%)
helped: 5447
HURT: 0
helped stats (abs) min: 1.0 max: 49.0 x̄: 5.65 x̃: 5
helped stats (rel) min: 1.92% max: 100.00% x̄: 27.91% x̃: 25.64%
95% mean confidence interval for ldst value: -5.75 -5.55
95% mean confidence interval for ldst %-change: -28.27% -27.56%
Ldst are helped.
total quadwords in shared programs: 1436507 -> 1398329 (-2.66%)
quadwords in affected programs: 515101 -> 476923 (-7.41%)
helped: 5150
HURT: 111
helped stats (abs) min: 1.0 max: 39.0 x̄: 7.46 x̃: 6
helped stats (rel) min: 0.17% max: 100.00% x̄: 10.02% x̃: 8.24%
HURT stats (abs) min: 1.0 max: 9.0 x̄: 2.01 x̃: 1
HURT stats (rel) min: 0.43% max: 21.62% x̄: 3.57% x̃: 1.94%
95% mean confidence interval for quadwords value: -7.41 -7.11
95% mean confidence interval for quadwords %-change: -9.98% -9.49%
Quadwords are helped.
total threads in shared programs: 35025 -> 35228 (0.58%)
threads in affected programs: 218 -> 421 (93.12%)
helped: 208
HURT: 5
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.91 0.99
95% mean confidence interval for threads %-change: 93.40% 99.55%
Threads are helped.
total loops in shared programs: 128 -> 125 (-2.34%)
loops in affected programs: 3 -> 0
helped: 3
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
total spills in shared programs: 158 -> 149 (-5.70%)
spills in affected programs: 15 -> 6 (-60.00%)
helped: 9
HURT: 0
total fills in shared programs: 1133 -> 966 (-14.74%)
fills in affected programs: 197 -> 30 (-84.77%)
helped: 9
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
Alyssa Rosenzweig [Mon, 21 Feb 2022 02:29:50 +0000 (21:29 -0500)]
panvk: Use more reliable assert for UBO pushing
The important thing isn't the number of words pushed, it's that there are no
UBOs required for us to upload. Check that instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
Georg Lehmann [Tue, 15 Feb 2022 12:22:40 +0000 (13:22 +0100)]
radv, aco: Add u_foreach_bit to .clang-format.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15083>
Xaver Hugl [Thu, 20 May 2021 16:49:07 +0000 (18:49 +0200)]
gbm: improve documentation about the lifetime of resources
Signed-off-by: Xaver Hugl <xaver.hugl@gmail.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10906>
Marek Olšák [Sat, 22 Jan 2022 15:03:16 +0000 (10:03 -0500)]
ac: update shadowed registers
based on PAL
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 21 Jan 2022 09:04:22 +0000 (04:04 -0500)]
radeonsi: move Arcturus code outside the gfx9 branch
preparation for a future commit
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 18 Feb 2022 02:25:21 +0000 (21:25 -0500)]
ac/llvm: replace structured by vindex != NULL in ac_build_buffer_store_common
"raw" (IDXEN=0) and "structured" (IDXEN=1) do bounds checking differently.
From `si_make_buffer_descriptor`:
* - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
* - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
so there is a difference between setting vindex = i32_0 and vindex = NULL.
Instead of having the `structured` flag, we can just check if vindex is NULL.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Fri, 18 Feb 2022 02:25:21 +0000 (21:25 -0500)]
ac/llvm: replace structured by vindex != NULL in ac_build_tbuffer_store
"raw" (IDXEN=0) and "structured" (IDXEN=1) do bounds checking differently.
From `si_make_buffer_descriptor`:
* - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
* - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
so there is a difference between setting vindex = i32_0 and vindex = NULL.
Instead of having the `structured` flag, we can just check if vindex is NULL.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Tue, 22 Feb 2022 08:05:35 +0000 (03:05 -0500)]
radeonsi: use SET_SH_REG_INDEX with index=3 for registers containing CU_EN
This matches PAL and RADV behavior. It's for preemption.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
Marek Olšák [Tue, 22 Feb 2022 04:25:06 +0000 (23:25 -0500)]
ac/surface: add more elements to meta equations because HTILE can use them
according to gfx10SwizzlePattern.h
Fixes:
9fabbf2150253d06d - ac/surface: copy the HTILE equations to the surface
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>