Marek Olšák [Sat, 23 Oct 2021 04:54:09 +0000 (00:54 -0400)]
vbo: return a GL error earlier in vbo_save_playback_vertex_list_gallium
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13506>
Marek Olšák [Sat, 23 Oct 2021 20:14:25 +0000 (16:14 -0400)]
mesa: remove PADDING_64BIT by adding the dlist header into vbo_save_vertex_list
Now we can put useful data where the padding was.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13506>
Marek Olšák [Fri, 22 Oct 2021 20:24:37 +0000 (16:24 -0400)]
mesa: remove display list OPCODE_NOP
This decreases overhead because there are fewer nodes to parse.
There are 2 changes done here:
- If the next node offset is (offset % 8) == 4, pad the last node instead
of inserting NOP. This makes sure that the node offset is aligned.
- The vertex list node will add 4 bytes to the header to make the payload
aligned, so the payload will be at &n[2].
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13506>
Marek Olšák [Fri, 22 Oct 2021 19:15:35 +0000 (15:15 -0400)]
mesa: fix locking when destroying/overwriting/adding display lists
We need to hold the lock when calling destroy_list and doing
_mesa_HashInsertLocked in EndList.
So move the locking out of destroy_list.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13506>
Marek Olšák [Fri, 22 Oct 2021 17:49:00 +0000 (13:49 -0400)]
radeonsi: don't invoke si_decompress_depth if textures are not dirty at binding
This eliminates the overhead of invoking si_decompress_depth.
The complication here is that we need to update needs_depth_decompress_mask
every time we update dirty_level_mask.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13492>
Marek Olšák [Fri, 22 Oct 2021 07:31:36 +0000 (03:31 -0400)]
winsys/amdgpu: optimize looping inefficiencies in add_bo_fence_dependencies
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 07:24:02 +0000 (03:24 -0400)]
winsys/amdgpu: move BO fence array updates to the CS thread
We always wait for num_active_ioctls == 0 before we use the fence,
so we can just add fences to BOs in the CS thread.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 07:19:50 +0000 (03:19 -0400)]
winsys/amdgpu: don't use ip_instance and ring fields of fence and IB structures
They are always 0.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 06:04:18 +0000 (02:04 -0400)]
winsys/amdgpu: increase the BO hash list size
This decreases overhead inside amdgpu_cs_add_buffer by 40%
for viewperf2020/catia.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 04:52:40 +0000 (00:52 -0400)]
winsys/amdgpu: don't clear RADEON_USAGE_SYNCHRONIZED for last_added_bo_usage
It was breaking the early return path.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 04:30:36 +0000 (00:30 -0400)]
winsys/amdgpu: remove an amdgpu_cs dereference from amdgpu_cs_add_buffer
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 04:18:48 +0000 (00:18 -0400)]
winsys/amdgpu: simplify parameter passing and derefs in cs_add_buffer
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 03:17:03 +0000 (23:17 -0400)]
gallium/radeon: merge BO read/write usage flags with priority flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 03:15:12 +0000 (23:15 -0400)]
gallium/radeon: remove unused RADEON_DEPENDENCY_START_FENCE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 03:13:20 +0000 (23:13 -0400)]
gallium/radeon: remove/merge some BO priorities and remove holes
The upper bits will be used by RADEON_USAGE_*
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Fri, 22 Oct 2021 02:57:43 +0000 (22:57 -0400)]
gallium/radeon: change the BO priority definitions to bits
This is for the next microoptimization.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
Marek Olšák [Wed, 27 Oct 2021 05:29:42 +0000 (01:29 -0400)]
radeonsi: remove unused parameters in si_emit_draw_packets
This is a leftover from GS fast launch and compute-based culling.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13539>
Marek Olšák [Wed, 27 Oct 2021 05:25:49 +0000 (01:25 -0400)]
radeonsi: enable shader culling for indirect draws
It was mistakenly disabled, decreasing performance a lot.
Only valid for Mesa 21.3.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 21.3 <mesa-stable@lists.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13539>
Greg V [Wed, 8 Apr 2020 22:41:00 +0000 (01:41 +0300)]
util: make util_get_process_exec_path work on FreeBSD w/o procfs
sysctl is the correct way of getting the current executable's path.
procfs is not mounted by default.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1598>
Greg V [Wed, 8 Apr 2020 22:43:10 +0000 (01:43 +0300)]
util: __getProgramName: remove check for ancient FreeBSD versions, simplify ifdefs
FreeBSD 5.0 was released in 2003.
We really do not need to check that we're on >= 4.4.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1598>
Boyuan Zhang [Sun, 24 Oct 2021 22:54:31 +0000 (18:54 -0400)]
radeon/vcn: combine session init func
Combine the session init function for h.264 and hevc to reduce redundancy.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
Boyuan Zhang [Sun, 24 Oct 2021 22:53:56 +0000 (18:53 -0400)]
radeon/vcn: combine encode params func
Combine the encode params function for h.264 and hevc to reduce redundancy.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
Boyuan Zhang [Sun, 24 Oct 2021 22:09:45 +0000 (18:09 -0400)]
radeon/vcn: remove redundancy for vcn2 enc
Remove redundancy functions for vcn2 encode. Re-using the vcn1 quality params
function as a result.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
Boyuan Zhang [Sun, 24 Oct 2021 22:01:42 +0000 (18:01 -0400)]
radeon/vcn: update vcn2 enc interface
Add missing parameters according to vcn 2 encode interface.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
Boyuan Zhang [Sun, 24 Oct 2021 21:57:51 +0000 (17:57 -0400)]
radeon/vcn: update vcn1 enc interface
Update vcn 1 encode interface, upgrade interface minor version from 2 to 9,
and add necessary parameters accordingly.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13511>
Emma Anholt [Fri, 8 Oct 2021 20:17:27 +0000 (13:17 -0700)]
ci: Enable testing radeonsi's libva using libva-util unit tests.
We've noticed issues with these tests when uprevving Mesa in Chrome OS.
This CI catches some existing failures, and some debug-build assertion
failures as well.
To do this, uprev deqp-runner for its new gtest-runner command. This
runner is not as efficient as I would hope, due to some expensive code in
gtest. I've reported the issue to gtest and it should be easily fixable,
but for now it at least means we get to use the same baseline/skip/flake
handling we have from deqp and piglit runners.
I also fixed build-libdrm for our rootfses to not throw away libdrm's
share directory, which was causing a bunch of test-time spam from radeon's
libdrm when trying to look up its marketing name tables (not that big of a
deal for deqp-runner, but really noisy for piglit and libva-utils which
make gallium screens approximatly per-test).
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13419>
Connor Abbott [Thu, 28 Oct 2021 16:59:33 +0000 (18:59 +0200)]
freedreno/a6xx: Emit GRAS_LRZ_MRT_BUF_INFO_0
Analogous to the previous commit, this fixes the case where turnip sets
this reg to a media (yuv) format and then a gallium job is run next.
Fixes:
9c895e13 ("tu: Emit GRAS_LRZ_MRT_BUF_INFO_0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13578>
Connor Abbott [Thu, 28 Oct 2021 16:50:33 +0000 (18:50 +0200)]
tu: Always write GRAS_LRZ_MRT_BUF_INFO_0
This fixes flakes in dEQP-VK.pipeline.stencil.nocolor.format.* when run
after ycbcr tests. Apparently LRZ needs to know if there's a media
format enabled even if there are no color attachments, so we need to
write something here. Presumably any "normal" format would work but 0
seems like a good neutral choice.
Fixes:
9c895e13 ("tu: Emit GRAS_LRZ_MRT_BUF_INFO_0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13578>
Kenneth Graunke [Fri, 28 Aug 2020 23:12:17 +0000 (16:12 -0700)]
intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.
This is a new blitter command introduced on Tigerlake and expanded
substantially on XeHP. XY_BLOCK_COPY_BLT is actually fast, unlike
the legacy blitter commands. iris will use this in the future, and
anv hopefully could use it for a transfer queue someday as well.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
Kenneth Graunke [Fri, 4 Sep 2020 09:38:35 +0000 (02:38 -0700)]
intel/genxml: Allow MI_FLUSH_DW on the blitter
Pretty sure this is how you flush the blitter.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
Kenneth Graunke [Sat, 29 Aug 2020 00:38:45 +0000 (17:38 -0700)]
intel/genxml: Include blitter commands in gen*_pack.h
We're going to want to use the blitter again on newer hardware,
which means we need to be able to use genxml to emit those commands.
Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
Kenneth Graunke [Tue, 19 Oct 2021 05:48:14 +0000 (22:48 -0700)]
intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+
Let's try and catch performance problems before we have to do large
painful amounts of analysis to detect a missed field.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 05:35:33 +0000 (22:35 -0700)]
intel/genxml: Add an field option for nonzero="true"
This asserts that the value supplied is non-zero. Useful for things
like MOCS fields on modern platforms where we really want to avoid
setting it to 0 (uncached).
mbz types cannot be flagged as nonzero.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 27 Oct 2021 19:56:01 +0000 (12:56 -0700)]
i965: Set MOCS for Bindless Surface/Sampler State base addresses
We don't use bindless surface or sampler states today, and are unlikely
to ever implement that in i965, but we can set a MOCS value regardless
to avoid asserts in upcoming patches that assert MOCS isn't zero.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 22:59:40 +0000 (15:59 -0700)]
i965: Port STATE_BASE_ADDRESS to genxml and fix bugs
This largely copies crocus's code for this (but with Gfx9+ handling).
This version also fixes missing MOCS settings on several platforms,
which we hadn't noticed were missing.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 08:08:07 +0000 (01:08 -0700)]
i965: Fix MOCS for BLORP buffer copies
We were passing a MOCS of 0, which is uncached. Yikes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 07:25:47 +0000 (00:25 -0700)]
i965: Set MOCS for 3DSTATE_INDEX_BUFFER on Gfx6/7 as well.
For some reason we were only setting this on Gfx8+.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 07:13:29 +0000 (00:13 -0700)]
i965: Set MOCS for 3DSTATE_SO_BUFFERS on Gfx7.x too
For some reason we were only setting this on Gfx8+.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 22:24:51 +0000 (15:24 -0700)]
i965: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is disabled stream output targets, MOCS shouldn't matter, as
there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 22:18:09 +0000 (15:18 -0700)]
i965: Set MOCS for push constant buffers on Haswell and Gfx9+
We set MOCS on Ivybridge/Baytrail, but not Haswell, and not Skylake
and later. We shoud set it everywhere. While we're at it, we also
set it for null constant buffers, so that we aren't programming a 0
MOCS, to allow us to add some safeguards against that.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 23:41:57 +0000 (16:41 -0700)]
i965: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero. When we have entirely NULL surfaces, we just
default to the MOCS value for an internal buffer.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 17:18:43 +0000 (10:18 -0700)]
i965: Use ISL for MOCS rather than open coding it everywhere
The ISL MOCS infrastructure didn't exist when we wrote the i965 code,
but now that it does, we ought to use it, deleting a complicated mess
that was replicated all throughout the codebase.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Thu, 21 Oct 2021 04:29:57 +0000 (21:29 -0700)]
crocus: Fix MOCS for buffer copies.
We were passing a MOCS of 0, which is uncached. Yikes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Thu, 21 Oct 2021 04:24:39 +0000 (21:24 -0700)]
crocus: Set MOCS for 3DSTATE_SO_BUFFERS on Gfx7.x too
For some reason we were only setting this on Gfx8+.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 22:42:28 +0000 (15:42 -0700)]
crocus: Set MOCS for push constant buffers where possible
We apparently were not setting MOCS for 3DSTATE_CONSTANT_XS at all.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 22:33:00 +0000 (15:33 -0700)]
crocus: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero. When we have entirely NULL surfaces, we just
default to the MOCS value for an internal buffer.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 22:30:35 +0000 (15:30 -0700)]
crocus: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is disabled stream output targets, MOCS shouldn't matter, as
there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 21:55:01 +0000 (14:55 -0700)]
crocus: Set MOCS for index buffers on Gen6+
For some reason we were only setting them on Gen8+.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Fri, 22 Oct 2021 09:31:25 +0000 (02:31 -0700)]
crocus: Tidy the ifdefs for emitting STATE_BASE_ADDRESS
This reorganizes the code so that we set fields in a tidy order:
1. Set the base addresses
2. Set either buffer sizes (Gfx8) or upper bound values (Gfx4-7)
(These are logically the same thing, but expressed differently.)
3. Set MOCS (Gfx6+)
I find this easier to follow.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 21:53:23 +0000 (14:53 -0700)]
crocus: Set MOCS for most state base addresses on pre-Gen8
We were only setting MOCS for dynamic state, surface state, instruction,
and indirect base addresses on Gen8+. We should set them on Gen6+.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 16:12:54 +0000 (09:12 -0700)]
anv: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is disabled stream output targets, MOCS shouldn't matter, as
there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 06:43:04 +0000 (23:43 -0700)]
anv: Set MOCS on NULL vertex buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is 3DSTATE_VERTEX_BUFFERS where we set NullVertexBuffer.
It shouldn't matter here, as there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for null vertex buffers.
We can assume an internal buffer and request isl's vertex buffer MOCS.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 06:39:30 +0000 (23:39 -0700)]
anv: Set MOCS in 3DSTATE_CONSTANT_XS even if there isn't a buffer.
This avoids MOCS != 0 assertions in later patches. iris also does this,
and we do it for the 3DSTATE_CONSTANT_ALL packet path as well. It's a
bit pointless, but it should hopefully be harmless also.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 20:44:10 +0000 (13:44 -0700)]
anv: Set MOCS for 3DSTATE_CONSTANT_XS on Gfx7.x as well
We were only setting this on Gfx9+. It's MBZ on Gfx8, but it exists
on Gfx7.x and doesn't have those restrictions there; we should set it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 21:12:32 +0000 (14:12 -0700)]
anv: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero. When we have entirely NULL surfaces, we just
default to isl's MOCS value for an internal depth buffer.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 20 Oct 2021 06:13:47 +0000 (23:13 -0700)]
iris: Fix MOCS for buffer copies
We were passing a MOCS of 0, which is uncached. Yikes.
Fixes:
c5b22441f1c ("iris: Fix buffer -> buffer copy_region")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 12:20:00 +0000 (05:20 -0700)]
iris: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is disabled stream output targets, MOCS shouldn't matter, as
there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 12:22:45 +0000 (05:22 -0700)]
iris: Set MOCS on NULL vertex buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is 3DSTATE_VERTEX_BUFFERS where we set NullVertexBuffer.
It shouldn't matter here, as there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for null vertex buffers.
We can assume an internal buffer and request isl's vertex buffer MOCS.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 12:31:55 +0000 (05:31 -0700)]
iris: Set MOCS on 3DSTATE_CONSTANT_ALL packets that disable all buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we missed
setting a non-zero MOCS was in 3DSTATE_CONSTANT_ALL packets which fully
disable all constant buffers. (If any constant buffer was present, we
would set an actual MOCS value.)
MOCS really shouldn't matter here, as there are no actual constant
buffers to be cached. That said, it should be harmless to do so, and
we can just assume a generic MOCS for internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Wed, 13 May 2020 22:08:33 +0000 (15:08 -0700)]
iris: Set MOCS on 3DSTATE_CONSTANT_XS on Gfx9+
We were leaving this blank due to a Broadwell restriction, causing our
constant buffers to be uncached. We later fixed this for Gfx12+, but
left Gfx9-11 without a fix. We should specify one.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 12:27:04 +0000 (05:27 -0700)]
iris: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero. When we have entirely NULL surfaces, we just
default to isl's MOCS value for an internal depth buffer.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 05:56:48 +0000 (22:56 -0700)]
iris: Set Bindless Sampler State MOCS
We don't use bindless sampler states today, but when we do, we'll want
them to have proper MOCS values. This also avoids asserts in upcoming
patches which enforce that MOCS isn't zero.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 05:55:34 +0000 (22:55 -0700)]
iris: Drop unnecessary parenthesis
Trivial.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 06:32:46 +0000 (23:32 -0700)]
blorp: Use a non-zero MOCS for disabled constant buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is disabled constant buffers, where MOCS shouldn't matter, as
there's no actual buffer to be cached.
That said, it should be harmless to set MOCS for these null constant
buffers; we can just assume a generic MOCS for internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 12:31:06 +0000 (05:31 -0700)]
blorp: Fill in MOCS for null depth/stencil/HiZ buffers.
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero. We just assume a generic internal MOCS when we
have entirely NULL surfaces.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 23:34:42 +0000 (16:34 -0700)]
blorp: Fill in MOCS even for SURFTYPE_NULL surfaces.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.
That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 21:16:38 +0000 (14:16 -0700)]
isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is SURFTYPE_NULL depth, stencil, and HiZ buffers, where MOCS
really shouldn't matter, as there's no actual surface to be cached.
That said, it should be harmless to set MOCS for these null surfaces.
We now set the one provided in info->mocs regardless of whether any
buffers actually exist or not.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 20:54:29 +0000 (13:54 -0700)]
isl: Fill in MOCS even for SURFTYPE_NULL surfaces.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications. One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.
That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 17:05:47 +0000 (10:05 -0700)]
intel/genxml: Change 3DSTATE_CONSTANT_XS::MOCS to be MBZ on Gfx8.
The Broadwell PRM says: "Constant Buffer Object Control State must
always be programmed to zero."
This patch changes the MOCS field in gen8.xml to be "mbz" type, so that
it's impossible to set it to a non-zero value.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 19 Oct 2021 06:06:25 +0000 (23:06 -0700)]
intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field
This is redundant with the existing "MOCS" field. We don't need both.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Tue, 26 Oct 2021 21:46:21 +0000 (14:46 -0700)]
intel/genxml: Add an "mbz" data type
There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.
This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct. We also update the decoder to handle it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Kenneth Graunke [Fri, 22 Oct 2021 09:33:04 +0000 (02:33 -0700)]
intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4
We had this field mislabeled as "Instruction Access Upper Bound", but
instruction state base address doesn't exist until Gfx5. This is
supposed to be the upper bound for indirect object base address,
matching the G45 copy.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
Pierre-Eric Pelloux-Prayer [Fri, 15 Oct 2021 16:24:25 +0000 (18:24 +0200)]
drirc: enable do_dce_before_clip_cull_analysis for ANSA
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>
Pierre-Eric Pelloux-Prayer [Thu, 16 Sep 2021 11:11:30 +0000 (13:11 +0200)]
glsl/drirc: add an option for gl_ClipVertex / gl_CullDistance checks
The GLSL spec says it's an error if a shader statically writes to these
2 variables.
Until this commit, Mesa refused to link a shader if it had an unused
function writing to one of these variables while another (used) function
wrote to the other.
This commit adds an option to perform dead function elimination after
the intra-stage linking step but before performing these checks.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12897>
Dylan Baker [Thu, 28 Oct 2021 17:44:08 +0000 (10:44 -0700)]
docs: update calendar and link releases notes for 21.2.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>
Dylan Baker [Thu, 28 Oct 2021 17:42:02 +0000 (10:42 -0700)]
docs: add sha256 sums for 21.2.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>
Dylan Baker [Thu, 28 Oct 2021 16:48:04 +0000 (09:48 -0700)]
docs: add release notes for 21.2.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13579>
Filip Gawin [Wed, 27 Oct 2021 16:45:00 +0000 (18:45 +0200)]
r300: improve precission of linear interpolation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13554>
Danylo Piliaiev [Wed, 27 Oct 2021 10:40:51 +0000 (13:40 +0300)]
ir3/ra: Check register file upper bound when updating preferred_reg
Otherwise we could get invalid reg in get_reg()
Would fix many dEQP-VK.ssbo.phys.layout.*
Fixes:
0ffcb19b9d9fbe902224542047c389a661fbf816 "ir3: Rewrite register allocation"
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13546>
shanshengwang [Tue, 26 Oct 2021 09:50:24 +0000 (17:50 +0800)]
radeon/vce: Limiting max supported refernce frames to 1 for h264 encoding
VCE currently restricted max_supported reference frames to 1
Signed-off-by: shanshengwang <shansheng.wang@amd.com>
Suggested-by: Suresh Guttula <suresh.guttula@amd.com>
Acked-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13543>
Samuel Pitoiset [Thu, 21 Oct 2021 16:00:22 +0000 (18:00 +0200)]
ac/nir: remove bogus assertion about the position for culling
It's undefined to not export a position but some applications rely
on that. The position is always initialized to 0,0,0,1 everywhere else
if not exported.
Fixes KHR-GL46.shader_image_load_store.multiple-uniforms with Zink.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13470>
Lionel Landwerlin [Thu, 28 Oct 2021 08:13:39 +0000 (11:13 +0300)]
intel/pps: reuse timestamp_frequency from intel_device_info
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
Lionel Landwerlin [Thu, 28 Oct 2021 08:13:00 +0000 (11:13 +0300)]
intel/pps: provide accurate min sampling period
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
Lionel Landwerlin [Thu, 28 Oct 2021 08:12:16 +0000 (11:12 +0300)]
intel/dev: printout timestamp period
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
Lionel Landwerlin [Wed, 27 Oct 2021 21:15:33 +0000 (00:15 +0300)]
docs: put a list of commands to setup perfetto
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
Lionel Landwerlin [Wed, 27 Oct 2021 21:09:14 +0000 (00:09 +0300)]
pps: add an intel config file
It was useful to set a colleague up on perfetto.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
Lionel Landwerlin [Wed, 27 Oct 2021 21:08:19 +0000 (00:08 +0300)]
pps: remove counter_ids fields
Those appear not to be recognized anymore by perfetto.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
Jordan Justen [Tue, 26 Oct 2021 07:54:58 +0000 (00:54 -0700)]
intel/dev/test: Assert (verx10 / 10) == ver
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13568>
Rhys Perry [Wed, 27 Oct 2021 08:34:44 +0000 (09:34 +0100)]
aco: use std::vector and IDSet in RA validator
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13541>
Iago Toral Quiroga [Wed, 27 Oct 2021 10:24:09 +0000 (12:24 +0200)]
broadcom/compiler: padding fixes to QPU assembly dumps
When there are dst/src modifiers it is pretty common that instructions
take too much space and lead to alignment issues that make code a lot
harder to read, so align the MUL and SIG columns a bit wider to avoid
this:
Before:
0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs; nop
0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48; nop
0x380c038b85b83282 fmax rf11, rf10, rf2; mov.ifa rf14, rf46
0x3800219ab503f359 and rf26, rf13, rf25; nop
0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48; nop ; thrsw
0x382c013fb5b8368e and rf63, rf26, rf14; mov.ifa rf4, rf46; thrsw
0x38002185b503ffc4 and rf5, rf63, rf4 ; nop
0x38002186b503f141 and rf6, rf5, rf1 ; nop
0x382031873503f186 vfpack tlb, rf6, rf6; nop ; thrsw
0x380031873503f18f vfpack tlb, rf6, rf15; nop
0x38003186bb03f000 nop ; nop
After:
0x380021828003faa8 fmax rf2, rf42.abs, rf40.abs ; nop
0x3800f186c503f0f0 fcmp.pushc -, rf3, rf48 ; nop
0x380c038b85b83282 fmax rf11, rf10, rf2 ; mov.ifa rf14, rf46
0x3800219ab503f359 and rf26, rf13, rf25 ; nop
0x3820f186c503f2f0 fcmp.pushc -, rf11, rf48 ; nop ; thrsw
0x382c013fb5b8368e and rf63, rf26, rf14 ; mov.ifa rf4, rf46 ; thrsw
0x38002185b503ffc4 and rf5, rf63, rf4 ; nop
0x38002186b503f141 and rf6, rf5, rf1 ; nop
0x382031873503f186 vfpack tlb, rf6, rf6 ; nop ; thrsw
0x380031873503f18f vfpack tlb, rf6, rf15 ; nop
0x38003186bb03f000 nop ; nop
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13545>
Mike Blumenkrantz [Wed, 27 Oct 2021 21:37:30 +0000 (17:37 -0400)]
zink: always use explicit lod for texture() when legal in non-fragment stages
implicit lod is something else entirely
fixes #5566
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13563>
Mike Blumenkrantz [Wed, 27 Oct 2021 20:32:55 +0000 (16:32 -0400)]
zink: set aspectMask for renderpass2 VkAttachmentReference2 structs
this is otherwise just garbage
fixes #5569
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13561>
Mike Blumenkrantz [Wed, 27 Oct 2021 20:37:03 +0000 (16:37 -0400)]
zink: use align64 for allocation sizes
avoid 32bit sint overflows
fixes #5568
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13560>
Mike Blumenkrantz [Wed, 27 Oct 2021 21:13:35 +0000 (17:13 -0400)]
zink: cache bo SpvId array types
this cuts down on a truckload of useless new validation spam
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13559>
Yiwei Zhang [Mon, 18 Oct 2021 06:49:30 +0000 (06:49 +0000)]
venus: implement vn_buffer_cache_entries_create
1. advertise high hit rate cache combinations, and we should limit the
caches to those only require device memory pool alloc
2. use size = 1 to ask for buffer memory requirements so that we do a
sanity check on our assumption of returned size and alignment. For
implementations don't meet our assumption, continue without cache.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
Yiwei Zhang [Mon, 18 Oct 2021 23:36:11 +0000 (23:36 +0000)]
venus: implement vn_buffer_cache_get_memory_requirements
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
Yiwei Zhang [Mon, 18 Oct 2021 18:03:11 +0000 (18:03 +0000)]
venus: implement vn_buffer_get_max_buffer_size
This change estimates the max_buffer_size with quick sort. Try to
avoid some traffic upon device creation time, but not worth adding a
buffer simple create api to avoid the extra requirement query traffic
since this is temporary.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
Yiwei Zhang [Fri, 15 Oct 2021 18:37:23 +0000 (18:37 +0000)]
venus: add buffer cache init and usage flows
1. struct vn_buffer_cache_entry for buffer memory requirements
2. struct vn_buffer_cache for all buffer related cached info
3. implement vn_buffer_cache_init
4. implement vn_buffer_cache_fini
5. empty vn_buffer_get_max_buffer_size
6. empty vn_buffer_cache_entries_create
7. implement vn_buffer_cache_entries_destroy
8. empty vn_buffer_cache_get_memory_requirements
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
Yiwei Zhang [Thu, 21 Oct 2021 06:06:10 +0000 (06:06 +0000)]
venus: add struct vn_image_memory_requirements
This aligns with vn_buffer_memory_requirements and can potentially
simplify future image memory requirements cache init.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>
Yiwei Zhang [Thu, 21 Oct 2021 05:56:30 +0000 (05:56 +0000)]
venus: add struct vn_buffer_memory_requirements
This will simplify later buffer cache api.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13428>