nir: Add nir_function_instructions_pass helper

Extract the logic. Convenience for working with real functions.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24687>

nir: use a _clone so users calling their variable clone don't get a warning

I've got code using clone name and it gets confused.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24687>

ci/freedreno: Add another excessive-constlen UBO skip.

Causes flakes in other tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24624>

Uprev Piglit to f7db20b03de6896d013826c0a731bc4417c1a5a0

https://gitlab.freedesktop.org/mesa/piglit/-/compare/ed58dfbd12be34fa3dab97a7a2987b890e0637f1...f7db20b03de6896d013826c0a731bc4417c1a5a0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24624>

util: Add convenience macros for linear allocator

Similar to the ones for ralloc.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25161>

vulkan/properties: Handle unsized arrays properly

Sadly we cannot autogenerate handling for them, so fall back to hand
written handling instead.

Fixes: eaee792 ("vulkan: Add a generated vk_properties struct")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25055>

tu: Fix heap size

It make no sense to advertise a bigger heap than what we can fit into
the GPU virtual address space.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25130>

freedreno/a6xx: ARB_shader_viewport_layer_array

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: Handle PIPE_BIND_BLENDABLE

We weren't advertising EXT_float_blend due to missing handling for the
BLENDABLE usage bit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: Use pipe_blit_info::sample0_only

Instead of trying to pass this back-door, and failing in a few cases we
go thru generic paths.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: EXT_depth_bounds_test

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: EXT_shader_image_load_formatted

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: EXT_demote_to_helper_invocation

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: ARB_texture_filter_minmax

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: ARB_sample_locations

Note, gl_SamplePosition (rgetpos), and therefore interpolateAtSample(),
doesn't work with sample location_enable=true.  For vulkan, "If the
current pipeline uses custom sample locations the value of any variable
decorated with the SamplePosition built-in decoration is undefined."
But ARB_sample_positions doesn't mention this.  Possibly the vk text
should be backported to the gl extension.  (If the app is specifying the
sample locations, it shouldn't need gl_SamplePosition.)

The upshot of this is 2 out of 3 tests that piglit arb_sample_locations
test tests fail, even though sample locations itself is working.
Possibly the test should be updated.  Or we could use driconf to hide
ARB_gpu_shader5 and ARB_sample_shading from this test.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: ARB_post_depth_coverage

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno: Implement ATI_meminfo

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: Re-write the function-of-doom

Re-write the program state building to align more closely with turnip,
for easier comparision.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: Re-work fd6_emit_shader

Shuffle around a bit of the state emit, so that it more closely matches
tu_emit_xs().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

freedreno/a6xx: Drop unused screen args

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

ir3+tu: Simplify ir3_find_sysval_regid callers

The test for NULL shader stage is pretty common so just move it into
ir3_find_sysval_regid().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24999>

r300: reduce number of iterations for vertex shader loops

Using the default value leads to occasional hangs on RV516 for unknown
reasons. Set it to 128 insted of 255.

dEQP and piglit are still happy and I don't expect any real app to hit
this, but lets see. As a side effect this boosts fps in the apps that
have non-unrollable vertex shaders (as the shaders now effectivelly run
almost two times faster) and ~5% dEQP runtime decrease.

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7934
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20873>

winsys/radeon: fix a race between bo import and destroy

This is similar to commit 85e74944c69 ("winsys/amdgpu: fix a race
between import and destroy") but for winsys/radeon.  In short, we need
to check the reference count again after bo_handles_mutex is held.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25133>

radv/ci: Document new flake

Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25140>

anv: remove misleading comment about batch_len

We don't fill batch_len later when chaining batches. But that doesn't
seem to be a problem, I checked i915.ko and nothing Gen8+ seems to use
batch_len. The new xe.ko exec ioctl doesn't even ask for batch_len.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24681>

anv/xe: return failure in case waiting for the vm_bind syncobj fails

Don't hide failures, we have xe.ko bugs related to that, such as:
    https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/496

The bind ioctl may fail if the application does something wrong, but
the wait really should never fail.

v2: Don't print an error message (Lionel).

Reviewed-by: José Roberto de Souza <jose.souza@intel.com> (v1)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24681>

anv/xe: make vm_binds async

Our sparse implementation will require us to issue partial unbinds,
but partial unbinds are not supported in synchronous vm_bind ioctls,
requiring us to to have our VM be marked with the ASYNC flag. This is
not properly documented and is subject to change in the next
iterations of the API.

Error handling with async binds is also not documented anywhere and is
being actively discussed in the mailing lists, so whatever we decide
to implement here is likely to end up changing in a few weeks. Also, I
haven't seen these errors happening in the real world, so for now
they're a very corner case. So for now just foward errors to
user-space and hope things work.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24681>

anv: add a new vm_bind vfunc

For Sparse Resources we need to be able to specify the address, size
and offsets and we also want to be able to issue multiple binds at the
same time. Extend xe_vm_bind_op() to handle those cases and add
the new vfunc.

v2:
 - use STACK_ARRAY() (Lionel)
 - no more need to work around xe.ko bug that was fixed (José)

Reviewed-by: José Roberto de Souza <jose.souza@intel.com> (v1)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24681>

anv: rename the vm_bind vfuncs

The only driver that has a vm_bind ioctl is xe.ko, and its vm_bind
ioctl is not called GEM vm_bind, it's just DRM_IOCTL_XE_VM_BIND
(without GEM anywhere). Back when i915.ko was going to have a vm_bind
ioctl it had GEM on its name, so I guess that's how "gem" appeared in
the naming here, but now nothing does, so let's get rid of it.

Also, these vfuncs we have are specifically made to bind and unbind
whole BOs, so rename them to vm_bind_bo() and vm_unbind_bo() in order
to try to clarify what they mean. The goal is to add a more generic
vm_bind() later that can do anything.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24681>

vulkan wsi: add support for PresentOptionAsyncMayTear

This commit adds tearing support for Xwayland

Signed-off-by: Xaver Hugl <xaver.hugl@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19125>

zink: set optimal_keys for turnip jobs

nobody cares about stipple on turnip for real world scenarios, so
testing it instead of the thing that people will actually want is pointless

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25037>

zink: imply ZINK_DEBUG=quiet if ZINK_DEBUG=optimal_keys is set on turnip

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25037>

zink: add ZINK_DEBUG=quiet

mainly for use with ZINK_DEBUG=optimal_keys on turnip since spamming
a warning like that constantly is pointless

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25037>

ci/zink: Add new zink-lvp flakes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25149>

ci/intel: Add new skqp flake

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25149>

ci/d3d12: Add new flake

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25149>

ci/radeonsi: Add new flake

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25149>

ci: Declare stages before jobs

It looks like GitLab 16.x requires us to declare the stages before we
declare any jobs, else it falls down resolving 'needs' with 'job is not
in any earlier stage'.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25149>

meson: support installation tags

the only thing missing is to tag custom install targets, namely:
 - ICDs (vulkan, glvnd, OpenCL, VA-API, VDPAU)
 - Vulkan layers
 - custom install script for megadrivers
 - drirc file

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24911>

v3dv: expand sampling from linear image hack to support multi-planar images

Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25048>

v3dv: add support for sampling simple 2D linear textures

V3D can't sample linear images (other than 1D), however, some applications
will require this to work. Particularly, our swapchain images may need to be
linear (for display), so sampling from them won't work.

This change detects the case where we are binding a descriptor which attempts
to sample from a simple 2D linear texture, transparently creates a tiled
copy of the image and rewrites the  descriptor to refer to the tiled image
instead. This will be slow but will allow some applications that require this
to work (i.e. some aspects of Android's user interface).

As of this patch, this only supports sampling linear images with a single
miplevel and layer from single-plane images in non-arrayed descriptors. We
could handle other cases too with a bit more work though.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9712
Tested-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25048>

Revert "ci: disable Collabora's LAVA lab for maintance"

This reverts commit https://gitlab.freedesktop.org/mesa/mesa/-/commit/c558c4955053eeb9476acefa148d414ff71cb47d

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25143>

v3dv: Rely on the internal tiled flag instead of the common vk structure

Common vk.tiling can have 3 states:

VK_IMAGE_TILING_OPTIMAL = 0,
VK_IMAGE_TILING_LINEAR = 1,
VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT = 1000158000,

The latter is checked by [1]

In this case, actual tiling can be either linear or tiled;
therefore, logic in v3dv_meta_copy will not work correctly.

[1]: https://gitlab.freedesktop.org/mesa/mesa/-/blob/39fca243bb914cea853e9d3502f1f38e6bf96ad4/src/vulkan/runtime/vk_image.c#L158

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25139>

tu: Split program draw state into per-shader states

This completely rewrites how uploading variants and emitting the program
state works, which will make fast linking significantly faster and lays
some of the groundwork for EXT_shader_objects. Variants are now
compiled and uploaded as part of creating a tu_shader, and a
a per-stage draw state is also created that contains all registers that
are only set based on one stage. The program state is split into
per-stage states, which come from the shaders, and VPC state which is
emitted at linking time. Pipelines now contain shaders, and importing
shaders from libraries when fast-linking just involves taking a
reference on the shader. While the command buffer code still uses the
old pipeline structures, the plan is to switch more and more things to
directly use the shaders or derived state from the shaders that gets set
by the pipeline, so that we can eliminate pipeline usage from
tu_cmd_buffer.cc to enable ESO.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

ir3: Add helper to determine when variant exceeds safe constlen

This will help us not compile extra variants as often in the unlinked
case, which will become the only case on turnip.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

freedreno, ir3, tu: Constify various uses of ir3_shader_variant

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Split up tu6_emit_vpc()

This started out as a place to set linkage-related registers, but it
gradually became a grab-bag of different things. In the future each
stage will have its own draw state, so we split out the parts that only
depend on a single stage into separate functions. Each piece of state we
can split out is another piece of state that won't have to be emitted
while fast-linking.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

ir3: Add ir3_find_input_loc() helper

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Pull entangled shader state into program config

There are a few cross-stage states that we absolutely have to wait to
emit until we know more than one stage. Pull these into the program
config draw state, so that we can split up the program draw state into a
per-stage draw state. For VK_EXT_shader_object, these will have to
emitted at draw time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu, freedreno/a6xx: Don't use VS for PrimID passthru state

Emit the registers solely based on whether FS reads PrimID, and assume
the HW will do the right thing and disable PrimID passthru when GS is
enabled. This untangles these registers so we can set them from the FS
draw state in the future.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Rename PrimID-related registers

It turns out that the hardware automatically selects whether PrimID
passthrough needs to happen based on whether GS is enabled, which means
that it's safe to always set these registers based whether PrimID is
read by the FS and the hardware will ignore them when GS is enabled. Use
the real names for these registers to make it less confusing when we
start to do that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Merge depth/stencil draw states

This removes more draw states that are commonly set together. We still
have a separate draw state for RB_DEPTH_CNTL, because it depends on
other things like the attachment state and depth clamp and it would be
more difficult for layers like zink to use a combined depth/stencil
state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Stop reusing base Vulkan dynamic state enums

We're about to remove the 1:1 correspondance between base Vulkan 1.0
dynamic states and draw states.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Merge PC_RASTER_CNTL into RAST draw state

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Merge SAMPLE_LOCATIONS and SAMPLE_LOCATIONS_ENABLE draw states

There's no need to separate them except that it was easier before, no
one will enable the second without also enabling the first. Now that
mesa will merge the states for us we can go ahead and merge them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

tu: Remove MSAA draw state

We only need to emit MSAA state once per subpass at most, unless the
pipeline switches primitive types or for framebuffer-less subpasses
(which always use sysmem anyway). Therefore it seems like draw state
skipping isn't going to bring much benefit here, and having it as a draw
state in the first place is a remnant of how this used to be part of the
pipeline state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25076>

anv: tell blorp to do mesh stuff only if it's enabled

Otherwise blorp operations will set dirty bits for mesh that we don't
expect at pipeline state emission time.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: ensure pipelines have all state

While we don't need to emit all of the unused mesh/task states when mesh
is disabled, if we don't have them we fail some assertions in the
difference checks due to the corresponding state being empty.
This may happen when going from a mesh pipeline to a non-mesh one, or
one that uses task shaders to one that doesn't.

It may be possible to avoid having to do this, but I'd rather start from
a working state and optimize it later.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: fix missing 3DSTATE_SBE_CLIP emission

Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: fix missing 3DSTATE_SBE_MESH emission

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: ensure partially packed instructions are emitted in the pipeline

Any partially packed instructions should always be pre-packed by
genX_pipeline.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: ensure mesh pipeline have all pre-rasterization stages disabled

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 44656f98d5 ("anv: split pipeline programming into instructions")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: emit 3DSTATE_URB_ALLOC_(MESH|TASK) only when mesh shaders are enabled

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

anv: fix 3DSTATE_VFG emission

3DSTATE_VFG was moved into a section that only gets emitted for legacy
pipelines, not mesh pipelines.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0ce772bd19 ("anv: split 3DSTATE_VFG emission")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25109>

radeonsi: sets OPTIMAL_BIN_SELECTION to 0 if using bottom_edge_rule

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24725>

radeonsi: stores bottom_edge_rule option in the rasterizer state

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24725>

ci: disable Collabora's LAVA lab for maintenance

This is to inform you of some planned downtime in the LAVA lab as follows:

* Start: 2023-09-11 08:00 BST (UTC+1)
* End: 2023-09-11 12:00 BST (UTC+1)

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25141>

radv: fix enabling DGCC

This was broken if only DGC (graphics) is enabled.

Fixes: 559da067559 ("radv: implement NV_device_generated_commands_compute")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25126>

clover/llvm: move to modern pass manager.

This seems like it should work, but I haven't tested it yet.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24879>

lima: fix plbu block stride calculation

For some specific texture sizes, notably some texture sizes with width
4096, block stride calculation could end up calculating stride 256 which
is an invalid value.
In those specific cases, this could cause rendering artifacts or
application/driver crashes.

Cc: mesa-stable
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25084>

radv/rt: Enable monolithic pipelines

Store can_inline inside the stages to avoid rerunning the analysis pass
for library stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>

radv/rt: Add monolithic raygen lowering

Ray traversal is inlined to allow for constant folding and avoid
spilling.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>

radv/rt: Store NIR shaders separately

In order to compile monolithic shaders with pipeline libraries, we need
to keep the NIR around for inlining recursive stages.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>

nir/inline_uniforms: fix oob access with nir_find_inlinable_uniforms

the array dimensionality needs to match nir_add_inlinable_uniforms even if
only the first member is used

Fixes: 0c0fb216dd6 ("nir/inline_uniforms: Allow possibility of more than one UBO")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25063>

zink: delete all psiz=1.0 stores if maintenance5 is present

this frees up an output location woooo

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24782>

zink: slightly refactor psiz deletion during linking

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24782>

Revert "ci: taking igalia farm offline"

This reverts commit a69ffbd08a44032d0f12c5739382cefc8a5d7f50.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25136>

zink: use HIC for image subdata when possible

this has a lot of caveats:
* extension must be supported
* resource must have usage bit set
* resource must not have any pending batch usage
* resource must be in supported layout

if all of these conditionals pass, then HIC can be used for direct image subdata

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: check/use suboptimal HIC during ici init

this allows implicit use of HIC where possible while rejecting it when
it would cause performance loss

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: use some return codes for check_ici errors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: fix some off-by-one indentation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: add a fixup method for extra driver props

some extensions have "extra" props which need the get_count -> get_prop_array
dance, and codegen is too stupid to figure this out (and probably always will be)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: disable HIC without resizable BAR

this otherwise ooms the system

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: move mem type detection up in file

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: hook up VK_EXT_host_image_copy

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

lavapipe: don't advertise UNDEFINED layout for HIC

this is illegal

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

lavapipe: handle VkHostImageCopyDevicePerformanceQueryEXT

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: use VkFormatProperties3

but wrap it in a smaller type to save some space

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

zink: simplify redundant is_buffer check

it's in the params

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>

ci: bump VVL to 1.3.263

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24925>

intel/dev: Update device string for MTL PCI ID 0x7d55

Ref: bspec 55420
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25073>

nvk: Invalidate the texture cache in PipelineBarrier

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>

nvk: Set the discard bit for Z/S self-deps

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>

nvk: Don't add a dummy attachment when gl_SampleMask is written

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>

intel/compiler: Don't evict for workgroup-scope fences

Flushing and invalidating caches isn't necessary for workgroup scope
fences.  In fact, the DP_FLUSH_TYPE docs (BSpec 54041) say:

   "If the fence scope is Local or Threadgroup, HW ignores the flush
    type and operates as if it was set to None(no flush)"

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

intel/compiler: Combine control barriers with identical memory semantics

This prevents the second barrier generating a spurious, identical fence
message as the first barrier.

fossil-db stats on Alchemist:

   Totals:
   Instrs: 196513342 -> 196512777 (-0.00%); split: -0.00%, +0.00%
   Cycles: 14271426028 -> 14271404569 (-0.00%); split: -0.00%, +0.00%
   Send messages: 8021892 -> 8021770 (-0.00%)

   Totals from 46 (0.01% of 653252) affected shaders:
   Instrs: 76761 -> 76196 (-0.74%); split: -0.75%, +0.01%
   Cycles: 2027946 -> 2006487 (-1.06%); split: -1.45%, +0.39%
   Send messages: 7589 -> 7467 (-1.61%)

Nothing in shader-db was affected.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

anv: Use nir_opt_barrier_modes() to drop unnecessary barriers

fossil-db stats on Alchemist:

   Totals:
   Instrs: 196514947 -> 196513342 (-0.00%); split: -0.00%, +0.00%
   Cycles: 14271450761 -> 14271426028 (-0.00%); split: -0.00%, +0.00%
   Send messages: 8022316 -> 8021892 (-0.01%)

   Totals from 43 (0.01% of 653252) affected shaders:
   Instrs: 98558 -> 96953 (-1.63%); split: -1.63%, +0.00%
   Cycles: 15867801 -> 15843068 (-0.16%); split: -0.17%, +0.02%
   Send messages: 8997 -> 8573 (-4.71%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

glsl: Use nir_opt_barrier_modes() to drop unnecessary barriers

iris shader-db stats on Alchemist:

    total instructions in shared programs: 23150249 -> 23142733 (-0.03%)
    instructions in affected programs: 157322 -> 149806 (-4.78%)
    helped: 105
    HURT: 2
    helped stats (abs) min: 2 max: 821 x̄: 71.61 x̃: 15
    helped stats (rel) min: 0.13% max: 27.56% x̄: 6.21% x̃: 2.35%
    HURT stats (abs)   min: 1 max: 2 x̄: 1.50 x̃: 1
    HURT stats (rel)   min: 0.18% max: 0.23% x̄: 0.20% x̃: 0.20%
    95% mean confidence interval for instructions value: -101.99 -38.50
    95% mean confidence interval for instructions %-change: -7.59% -4.58%
    Instructions are helped.

    total sends in shared programs: 1036916 -> 1035366 (-0.15%)
    sends in affected programs: 15274 -> 13724 (-10.15%)
    helped: 108 / HURT: 0
    helped stats (abs) min: 1 max: 162 x̄: 14.35 x̃: 3
    helped stats (rel) min: 0.88% max: 33.83% x̄: 9.81% x̃: 5.05%
    95% mean confidence interval for sends value: -20.79 -7.92
    95% mean confidence interval for sends %-change: -11.66% -7.95%

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

dxil: Set UAV_FENCE_THREAD_GROUP any time global isn't required

With the new nir_opt_barrier_modes() pass, we may encounter control
barriers with no memory modes set, such as:

   @barrier () (execution_scope=WORKGROUP, memory_scope=WORKGROUP, mem_semantics=ACQ|REL, mem_modes=0)

The DXIL validator documentation [1] mentions an
INSTR.BARRIERMODENOMEMORY validation rule:

   "sync must include some form of memory barrier - _u (UAV) and/or
    _g (Thread Group Shared Memory). Only _t (thread group sync) is
    optional."

We were generating a dx.op.barrier instruction with only one flag,
DXIL_BARRIER_MODE_SYNC_THREAD_GROUP.  This seems to run afoul of the
above validator rule.  So, this patch adjusts the code generator to
set DXIL_BARRIER_MODE_UAV_FENCE_THREAD_GROUP too, whenever
UAV_FENCE_GLOBAL isn't required.

[1] https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/DXIL.rst

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>

virgl, nir_to_tgsi: Add a hack for promoting partial memory barriers

Most drivers will want nir_opt_barrier_modes() to optimize out
unnecessary memory barrier modes.  However, virgl has to translate
back to GLSL, which means it can really only handle partial memory
barriers in compute shaders today, because there isn't a proper
way to express them otherwise.  Just ask nir_to_tgsi to promote
these back to full barriers as a workaround.

See KHR-GL43.shader_storage_buffer_object.advanced-readWrite-case1
on virpipe-on-gl as a case where this hack is needed.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>