Boris Brezillon [Wed, 7 Apr 2021 13:31:16 +0000 (15:31 +0200)]
panfrost: Decode pre/post frame DCDs
Bifrost FB descritptors can be attached 3 DCDs describing pre/post frame
operations (pre frames DCDs can be used to preload the tile buffers).
Decode them when mode != NEVER.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:27:53 +0000 (15:27 +0200)]
panfrost: s/pandecode_vertex_tiler_postfix_pre/pandecode_dcd/
We will soon use this function to decode pre/post frame DCDs which are
not part of a job descriptor.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:23:11 +0000 (15:23 +0200)]
panfrost: Add the early ZS pre frame mode
We will use that one when preloading ZS buffers.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:22:12 +0000 (15:22 +0200)]
panfrost: Add align info to the draw and draw padding definitions
Needed if we want to allocate pre/post frame draw descriptors.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:34:22 +0000 (15:34 +0200)]
panfrost: Add an helper to emit fragment jobs
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:56:19 +0000 (09:56 +0200)]
panfrost: Add various helpers to simplify FB desc emission
Now that image and image views are gallium-agnostic and contain enough
information, we can provide generic helpers to emit FB descriptors and
their dependencies, thread storage and tiler descriptors.
This helpers will be re-used in the Vulkan driver.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 2 Apr 2021 13:06:52 +0000 (15:06 +0200)]
pan/midg: Use the sampler index passed to the texture instruction
Sampler index and texture index can differ.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:52:29 +0000 (09:52 +0200)]
panfrost: Pass a const device to panfrost_sample_positions()
This function doesn't modify the dev object, we can constify this
argument.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:50:41 +0000 (09:50 +0200)]
panfrost: Provide a helper to retrieve image surface pointers
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:49:00 +0000 (09:49 +0200)]
panfrost: Provide a helper to calculate the polygon list size
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 15:24:47 +0000 (16:24 +0100)]
panfrost: Pass an image view to panfrost_new_texture()
pan_image_view contains everything we need to emit a texture
descriptor. Pass this object instead of the dozen of arguments
we have now.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 10:14:28 +0000 (11:14 +0100)]
panfrost: Patch the gallium driver to use pan_image_layout_init()
Now that we have a generic implementation, we can use it and get rid
of panfrost_setup_layout().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 10:13:05 +0000 (11:13 +0100)]
panfrost: Add a pan_image_layout_init() helper
We will need it for Vulkan.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 17:50:20 +0000 (18:50 +0100)]
panfrost: Move special Z32_S8X24 case out of panfrost_setup_layout()
We are about to move the panfrost_setup_layout() logic out of the
gallium driver, and the Z32_S8X24 split is not mandatory (some GPU
support this format natively). Let's move this special case out of
panfrost_setup_layout() and patch the format of the first plane
instead.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 17:35:52 +0000 (18:35 +0100)]
panfrost: Move out-of-band CRC info to pan_image
We already have the data BO stored there, let's move the out-of-band
CRC BO too. We also add a CRC mode to pan_image_layout so we can easily
know where the CRC resides.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 17:12:12 +0000 (18:12 +0100)]
panfrost: Add an offset field so we can attach a sub-buffer to an image
Needed for Vulkan.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 16:33:47 +0000 (17:33 +0100)]
panfrost: Split pan_image in two
Move the image view bit out of pan_image and create a separate
pan_image_view struct. Once this is done we can embed a pan_image
object in panfrost_resource which will be referenced by the image
view that we pass to panfrost_load_{midgard,bifrost}().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 15:31:19 +0000 (16:31 +0100)]
panfrost: Add extra info to the pan_image_layout struct
This means duplicating some of the bits we already have in the
pipe_resource object embedded in panfrost_resource, but if will also
allow us to move some code out of the gallium driver without requiring
copy those fields every time we call a generic helper.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 18:12:39 +0000 (19:12 +0100)]
panfrost: Stop passing a depth > 1 when creating 2D textures
The depth field is ignored if dim != 3D, but it's a bit confusing.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 15:28:03 +0000 (16:28 +0100)]
panfrost: Add a format field to pan_image_layout
We will need this information at the layout level if we want to move
some of the code out of the gallium driver and share it with the
Vulkan driver. Let's get rid of panfrost_resource.internal_format which
basically encodes the same thing.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 14:17:08 +0000 (15:17 +0100)]
panfrost: Move image states out of pan_image_layout
The layout is supposed to encode image miplevels/surfaces layout, not
the state data stored in the buffers. It doesn't matter for a gallium
driver, since resources are expected to hold both a layout and a state,
but Vulkan is a bit different. In Vulkan, the image state is explicitly
passed by the user when starting a render pass (vkCmdBeginRenderPass()),
and might evolve depending on the operation done in this render pass.
This state is not effective until the command buffer is queued and
executed. For these reasons, keeping the image state attached to the
VkImage object is not an option, but we'd still like to re-use the
layout and state objects, and all common helpers acting on those objects.
Let's move the state bits out of the layout to make that possible.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 13:19:37 +0000 (14:19 +0100)]
panfrost: s/panfrost_slice/pan_image_slice_layout/
We are about to move slice states out of the panfrost_slice object,
but before we do that, let's rename the existing struct to reflect what
this object refers to.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Connor Abbott [Mon, 7 Dec 2020 13:54:25 +0000 (14:54 +0100)]
vtn: Handle ZeroExtend/SignExtend image operands
These decorations allow you to override the signedness of image
instructions. This means that we have to override the type we get from
the sampled image.
Apparently both Intel and AMD get the type from the descriptor rather
than the instruction, but this appears to not be the case with Adreno,
which is why this wasn't noticed until now. So this probably won't fix
any preexisting bugs, but it's required to fix
dEQP-VK.image.extend_operands_spirv1p4.* when exposing VK_KHR_spirv_1_4
on turnip.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7968>
Lucas Stach [Tue, 13 Apr 2021 14:42:57 +0000 (16:42 +0200)]
Revert remaining half of "gallium/dri2: Pass the resource that corresponds to the plane"
As documented in
6ec7e0d40664 (gallium: document convention for get_handle
calls on multi-planar resources) it's the drivers responsibility to walk
the chain of resources for multi-planar resources. The get_handle interface
should always be called with the base resource by the frontend.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10212>
Juan A. Suarez Romero [Tue, 13 Apr 2021 08:00:14 +0000 (10:00 +0200)]
v3dv: fix assertion
Ensure subpass_idx has a valid value; we use "-1" as invalid one.
Fixes CID#1468096 "Macro compares unsigned to 0 (NO_EFFECT)"
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10203>
Juan A. Suarez Romero [Thu, 8 Apr 2021 16:27:10 +0000 (18:27 +0200)]
v3d: use GS_BIN inputs as VS_BIN outputs
When creating the Vextex Shader bin, only store outputs that will be
read later as inputs by the Geometry Shader bin.
This fixes
KHR-GLES31.core.geometry_shader.rendering.rendering.lines_input_triangle_strip_output_line_loop_drawcall
(exposed by previous commit).
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10129>
Juan A. Suarez Romero [Thu, 8 Apr 2021 16:20:08 +0000 (18:20 +0200)]
broadcom/compiler: use VPM offsets in GS load_per_vertex input
Vertex Shader has a store_out lowering pass that converts gallium driver
locations in offsets inside the VPM.
One of the consequences is that these offsets are consecutives; that is,
if the VS stores VARYING_SLOT_VAR0.xyz and VARYING_SLOT_VAR1.xyzw, there
isn't a hole in the VPM offsets for the un-stored VARYING_SLOT_VAR0.w.
Thus we need to change how the VPM offset is computed in the Geometry
Shader when loading the inputs.
This bug is exposed by !9050.
v2 (Iago):
- Include explanatory comment.
- Use assert.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10129>
Bas Nieuwenhuizen [Tue, 13 Apr 2021 09:21:36 +0000 (11:21 +0200)]
radv: Re-enable retiling.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10037>
Juan A. Suarez Romero [Tue, 6 Apr 2021 11:24:42 +0000 (13:24 +0200)]
ci/broadcom: use SNMP to turn on/off devices
So far we were using a telnet-based script to communicate with the PoE
Switch to turn on/off the network ports the DUTs are connected.
But this script does not seem very reliable because from time to time the
switch fails to execute the steps in the script.
As the PoE Switch we use is a smart one with support for SNMP protocol,
it would be easier to use it to handle it, which allows to turn on/off
the ports without going through the nasty telnet steps
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9954>
Samuel Pitoiset [Mon, 12 Apr 2021 16:00:51 +0000 (18:00 +0200)]
radv: fix needed dynamic state for VRS
If the pipeline struct isn't found, the state might still be dynamic.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10193>
Erik Faye-Lund [Mon, 29 Mar 2021 10:45:41 +0000 (12:45 +0200)]
compiler/glsl: do not cast struct to string
When formatting the error here, we're currently casting an
ast_type_qualifier as a string.
But we don't need to use a string here at all, because we know from
context exactly what qualifier we're talking about, because the
if-statements explicitly check for the uniform-qualifier.
So let's just hard-code the format-string to reference the right
qualifier instead of the string-shenanigans. The latter cannot do the
right thing.
Fixes:
2d03f48a65a ("glsl: Add parsing for GLSL uniform blocks.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9911>
Erik Faye-Lund [Mon, 29 Mar 2021 10:36:28 +0000 (12:36 +0200)]
compiler/glsl: drop rogue argument to _mesa_glsl_error
This arugment is not present int the format-string, so we shouldn't pass
it to _mesa_glsl_error either.
Noticed by Coverity.
Fixes:
02dc74fbd72 ("glsl: parse invocations layout qualifier for ARB_gpu_shader5")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9911>
Marek Olšák [Mon, 8 Feb 2021 11:06:24 +0000 (06:06 -0500)]
st/mesa: fix nir_lower_io if it's done right after IO vectorization
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 14:32:25 +0000 (09:32 -0500)]
gallium: add PIPE_SHADER_CAP_FP16_CONST_BUFFERS for FP16 uniforms
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 14:44:04 +0000 (09:44 -0500)]
glsl: lower mediump uniforms to FP16 based on an option
Everything else is done - just allow it.
v2: update lower_precision_test.py
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Sun, 14 Feb 2021 12:21:31 +0000 (07:21 -0500)]
mesa: implement glGetActiveUniform for FP16 uniforms
We must return the types before lowering to 16 bits.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Sun, 14 Feb 2021 12:02:13 +0000 (07:02 -0500)]
mesa: implement glGetUniform for FP16 uniforms
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 13:44:31 +0000 (08:44 -0500)]
mesa: implement glUniform for packed FP16 uniforms
Let's just say that this passes dEQP.
If you think the _mesa_float_to_half conversions are costly, you can
enable FP16 uniforms only if the CPU supports F16C, which is fast.
Drivers will control whether this is used, not common code.
ARM will need something that is equivalent to F16C.
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 13:14:07 +0000 (08:14 -0500)]
glsl: pack 16-bit uniforms in the NIR linker
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Alyssa Rosenzweig [Mon, 3 Aug 2020 19:21:16 +0000 (15:21 -0400)]
nir: Add varying precision linking helper (v2)
It is useful for the precisions of varyings to match across shader
stages at link-time to enable precision lowering optimizations, which
would otherwise require costly draw-time fixups.
The goal is to enable `producer->precision == consumer->precision` to be
an invariant drivers may rely on for linked shaders.
v2: keep transform feedback outputs at mediump - mareko
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Mon, 8 Feb 2021 02:10:08 +0000 (21:10 -0500)]
nir: add many passes that lower and optimize 16-bit input/outputs and samplers
Added:
* a pass that renumbers bases of IO intrinsics
* a pass that converts mediump IO to 16 bits, optionally using the new
packed varying slots
* a pass that sets (forces) mediump in IO intrinsics (for testing)
* a pass that remaps VARYING_SLOT_VAR[0..15]_16BIT to VARYING_SLOT_VAR[0..31]
(if some shader stages don't want packed varyings)
* a pass that folds type conversions around texture opcodes into those
opcodes (e.g. tex(f2f32(coord), ..) is changed into tex accepting f16)
* a pass that changes (legalizes) sampler src and dst types based on specified
hw constraints (e.g. derivatives must be the same type as coordinates)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Tue, 9 Feb 2021 15:58:51 +0000 (10:58 -0500)]
nir: add new VARYING_SLOTs and shader info for packed 16-bit varyings
This allows mediump inputs and outputs to be trivially lowered into packed
16-bit varyings where 1 slot is occupied by 2 16-bit vec4s, without any
packing instructions in NIR and without any conflicts with 32-bit varyings.
The only thing that is changed is IO semantics in intrinsics to get packed
16-bit varyings.
This simplifies supporting 16-bit types for drivers that have 32-bit slots
everywhere except the fragment shader where they can do 16-bit interpolation
on either the low or high half of each slot.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Tue, 9 Feb 2021 16:08:11 +0000 (11:08 -0500)]
nir: add src and dest types to all IO loads and stores for mediump
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Mon, 8 Feb 2021 00:57:09 +0000 (19:57 -0500)]
compiler: move TEXTURE_COORD/VERTEX_GENERIC_ATTRIB limits into shader_enums.h
because they are used there.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Jesse Natalie [Mon, 12 Apr 2021 02:15:35 +0000 (19:15 -0700)]
nir_opt_deref: ptr_as_array(deref_cast<T*>(x))[0] isn't the same as x[0] if the cast has alignment
This breaks CLOn12's handling of CL CTS test_basic vector_creation for char3 (at least).
Removing this cast causes us to try to load from a deref with no alignment info.
Fixes:
99bb2a4d ("nir/opt_deref: Don't remove casts with alignment information")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
Jesse Natalie [Mon, 12 Apr 2021 02:13:44 +0000 (19:13 -0700)]
vtn: Support scoped control barriers for OpenCL too
The current handling for SPIR-V memory semantics is very specific to
the wording in the SPIR-V spec, which breaks its handling of OpenCL
(compared to what we had working downstream before merging upstream).
Update/relax the logic here to support CL's barrier(CLK_GLOBAL_MEM_FENCE);
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
Marek Olšák [Mon, 5 Apr 2021 00:19:55 +0000 (20:19 -0400)]
radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos
just deduplicate the code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 23:37:01 +0000 (19:37 -0400)]
radeonsi: move binding the internal compute shader into si_launch_grid_internal
instead of doing it in each function
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 21:01:01 +0000 (17:01 -0400)]
radeonsi: enable DCC for MSAA 4x and 8x on gfx9
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 20:58:29 +0000 (16:58 -0400)]
radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 20:14:23 +0000 (16:14 -0400)]
radeonsi: fix and enable full DCC with MSAA 2x on gfx9
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 22 Mar 2021 23:43:53 +0000 (19:43 -0400)]
ac,radeonsi: rewrite DCC retiling without the DCC retile map
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.
The RADV code is disabled.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Tue, 23 Mar 2021 01:21:30 +0000 (21:21 -0400)]
ac/surface: limit the number of swizzle modes that can have displayable DCC
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 19:52:44 +0000 (15:52 -0400)]
ac/surface: add a test of DccAddrFromCoord prototype outside of addrlib
The test takes over 2 minutes on a 12C/24T CPU with OpenMP.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 5 Apr 2021 18:01:37 +0000 (14:01 -0400)]
meson: add an optional OpenMP dependency for AMD tests
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 19:51:36 +0000 (15:51 -0400)]
amd/addrlib: expose DCC address equations to drivers
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 7 Apr 2021 21:20:53 +0000 (17:20 -0400)]
ac/surface/tests: fix a random segfault in the modifier test
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 20:05:40 +0000 (16:05 -0400)]
ac/surface/tests: test Sienna Cichlid and Navy Flounder
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 31 Mar 2021 11:58:28 +0000 (07:58 -0400)]
ac/surface: only apply the 3D swizzle mode tuning to gfx10+
This fixes an addrlib failure on gfx9.
Fixes:
b43f40166cd "ac/surface: select best swizzle mode for 3D sampler performance"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 24 Mar 2021 02:53:00 +0000 (22:53 -0400)]
radeonsi: allow DCC_DECOMPRESS via CB with MSAA textures
The shader-based codepath doesn't support it.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Wed, 31 Mar 2021 10:50:14 +0000 (06:50 -0400)]
radeonsi: try to fix DCC coherency issues with DCC decompression
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 29 Mar 2021 06:24:39 +0000 (02:24 -0400)]
radeonsi: refine fast clears for small buffers, always use them for large HTILE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 20:57:15 +0000 (16:57 -0400)]
radeonsi: do Z-only or S-only HTILE clear using a compute shader doing RMW
This adds a clear_buffer compute shader that does read-modify-write to
update a subset of bits in HTILE.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 16:17:17 +0000 (12:17 -0400)]
radeonsi: when transitioning to TC-compat HTILE, try to do a proper clear
instead of always clearing to uncompressed.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 16:01:04 +0000 (12:01 -0400)]
radeonsi: enable DCC fast clears for non-zero mipmap levels and 0/1 clear values
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 07:43:44 +0000 (03:43 -0400)]
radeonsi: implement fast Z/S clears using clear_buffer on HTILE
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 07:41:59 +0000 (03:41 -0400)]
radeonsi: indent the code for TC-compatibility HTILE transition
So that HTILE clears can be nicely inserted into a new else statement there.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 07:12:21 +0000 (03:12 -0400)]
radeonsi: add si_can_fast_clear_depth/stencil helpers
for later use
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 04:17:44 +0000 (00:17 -0400)]
radeonsi: clean up some mess around htile_stencil_disabled
Set the final value in si_texture_create_object, so that other places
don't have to derive it redundantly.
The only thing to remember is that HTILE stencil can be enabled when
stencil is not present, and it can be disabled when stencil is present
due to various workarounds.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 21 Mar 2021 00:29:33 +0000 (20:29 -0400)]
radeonsi: parallelize Z/S conversion into TC-compatible with fast color clears
It's not really a fast clear, but it's the next logical step towards doing
HTILE clears here.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sat, 20 Mar 2021 23:59:06 +0000 (19:59 -0400)]
radeonsi: implement Z/S fast clear for non-zero mipmap levels
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sat, 20 Mar 2021 00:47:48 +0000 (20:47 -0400)]
radeonsi: implement per-level DCC and CMASK fast clears for gfx10+
Fast clears are only used for level 0. This enables clearing level 0
of CMASK and DCC on gfx10+ when there are multiple mipmap levels.
vi_dcc_clear_level can also clear any level now.
Mipmapped array textures are still cleared slowly.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 23:05:13 +0000 (19:05 -0400)]
radeonsi: allow trivial DCC clears for shared textures with DCC constant encode
This relaxes the existing restriction.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Thu, 18 Mar 2021 02:11:19 +0000 (22:11 -0400)]
radeonsi: restructure DCC disablement into a switch
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Tue, 16 Mar 2021 02:17:39 +0000 (22:17 -0400)]
radeonsi: don't cache FMASK transactions from CB in L2
FMASK is usually pretty large. It's better to leave the cache to shaders.
FMASK stores are still cached, but they can be evicted sooner, which is
the same as other color stores. Only DCC, HTILE, and CMASK are cached.
I haven't benchmarked this, but it seems like the right thing to do.
This only affected APUs.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Nanley Chery [Tue, 17 Sep 2019 23:16:04 +0000 (16:16 -0700)]
iris: Support I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
With a resolution of 1600x1200, I measured FPS increases in:
* glxgears 18.04% +/- 0.65% (n=691)
* Nexuiz 3.58% +/- 0.09% (n=553)
compared to the master branch at commit
3f614c6f7cb97ffc4db2d6c9e222e744871e33d3.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Fri, 20 Sep 2019 01:13:46 +0000 (18:13 -0700)]
iris: Support RC_CCS_CC modifier in plane queries
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Tue, 17 Sep 2019 23:49:55 +0000 (16:49 -0700)]
iris: Support clear color plane imports for RC_CCS_CC
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Tue, 19 Mar 2019 21:11:34 +0000 (14:11 -0700)]
isl: Describe I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
v2. Simplify the diff. (Jason)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Tue, 1 Sep 2020 18:42:48 +0000 (11:42 -0700)]
drm-uapi: Update drm_fourcc.h for new TGL modifier
Pull in the header from drm-next commit
32c3d9b0f51ee1e6bb0160496b97e50b5caca4d0. Among other things, this
brings in the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Nanley Chery [Mon, 22 Feb 2021 18:54:30 +0000 (10:54 -0800)]
iris: Set BO maps to NULL in bo_free
bo_free is called on external BOs when there are no objects left which
reference them. The function unmaps the address range associated with
any maps which occured. However, if the BO is busy (not idle), it
doesn't mark the pointer to the start address as invalid. This can lead
to a segfault later on.
At the end of bo_free, these BOs are still present in the handle hash
table. If such a BO is reused (i.e., when a DMABUF with the same handle
is reimported) and the driver attempts to get another mapping, the
bufmgr will incorrectly assume that the map pointer is still valid and
reuse it. This leads to a segfault. Set the pointer to NULL to mark it
as invalid.
Enables iris to run and pass the piglit test,
ext_image_dma_buf_import-reimport-bug.
Cc: mesa-stable
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9230>
Mike Blumenkrantz [Wed, 7 Apr 2021 13:05:12 +0000 (09:05 -0400)]
aux/trace: do deep dumps of fb state for triggered traces
having the full surface info available here is very useful
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
Mike Blumenkrantz [Wed, 7 Apr 2021 12:53:40 +0000 (08:53 -0400)]
aux/trace: dump current fb state on trigger-mode draw if it hasn't been seen yet
this info is important to have for a given frame, but it requires that the base
structs be copied and stored to the trace context for later use
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
Mike Blumenkrantz [Wed, 7 Apr 2021 12:23:50 +0000 (08:23 -0400)]
aux/trace: enhance trigger mode to dump context states during bind
when dumping a single frame, the creation info for these states hasn't been
dumped yet, so always dump it during bind so it's visible
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10093>
Chia-I Wu [Sat, 10 Apr 2021 05:49:21 +0000 (22:49 -0700)]
venus: check vn_renderer_info::vk_xml_version
When crosvm does not support venus, it still advertises
VIRGL_RENDERER_CAPSET_VENUS but provides no or zeroed capset data.
vk_xml_version will be zero.
It is a good idea to verify vk_xml_version anyway.
v2: print required version suggested by Ryan
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10192>
Eric Anholt [Thu, 1 Apr 2021 23:17:32 +0000 (16:17 -0700)]
ci: bump bare-metal kernel to bring in an a530 stability fix
and while I'm here, drop a workaround for back when we had binary
snapshots of the a530 kernel without compression support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10047>
James Park [Fri, 19 Mar 2021 08:47:21 +0000 (01:47 -0700)]
amd: Hide drm_fourcc.h on Windows
Declare missing definitions instead.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>
James Park [Fri, 4 Dec 2020 04:25:54 +0000 (20:25 -0800)]
amd: Hide amdgpu_drm.h on Windows
Declare missing definitions instead.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9708>
Icecream95 [Thu, 21 Jan 2021 03:23:49 +0000 (16:23 +1300)]
panfrost: Add fast path for graphics work group computation
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
Icecream95 [Tue, 19 Jan 2021 10:40:26 +0000 (23:40 +1300)]
panfrost: Align BO size to 4096 bytes
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
Icecream95 [Mon, 8 Feb 2021 09:50:27 +0000 (22:50 +1300)]
panfrost: Only add resource checksum BOs to the batch once
Previously panfrost_batch_add_bo was called MAX_MIP_LEVELS times on
the same batch.
Fixes:
cbf68b21fb2 ("panfrost: Move checksum_bo to panfrost_resource")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10158>
James Park [Tue, 23 Feb 2021 09:55:28 +0000 (01:55 -0800)]
ac/rgp: BSD elf library compatibility
Allow compilation on Windows using modified BSD elf library.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9210>
Thong Thai [Fri, 9 Apr 2021 14:26:59 +0000 (10:26 -0400)]
radeon: Add cropping to encoded H.265 when padding is used
Because the VCN encoder needs the surface to be memory aligned, the
resolution of the image passed to the encoder might be larger and have
extra padding added - this change crops the resulting output to
compensate for the extra padding that might have been added.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4559
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10137>
Vasily Khoruzhick [Thu, 8 Apr 2021 06:32:46 +0000 (23:32 -0700)]
lima: limit number of draws per job
Otherwise we may hit tile heap size limit if an app issues too many
draws per job.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10121>
Vasily Khoruzhick [Mon, 12 Apr 2021 15:10:29 +0000 (08:10 -0700)]
lima: use passed surface to get mipmap level for reload, not cbuf
lima_pack_reload_plbu_cmd() can be used for either cbuf or zsbuf, so
use passed surface other using cbuf unconditionally.
Fixes:
b8c31ac06d35 ("lima: fix glCopyTexSubImage2D")
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10121>
Erico Nunes [Sun, 28 Mar 2021 21:42:43 +0000 (23:42 +0200)]
lima: increase epsilon for depthrange near == far
When the application sets depthrange near == far, lima inserts an
'epsilon' difference of decreasing 'near' by 1 unit, to prevent
application bugs.
For some specific values of depthrange this does not seem to be
sufficient, presumably due to precision limitations.
Increase the difference by also incrementing the 'far' distance in
this case, to further avoid bugs.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9933>
Marek Olšák [Mon, 12 Apr 2021 05:54:07 +0000 (01:54 -0400)]
ac/surface: use named "color and "zs" structures in unions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Mon, 12 Apr 2021 05:48:02 +0000 (01:48 -0400)]
ac/surface: unify htile_* and dcc_* fields as meta_* fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Mon, 12 Apr 2021 04:54:37 +0000 (00:54 -0400)]
ac/surface: unify htile_levels and dcc_levels as meta_levels
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Marek Olšák [Fri, 2 Apr 2021 21:08:23 +0000 (17:08 -0400)]
ac/surface: pack radeon_surf better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>