Alyssa Rosenzweig [Tue, 1 Aug 2023 13:07:31 +0000 (09:07 -0400)]
agx: Assert invariant stated in the comment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Tue, 1 Aug 2023 12:33:13 +0000 (08:33 -0400)]
agx: Use agx_replace_src
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Tue, 1 Aug 2023 12:30:33 +0000 (08:30 -0400)]
agx: Stop setting registers after the shader
Leftover from before live range splitting. Should be a no-op.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Tue, 1 Aug 2023 12:15:13 +0000 (08:15 -0400)]
agx: Set phi sources in predecessors
This ensures correctness with live range splits. Now agx_set_sources is only for
non-phis where it makes sense.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Tue, 1 Aug 2023 11:26:51 +0000 (07:26 -0400)]
agx: Fix accounting for phis
All affected shaders are in pubg. Presumably, with the new demand calculation,
RA is hitting a higher target thread count at the expense of a little more live
range splitting.
total instructions in shared programs: 1773295 -> 1773310 (<.01%)
instructions in affected programs: 6058 -> 6073 (0.25%)
helped: 0
HURT: 15
Instructions are HURT.
total bytes in shared programs:
11695360 ->
11695450 (<.01%)
bytes in affected programs: 40496 -> 40586 (0.22%)
helped: 0
HURT: 15
Bytes are HURT.
total halfregs in shared programs: 530844 -> 530724 (-0.02%)
halfregs in affected programs: 1785 -> 1665 (-6.72%)
helped: 15
HURT: 0
Halfregs are helped.
total threads in shared programs:
18909440 ->
18910400 (<.01%)
threads in affected programs: 12480 -> 13440 (7.69%)
helped: 15
HURT: 0
Threads are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Tue, 1 Aug 2023 11:26:03 +0000 (07:26 -0400)]
agx: Allow 64-bit memory regs
The mask is based on the format, which can be at most 32-bits per channel. So if
we have 64-bit loads/stores we're still using a 32-bit format with double the
bits set in the mask. This will fix validation fails with spilling.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Mon, 31 Jul 2023 21:42:58 +0000 (17:42 -0400)]
agx: Maintain ctx->max_reg while assigning regs
We can't calculate after since ssa_to_reg[] gets overwritten during live range
splits. Theoretical issue only, but let's fix it while squashing live range
splitting bugs.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sun, 30 Jul 2023 20:08:35 +0000 (16:08 -0400)]
agx: Fix AGX_MESA_DEBUG=demand
No wonder it seemed like it wasn't doing anything!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Mon, 31 Jul 2023 20:40:48 +0000 (16:40 -0400)]
agx: Optimize logical_end removal
We know logical_end instructions are only at the end of the block (validated),
so by changing how we iterate the pass goes from O(instructions) to O(blocks)
which is strictly better.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Mon, 31 Jul 2023 21:19:56 +0000 (17:19 -0400)]
agx: Optimize swaps of 2x16 channels
We can use extr to swap the low and high halves of a 32-bit register in one
instruction.
No shader-db changes, but it reduces xor's on a deqp I'm looking at. Yes, I'm
procrastinating on debugging deqps, how'd you guess?
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Mon, 31 Jul 2023 02:44:28 +0000 (22:44 -0400)]
agx: Use compressed fadd/fmul encodings
See applegpu commit b9b3582 ("FBinaryInstructions have compressed encodings")
total bytes in shared programs:
11717310 ->
11716524 (<.01%)
bytes in affected programs: 317504 -> 316718 (-0.25%)
helped: 196
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sun, 30 Jul 2023 01:46:52 +0000 (21:46 -0400)]
agx: Require an immediate for `nest`
There's no good reason to allow non-immediate nesting values, and this lets us
use the (smaller) mov_imm instruction without special casing. This matches what
Metal produces, so it seems like a good preference.
total bytes in shared programs:
11720338 ->
11717310 (-0.03%)
bytes in affected programs: 2341580 -> 2338552 (-0.13%)
helped: 1385
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sun, 30 Jul 2023 01:54:58 +0000 (21:54 -0400)]
agx: Fix length bit confusion
Man, this expression was wrong. First of all, raw is 64-bit so our mask needs to
be too. Second, length is in bytes -- not bits -- so we need to multiply by 8 to
get something sensible. In effect, the old wrong expression would always use the
long encoding for ALU instructions... whoops. This particular bug probably goes
back to the very first version of agx_pack...
Massive improvement in code density. Noticed while comparing assembly with the
blob. It's my Saturday, I can pointless optimize if I want to.
total bytes in shared programs:
12175112 ->
11720338 (-3.74%)
bytes in affected programs:
11963800 ->
11509026 (-3.80%)
helped: 16624
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sun, 30 Jul 2023 01:36:07 +0000 (21:36 -0400)]
agx: Optimize out pointless else instructions
Now that they're in the right blocks, this is easy. Includes an informal proof
and the implementation itself is built around a finite state machine, which
together meant this code worked on its first try :~)
And hey, it's a pointless little instruction saving optimization I've wanted to
do for a while~
Major note is that this HAS to be done after register allocation, since it
doesn't update the control flow graph and would introduce critical edges
if it tried to actually deleted the else block. The intuitive reason for this is
simple: sometimes RA needs to insert instructions into the else block, even if
it was empty in the original NIR, so we always need an else block even if we can
delete it with this pass after RA.
total instructions in shared programs: 1778390 -> 1776725 (-0.09%)
instructions in affected programs: 268459 -> 266794 (-0.62%)
helped: 1013
HURT: 0
Instructions are helped.
total bytes in shared programs:
12185102 ->
12175112 (-0.08%)
bytes in affected programs: 1927524 -> 1917534 (-0.52%)
helped: 1013
HURT: 0
Bytes are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sun, 30 Jul 2023 00:58:53 +0000 (20:58 -0400)]
agx: Use unconditional else instruction
Rather than duplicating the condition. This matches the blob, so is presumably
the most energy-efficient way of expressing the logic.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sun, 30 Jul 2023 00:08:43 +0000 (20:08 -0400)]
agx: Put else instructions in the right block
According to Dougall's pseudocode, else_icmp operates as:
if r0l == 0:
r0l = n
elif r0l == 1:
if cc.compare(A[thread], B[thread]):
r0l = 0
else:
r0l = 1
exec_mask[thread] = (r0l == 0)
Notice that the comparison only happens when r0l == 1, that is, for threads that
are about to enter the else block. Threads that just executed the if body are
still active (r0l = 0) and skip the comparison. As such, the sources of
else_icmp are only read in the else block, and hence the whole instruction
should be placed in the else block for correctness with respect to live range
splitting.
shader-db is a wash, but shows some improvements due to correctly modelling the
liveness of the condition variable.
total instructions in shared programs: 1778376 -> 1778390 (<.01%)
instructions in affected programs: 14753 -> 14767 (0.09%)
helped: 35
HURT: 39
Inconclusive result (value mean confidence interval includes 0).
total bytes in shared programs:
12185018 ->
12185102 (<.01%)
bytes in affected programs: 101522 -> 101606 (0.08%)
helped: 35
HURT: 39
Inconclusive result (value mean confidence interval includes 0).
total halfregs in shared programs: 531174 -> 531032 (-0.03%)
halfregs in affected programs: 2320 -> 2178 (-6.12%)
helped: 40
HURT: 1
Halfregs are helped.
total threads in shared programs:
18909184 ->
18909440 (<.01%)
threads in affected programs: 1792 -> 2048 (14.29%)
helped: 2
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Fri, 4 Aug 2023 15:25:00 +0000 (11:25 -0400)]
agx: Do not move bindless handles
NIR->AGX translation relies on bindless handles being vec2 instructions with a
constant first index. Moving the entire vec2 into the preamble would mess this
up, so tell nir_opt_preamble to never do this. It's still allowed to move the
offset calculation into the preamble, if it thinks that's beneficial.
Fixes dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Thu, 3 Aug 2023 17:28:27 +0000 (13:28 -0400)]
agx: Fix shader info with sample mask writes
Otherwise the discard_agx isn't lowered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Wed, 9 Aug 2023 11:13:39 +0000 (11:13 +0000)]
asahi: Enable explicit coherency for G14D (multi-die)
It turns out we do need this explicit coherency dance for G14,
but only on G14D.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Janne Grunau [Sun, 30 Jul 2023 16:26:45 +0000 (18:26 +0200)]
asahi,agx: Upload constant buffers immediately
The lifetime of the constant buffer's user_buffer is not guaranteed
to last until agx_upload_uniforms.
Fixes the same ASAN issue mesa/mesa!21685 is trying to address.
Fixes:
080b05e29e1 ("asahi: Add Gallium driver")
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Thu, 27 Jul 2023 18:06:00 +0000 (14:06 -0400)]
agx: Fix atomics with no destination
We need to:
* properly null out the dest in DCE.
* not assert out when packing with null dest
Fixes potential reg pressure blow up with atomics that don't use their
destinations, though I don't see shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Thu, 27 Jul 2023 18:05:54 +0000 (14:05 -0400)]
agx/dce: Use the helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Sat, 29 Jul 2023 01:24:20 +0000 (21:24 -0400)]
agx: Don't lower load_local_invocation_index
We have an SR for it, which can save a bit of math. This came up while working
on the spiller.
total instructions in shared programs: 1778396 -> 1778376 (<.01%)
instructions in affected programs: 3036 -> 3016 (-0.66%)
helped: 10
HURT: 3
Instructions are helped.
total bytes in shared programs:
12185182 ->
12185018 (<.01%)
bytes in affected programs: 38640 -> 38476 (-0.42%)
helped: 18
HURT: 2
Bytes are helped.
total halfregs in shared programs: 531218 -> 531174 (<.01%)
halfregs in affected programs: 471 -> 427 (-9.34%)
helped: 6
HURT: 0
Halfregs are helped.
total threads in shared programs:
18909056 ->
18909184 (<.01%)
threads in affected programs: 1280 -> 1408 (10.00%)
helped: 2
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Janne Grunau [Sat, 29 Jul 2023 17:12:09 +0000 (19:12 +0200)]
asahi,agx: Fix stack buffer overflow in agx_link_varyings_vs_fs
Discovered while running dEQP-EGL under address sanitizer.
Fixes:
f3877f56ba7 ("asahi,agx: Rewrite varying linking")
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 29 Jul 2023 11:05:35 +0000 (20:05 +0900)]
asahi: Force linear for SHARED buffers with no/implicit modifier
Consumers might not pass through the modifier information in this case.
Fixes XWayland/mutter using dma-buf v4 feedback (though the fact they
try to use implicit modifiers is likely a bug on their end, and will
decrease performance).
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Tue, 25 Jul 2023 13:50:48 +0000 (09:50 -0400)]
asahi,agx: Respect no16 even for I/O
Don't call lower_mediump_io for no16. This is helpful for debugging and soon
driconf-shaming apps with broken precision qualifiers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 22 Jul 2023 09:37:40 +0000 (18:37 +0900)]
asahi: Impose limits on resource shadowing
Apps can have pathological use cases where huge resources are shadowed
repeatedly. An app that alternately writes to a resource and then uses
it to draw can create an unbounded amount of shadow BOs.
To fix this, introduce both a maximum resource size for shadowing, and a
maximum cumulative size that resource may be shadowed before we start
flushing readers. The flush path then clears the counter, as does the
happy path where there are no readers left after flushing writers.
Fixes massive memory bloating in Firefox and probably others.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 22 Jul 2023 09:36:54 +0000 (18:36 +0900)]
asahi: Print info about shadowed resources
If resource and perf debugging are both enabled, this prints resource
info for shadowed resources.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 22 Jul 2023 09:35:42 +0000 (18:35 +0900)]
asahi: Always use resource size, not BO size
BOs can be oversized, as they can come from the BO cache. Make sure to
always use the resource layout size, not the BO size, when we need this
for some reason.
This fixes BO shadowing creating overlarge BOs, and also the attachment
size for submissions (probably doesn't matter, but it's more correct now).
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 22 Jul 2023 09:34:11 +0000 (18:34 +0900)]
asahi: Fix race in BO stats accounting
These counters are accessed without locking, so they need to be atomic.
Should be cosmetic only.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 22 Jul 2023 09:33:09 +0000 (18:33 +0900)]
asahi: Do not overallocate BOs by more than 2x
This is not likely to be useful, and might take over a correctly-sized
BO that is going to be reused later.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Asahi Lina [Sat, 22 Jul 2023 09:31:45 +0000 (18:31 +0900)]
asahi: Add a noshadow debug flag
This lets us trivially test whether resource shadowing helps or hurts
any given workload.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Thu, 6 Jul 2023 20:26:37 +0000 (16:26 -0400)]
agx: Handle 8-bit vecs
These should "just" work, promoting the 8-bit channels to 16-bit registers
internally, allowing us to use our 8-bit stores with 8-bit data vectors packed
in 16-bit registers. All other non-conversion ALU gets lowered by the previous
patch, this is just needed for simple things like nir_op_vec of lowered math
passed to a vectorized store.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Thu, 6 Jul 2023 20:23:12 +0000 (16:23 -0400)]
agx: Lower 8-bit ALU
No hardware support for it.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Thu, 6 Jul 2023 12:26:09 +0000 (08:26 -0400)]
asahi: Move a bunch of helpers to common
These have no real Vulkan or Gallium dependence and are (as such) useful for
both VK and GL without any real change in level of abstraction. Do the code
motion.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
Alyssa Rosenzweig [Fri, 11 Aug 2023 14:31:40 +0000 (10:31 -0400)]
asahi: Stub num_dies
We'll use it in the upstreamable driver portion soon.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
George Ouzounoudis [Wed, 9 Aug 2023 21:03:24 +0000 (00:03 +0300)]
nvk: Support dynamic state for enabling sample locations
When switching dynamically we should also push the corresponding sample
locations, the default when disabled or the custom ones when enabled.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24592>
George Ouzounoudis [Wed, 9 Aug 2023 19:05:14 +0000 (22:05 +0300)]
nvk: Fix support for VK_EXT_sample_locations
Fixes some crashes on sample locations pipeline tests.
The implementation was already there but the device properties were
missing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24592>
Italo Nicola [Mon, 10 Jul 2023 23:09:44 +0000 (23:09 +0000)]
gallium/st: lower NV21 to R8_B8G8 instead of G8_B8R8
When NV21 lowering with hardware sampling and shader CSC was added, the
incorrect PIPE_FORMAT_G8_B8R8_UNORM was used. That format is supposed to
represent vulkan NV12 instead.
This commit introduces PIPE_FORMAT_R8_B8G8_UNORM, which correctly describes the
gallium mapping for YUV CSC, with R as Y, instead of G as Y.
Fixes:
26e3be513dc ("gallium/st: add support for PIPE_FORMAT_NV21 and PIPE_FORMAT_G8_B8R8_420")
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24266>
Italo Nicola [Thu, 20 Jul 2023 17:20:58 +0000 (17:20 +0000)]
pan/bi: add support for I420 and YV12 sampling
These formats can be directly sampled, and they have a lower stride
alignment requirement.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24266>
Italo Nicola [Fri, 21 Jul 2023 00:31:48 +0000 (00:31 +0000)]
gallium/st: add non-CSC lowering of YV12 as PIPE_FORMAT_R8_B8_G8_420
YV12 is the same as DRM_FORMAT_YVU420.
We lower it to PIPE_FORMAT_R8_B8_G8_420, which is equivalent to
PIPE_FORMAT_R8_G8_B8_420 with U/V planes swapped.
This is used for hardware that can sample from YUV but need CSC in shader.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24266>
Italo Nicola [Fri, 21 Jul 2023 00:27:48 +0000 (00:27 +0000)]
gallium/st: add non-CSC lowering of I420 as PIPE_FORMAT_R8_G8_B8_420
This new format is similar to PIPE_FORMAT_G8_B8_R8_420, but with R as Y, G as U
and B as V. The need for two diferent formats here is because gallium maps the
YUV channels differently from vulkan.
Some hardware, e.g. Mali GPUs, can sample from I420 but need CSC in shader,
this patch implements that.
Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24266>
David Rosca [Thu, 3 Aug 2023 14:05:54 +0000 (16:05 +0200)]
radeonsi/vcn: Update rate control when framerate changes with HEVC
Similar to H264/AV1, check for framerate changes and update
rate control also with HEVC.
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24475>
Georg Lehmann [Thu, 10 Aug 2023 18:55:04 +0000 (20:55 +0200)]
aco: always use rtne for fquantize2f16
The SPIR-V spec says:
If Value is positive with a magnitude too large to represent as a
16-bit floating-point value, the result is positive infinity.
If Value is negative with a magnitude too large to represent as a
16-bit floating-point value, the result is negative infinity.
This is only the case for rtne v_cvt_f16_f32
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24617>
Alyssa Rosenzweig [Fri, 4 Aug 2023 13:40:38 +0000 (09:40 -0400)]
agx: Lower flat shading in NIR
We get this as part of the lowering we added for interpolateAtOffset.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Alyssa Rosenzweig [Fri, 4 Aug 2023 13:39:55 +0000 (09:39 -0400)]
agx: Add interpolateAtOffset lowering pass
Add a lowering pass that lowers interpolation to math on the coefficient
registers. This handles interpolateAtOffset, as well as flat shading as an easy
special case.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Alyssa Rosenzweig [Fri, 4 Aug 2023 15:38:31 +0000 (11:38 -0400)]
agx: Forcibly vectorize pointcoord coeffs
This avoids regressions from scalarizing pointcoord loads.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Alyssa Rosenzweig [Fri, 4 Aug 2023 13:20:18 +0000 (09:20 -0400)]
agx: Set lower_fisnormal
We're going to generate this in our interpolation lower.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Alyssa Rosenzweig [Fri, 4 Aug 2023 13:41:32 +0000 (09:41 -0400)]
agx: Allow more varying slots
Don't overflow.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Alyssa Rosenzweig [Thu, 3 Aug 2023 18:04:24 +0000 (14:04 -0400)]
agx: Implement nir_intrinsic_load_coefficients_agx
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Alyssa Rosenzweig [Thu, 3 Aug 2023 17:33:54 +0000 (13:33 -0400)]
nir: Add load_coefficients_agx intrinsic
For lowering interpolation.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24498>
Mike Blumenkrantz [Fri, 21 Jul 2023 16:53:49 +0000 (12:53 -0400)]
nir: add a filter cb to lower_io_to_scalar
this is useful for drivers that want to do selective scalarization
of io
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24565>
Mike Blumenkrantz [Fri, 4 Aug 2023 18:59:14 +0000 (14:59 -0400)]
nir/lower_io: add a new doubles-only 64bit lowering option
this allows lowering only 64bit float operations for drivers that
support 64bit integers
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24565>
Vitaliy Triang3l Kuzmin [Mon, 7 Aug 2023 19:41:46 +0000 (22:41 +0300)]
r600/asm: Make sure MOVA and SET_CF_IDX are in the same clause
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24545>
Vitaliy Triang3l Kuzmin [Mon, 7 Aug 2023 19:34:38 +0000 (22:34 +0300)]
r600/asm: Fix AR force_add_cf setting if a clause is not open
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24545>
Samuel Pitoiset [Mon, 7 Aug 2023 12:32:00 +0000 (14:32 +0200)]
radv: use the number of VS outputs for computing the tessellation info
When TCS isn't linked with VS, the vertex stride should be computed
from vertex outputs. This is only for shader object and shouldn't
change anything right now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24540>
Samuel Pitoiset [Mon, 7 Aug 2023 12:31:34 +0000 (14:31 +0200)]
radv: add support for loading the LSHS vertex stride from a SGPR
With shader object, if VS and TCS aren't linked together, the LSHS
vertex stride should be computed from the vertex outputs. Otherwise,
if an output is unused, the stride is wrong in TCS.
This is currently for GFX8 only because for merged shaders this won't
be needed but shader object on GFX9+ isn't yet a thing.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24540>
Tapani Pälli [Tue, 5 Apr 2022 06:57:46 +0000 (09:57 +0300)]
iris: implement required PSS sync for Wa_18019816803
According to WA description, we need to track DS write state
and emit a PSS_STALL_SYNC whenever that state changes.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
Tapani Pälli [Mon, 31 Jul 2023 10:44:05 +0000 (13:44 +0300)]
anv: implement required PSS sync for Wa_18019816803
According to WA description, we need to track DS write state
and emit a PSS_STALL_SYNC whenever that state changes.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
Tapani Pälli [Thu, 8 Sep 2022 11:28:29 +0000 (14:28 +0300)]
intel/blorp: add a new flag to communicate PSS sync need
This is required for Wa_18019816803 when blorp emit DS state.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
Yogesh Mohan Marimuthu [Wed, 12 Apr 2023 05:43:18 +0000 (11:13 +0530)]
gallium: remove start_slot parameter from pipe_context::set_vertex_buffers
This patch removes start_slot from set_vertex_buffers() as suggested in
https://gitlab.freedesktop.org/mesa/mesa/-/issues/8142
compilation testing:
all gallium drivers, nine frontend compilation has been tested.
d3d10umd compilation has not been tested
driver, frontend testing:
only llvmpipe and radeonsi driver was tested running game
only the nine frontend changes are complex. All other changes are easy.
nine front end was using start slot and also using multi context.
nine frontend code changes:
In update_vertex_elements() and update_vertex_buffers(), the vertex
buffers or streams are ordered removing the holes. In update_vertex_elements()
the vertex_buffer_index is updated for pipe driver to match the ordered list.
v2: remove start_slot usage code from Marek (Marek Olšák)
v3: nine stream number holes mask code from Axel (Axel Davy)
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> (except nine, which is Ab)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22436>
Dave Airlie [Fri, 11 Aug 2023 03:50:35 +0000 (13:50 +1000)]
nvk: NOUVEAU_WS_BO_LOCAL is a trap.
This flag isn't a flag, don't be & at it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24625>
Faith Ekstrand [Wed, 9 Aug 2023 21:59:00 +0000 (16:59 -0500)]
nv50/ir: Rework conversions for texture array indices
Currently, negative array texture indices get saturated to 0 which,
while technically in-bounds, isn't what we want for Vulkan with image
robustness or robustness2. Vulkan requires that a negative index on a
texelFetch() count as out-of-bounds but a negative index on any other
texture operation gets clamped to 0. (See the spec section entitled
"(u,v,w,a) to (i,j,k,l,n) Transformation And Array Layer Selection").
Instead of using CVT for TXF, we now take U32 MAX with 0xffff. Because
it's unsigned, this ensures that negative array indices clamp to 0xffff
and will be considered out-of-bounds by the hardware (there are a
maximum of 2048 array indices in an image descriptor). For everything
other than TXF, we keep using an F32->U16 conversion but add a saturate.
This ensures that negative array indices clamp to 0 as per the Vulkan
spec. Very large indices will clamp to 0xffff which the hardware will
clamp to the maximum array index.
This fixes 324 tests in the dEQP-VK.robustness.* group, all those for 1D
and 2D array textures
Acked-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24593>
Mike Blumenkrantz [Thu, 10 Aug 2023 15:25:15 +0000 (11:25 -0400)]
nir: minor fixes for io_to_scalar
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24613>
Mike Blumenkrantz [Thu, 10 Aug 2023 11:46:35 +0000 (07:46 -0400)]
zink: add a special separate shader i/o mode for legacy variables
ARB shaders have no rules restricting i/o interfaces since it's assumed
that they'll match by name. given that mesa marks these all as separate
shaders, a separate path is needed to ensure these variables correctly
match up their i/o even when it's mismatched
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24608>
Mike Blumenkrantz [Thu, 10 Aug 2023 11:46:08 +0000 (07:46 -0400)]
zink: pre-convert mode in fixup_io_locations
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24608>
Faith Ekstrand [Thu, 10 Aug 2023 20:43:55 +0000 (15:43 -0500)]
nvk: Use common physical device properties
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24575>
Konstantin Seurer [Tue, 8 Aug 2023 15:00:08 +0000 (17:00 +0200)]
radv: Use common physical device properties
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24575>
Konstantin Seurer [Mon, 7 Aug 2023 17:04:15 +0000 (19:04 +0200)]
vulkan: Add a generated vk_properties struct
Generates a physical device properties table to avoid dealing with pNext
chains in the driver. Based on vk_features.
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24575>
Eric Engestrom [Thu, 10 Aug 2023 20:44:05 +0000 (21:44 +0100)]
ci/a530: document piglit flake
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
47086976
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24622>
Derek Foreman [Wed, 9 Aug 2023 19:17:27 +0000 (14:17 -0500)]
vulkan/wsi: Allow binding presentation_timing when software rendering
The presentation timing extension is used for doing WaitForPresent
properly, but we accidentally bind it after an early return intended to
stop us from binding dmabuf when software rendering.
Remove the early return.
cc: mesa-stable
Signed-off-by: Derek Foreman <derek.foreman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24588>
Eric Engestrom [Thu, 10 Aug 2023 09:48:49 +0000 (10:48 +0100)]
panfrost: upcast uint8/uint16 before shifting them beyond their range
../src/panfrost/compiler/compiler.h:89:14: runtime error: left shift of 51966 by 16 places cannot be represented in type 'int'
#0 0x55c72fd7dda4 in bi_apply_swizzle ../src/panfrost/compiler/compiler.h:89
#1 0x55c72fd808d6 in bi_source_value ../src/panfrost/compiler/bi_opt_constant_fold.c:35
#2 0x55c72fd80a83 in bi_fold_constant ../src/panfrost/compiler/bi_opt_constant_fold.c:52
#3 0x55c72fb2080c in constant_fold_pred ../src/panfrost/compiler/test/test-constant-fold.cpp:48
#4 0x55c72fb21a65 in ConstantFold_Swizzles_Test::TestBody() ../src/panfrost/compiler/test/test-constant-fold.cpp:103
#5 0x55c73070cc97 in void testing::internal::HandleSehExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2621
#6 0x55c7306f0df7 in void testing::internal::HandleExceptionsInMethodIfSupported<testing::Test, void>(testing::Test*, void (testing::Test::*)(), char const*) ../src/gtest/src/gtest.cc:2657
#7 0x55c730694add in testing::Test::Run() ../src/gtest/src/gtest.cc:2696
#8 0x55c73069798d in testing::TestInfo::Run() ../src/gtest/src/gtest.cc:2845
#9 0x55c73069b684 in testing::TestSuite::Run() ../src/gtest/src/gtest.cc:3004
#10 0x55c7306ccfcb in testing::internal::UnitTestImpl::RunAllTests() ../src/gtest/src/gtest.cc:5890
#11 0x55c73071053c in bool testing::internal::HandleSehExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2621
#12 0x55c7306f4ed3 in bool testing::internal::HandleExceptionsInMethodIfSupported<testing::internal::UnitTestImpl, bool>(testing::internal::UnitTestImpl*, bool (testing::internal::UnitTestImpl::*)(), char const*) ../src/gtest/src/gtest.cc:2657
#13 0x55c7306c23fa in testing::UnitTest::Run() ../src/gtest/src/gtest.cc:5455
#14 0x55c730748faf in RUN_ALL_TESTS() ../src/gtest/include/gtest/gtest.h:2314
#15 0x55c730748ffa in main ../src/gtest/src/gtest_main.cc:63
#16 0x7f8554bcc1c9 in __libc_start_call_main ../sysdeps/nptl/libc_start_call_main.h:58
#17 0x7f8554bcc284 in __libc_start_main_impl ../csu/libc-start.c:360
#18 0x55c72fb18be0 in _start (/builds/mesa/mesa/_build/src/panfrost/compiler/bifrost_tests+0xbd0be0)
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24610>
Eric Engestrom [Thu, 10 Aug 2023 15:18:44 +0000 (16:18 +0100)]
amd/ci: drop duplicate test expectations
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24612>
Chia-I Wu [Sun, 6 Aug 2023 22:58:54 +0000 (15:58 -0700)]
winsys/amdgpu: fix a race between import and destroy
amdgpu_bo_destroy is called when the bo ref count reaches 0. But if the
bo is on bo_export_table, amdgpu_bo_from_handle can race with
amdgpu_bo_destroy and increments the bo ref count. When that happens,
amdgpu_bo_destroy should bail.
v2:
- reorder amdgpu_bo_free and amdgpu_bo_unmap
- fix an assert
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24526>
Gert Wollny [Thu, 10 Aug 2023 15:05:58 +0000 (17:05 +0200)]
r600/sfn: work around injecting extra CF's to handle hardware bugs
The clause local registers can't be used if a new CF is started, but
the assembler still may introduce a CFs to work around some hardware bug,
so make sure RA doesn't assume that the predicate ALU op is in the same ALU
CF like the ALU ops before.
This is a hotfix, the scheduler should handle this better.
Fixes:
cfbd1fd41300740154f89b4382e4790e61c1bf0b
r600/sfn: Use clause local registers in RA
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24611>
Friedrich Vock [Sat, 8 Jul 2023 10:32:07 +0000 (12:32 +0200)]
radv: Handle VK_SUBOPTIMAL_KHR in trace layers
vkQueuePresentKHR might return VK_SUBOPTIMAL_KHR which is not VK_SUCCESS
but presentation succeeded anyway. We should capture a trace even if
VK_SUBOPTIMAL_KHR is returned.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24052>
Eric Engestrom [Thu, 10 Aug 2023 08:07:44 +0000 (09:07 +0100)]
ci/zink+radv: set a timeout of 2x the normal runtime
Normal runtime for both zink-radv-vangogh-valve and zink-radv-navi10-valve
is ~10min, so let's double that as our timeout.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24602>
Nanley Chery [Tue, 25 Jul 2023 18:09:48 +0000 (14:09 -0400)]
iris: Inline iris_can_sample_mcs_with_clear
Now that there's only one user, inline the function.
While we're here, update the stale comment about unknown sampling
formats causing us to implement a simplified workaround. We've had
visibility into the formats that blorp_copy will use for some time now.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24446>
Nanley Chery [Fri, 26 May 2023 23:48:45 +0000 (16:48 -0700)]
iris: Drop get_copy_region_aux_settings
With the previous commit, it is no longer used.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24446>
Nanley Chery [Fri, 5 May 2023 21:57:03 +0000 (14:57 -0700)]
iris: Fix iris_copy_region calls involving FCV_CCS_E
iris_copy_region improperly handles destinations that have
ISL_AUX_USAGE_FCV_CCS_E in use. To avoid corruption when copying to a
resource which has this aux usage, this function needs to:
1. Remove existing fast-clear blocks that would be incompatible with
the surface format that will be used by blorp_copy.
This is actually a general rendering requirement that affects more
aux usages than just FCV_CCS_E.
2. Either avoid generating new fast-clear blocks that would be
incompatible with the original surface format, or remove the newly
generated incompatible fast-clear blocks.
This is particular to FCV_CCS_E, which sometimes generates
fast-clear blocks during a rendering operation. The generation is
dependent on the surface format, the clear color, and the pixels
being written.
iris_copy_region does step 1, only allowing fast-clear blocks that
represent the value of zero. These are compatible with every surface
format. This function does not do step 2 however, leading to rendering
corruption in certain cases.
Fix this by generally relying more on the standard resource preparation
functions, which account for this issue. Specifically, by using
iris_resource_prepare_render, steps 1 and 2 are both handled for us.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3732
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24446>
Nanley Chery [Wed, 26 Jul 2023 18:11:34 +0000 (14:11 -0400)]
iris: Fix aux usage tracking in prepare_render
When a resource goes from being accessed with one aux usage to another,
iris_resource_prepare_access will flush the appropriate caches to
prevent rendering/sampling corruption. So, we must be careful to call
the prepare access function with the aux usage that will match the next
memory access of the resource.
iris_resource_prepare_render fails to do this because it sometimes calls
the prepare access function with the resource's aux usage after calling
that same function with the aux usage that will be used in the next
memory access.
Fix this by reversing the order of the prepare access function calls.
Fixes:
046bba0be05 ("iris: Handle clear color compatibility in prepare_render")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24446>
Matt Coster [Thu, 8 Jun 2023 08:28:56 +0000 (09:28 +0100)]
pvr: Add VK_KHR_copy_commands2
We already expose the *2() functions and allow the common vulkan code
to provide the vulkan 1.0 equivalents, so we might as well expose this
extension.
Coverage in dEQP is dEQP-VK.api.copy_and_blit.copy_commands2.*, which
are mostly identical to dEQP-VK.api.copy_and_blit.core.* without
additional extensions.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Tue, 25 Jul 2023 10:43:04 +0000 (11:43 +0100)]
pvr: Print VkStructureType name on pvr_debug_ignored_stype()
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Thu, 8 Jun 2023 08:36:52 +0000 (09:36 +0100)]
pvr: Add VK_KHR_get_surface_capabilities2
Common vulkan wsi code already exposes the *2() functions (as well as
the vulkan 1.0 equivalents), so we might as well expose this extension.
Coverage in dEQP is dEQP-VK.wsi.*.surface.query_capabilities2, which
are all currently unsupported as we do not expose any platform surface
extensions.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Thu, 8 Jun 2023 08:27:29 +0000 (09:27 +0100)]
pvr: Add VK_KHR_get_memory_requirements2
We already expose the *2() functions and allow the common vulkan code
to provide the vulkan 1.0 equivalents, so we might as well expose this
extension.
The runtime also provides common implementations for the *2() functions
based on VK_KHR_maintenance4, but those functions require the
requirements to be evaluated without creating a resource; that would
need significantly more refactoring work to achieve.
Coverage in dEQP is dEQP-VK.memory.requirements.extended.*, which all
pass or are unsupported.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Thu, 8 Jun 2023 08:33:36 +0000 (09:33 +0100)]
pvr: Add VK_KHR_get_display_properties2
Common vulkan wsi code already exposes the *2() functions (as well as
the vulkan 1.0 equivalents), so we might as well expose this extension.
Coverage in dEQP is dEQP-VK.wsi.display.get_display_*2, which all pass
or are unsupported.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Wed, 7 Jun 2023 16:21:23 +0000 (17:21 +0100)]
docs: Fixup imagination/pvr extension support
VK_KHR_timeline_semaphore support was missed by mistake.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Thu, 8 Jun 2023 09:03:36 +0000 (10:03 +0100)]
pvr: Refactor pvr_GetPhysicalDeviceProperties2()
This makes use of the vk_get_physical_device_core_1_*_property_ext()
helpers.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Matt Coster [Thu, 1 Jun 2023 13:12:47 +0000 (14:12 +0100)]
pvr: Clean up extension tables
Switches PVR_USE_WSI_PLATFORM to be an always defined boolean to allow
for cleaner use in the extension tables (borrowed from tu) and extends
the pattern to create PVR_USE_WSI_PLATFORM_* equivalents for each
supported platform.
Also fixes the ordering to match the struct definitions.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24489>
Eric Engestrom [Wed, 9 Aug 2023 17:35:36 +0000 (18:35 +0100)]
ci: build hasvk in debian-vulkan job
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24586>
Eric Engestrom [Wed, 9 Aug 2023 17:35:36 +0000 (18:35 +0100)]
ci: reorder vk drivers alphabetically in debian-vulkan job
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24586>
David Rosca [Wed, 9 Aug 2023 19:19:05 +0000 (21:19 +0200)]
ci/amd: Skip all VAAPI tests that creates too many huge surfaces
These tests creates up to thousand surfaces of 8192x8192 or
10240x10240 sizes which often times out.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9472
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24590>
Matt Coster [Wed, 26 Jul 2023 09:16:56 +0000 (10:16 +0100)]
pvr: Pad rogue_regarray_cache_key union members to avoid UB
GCC zeroes out the unreferenced parts of the union when assigning by
the smaller member, but clang doesn't. Neither is wrong, because the C
standard calls this UB; insert padding to ensure any compiler behaves
predictably.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24477>
Mike Blumenkrantz [Thu, 10 Aug 2023 09:51:41 +0000 (05:51 -0400)]
zink: don't try to replace separate shader prog in noopt mode
this crashes
Fixes:
ca2e2f4bd0c ("zink: apply ZINK_DEBUG=noopt to linked separate shaders")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24606>
Eric Engestrom [Wed, 9 Aug 2023 14:01:18 +0000 (15:01 +0100)]
docs/v3dv: mark direct display extensions as implemented
Fixes:
bf5cfb64868a50b84df8 ("v3dv: Enable (leased) direct display extensions.")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24584>
Gert Wollny [Sat, 5 Aug 2023 08:04:47 +0000 (10:04 +0200)]
r600: retire SB optimizer
The NIR backend is good enough and here is already a long list of
reasons why SB should not be called because it doesn't handle certain
instructions correctly.
v2: - remove more references to SB (Vitaly Kuzmin)
- remove unused sb context (Sam Ravnborg)
v3: - drop used variable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7166
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24509>
Mike Blumenkrantz [Wed, 2 Aug 2023 21:21:41 +0000 (17:21 -0400)]
zink: fix big tcs output io
as in the producer case, big io needs to reserve the appropriate number
of slots
fixes:
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-rd-after-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-float-index-wr-before-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-rd-after-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec2-index-wr-before-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-rd-after-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec3-index-wr-before-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-rd-after-barrier,Fail
spec@arb_tessellation_shader@execution@variable-indexing@tcs-output-array-vec4-index-wr-before-barrier,Fail
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24568>
Mike Blumenkrantz [Tue, 8 Aug 2023 20:57:07 +0000 (16:57 -0400)]
zink: explicitly set non-optimal last_vertex_stage shader key on ctx create
this otherwise results in generated gs not having the flag set, which breaks
various things
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24568>
Mike Blumenkrantz [Tue, 8 Aug 2023 12:51:41 +0000 (08:51 -0400)]
lavapipe: zero-init pipe_sampler_state
makes trace more reliable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24568>
Mike Blumenkrantz [Wed, 26 Jul 2023 19:17:07 +0000 (15:17 -0400)]
zink: reindex ssa defs before dumping debug shaders
this makes things more consistent across patches
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24568>
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