Frank Binns [Thu, 23 Feb 2023 09:58:29 +0000 (09:58 +0000)]
pvr: remove duplicate define
The same define appears a few lines above.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21495>
Frank Binns [Wed, 22 Feb 2023 22:42:14 +0000 (22:42 +0000)]
pvr: stop restricting the compiler to the Sascha Willems triangle demo
Do this by removing the compatibility table and only using hard coded shaders
when present. The hard coded shaders, along with the hard coding framework
itself, can be dropped once the compiler is capable of compiling the hard coded
shaders. In the meantime we don't want to risk regressing things that we know
work because we temporarily can't test them.
This restriction is being dropped now as the new compiler framework has been
merged and we want to make use of it so it can be developed further.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21495>
Giancarlo Devich [Sat, 25 Feb 2023 00:20:21 +0000 (16:20 -0800)]
d3d12: Track up to 16 active context resource states locally in d3d12_bo
After 16 entries, we fall back to the previous logic that used a hash
map to link the resource's state per context.
Preventing hash map churn by cheaply tracking up to 16 context's worth
of states per resource significantly reduces CPU cost in
find_or_create_state_entry
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21528>
Giancarlo Devich [Sat, 25 Feb 2023 00:19:16 +0000 (16:19 -0800)]
d3d12: Assign up to 16 simultaneously active contexts unique IDs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21528>
Giancarlo Devich [Sat, 25 Feb 2023 00:17:43 +0000 (16:17 -0800)]
d3d12: Move d3d12_context_state_table_entry to d3d12_resource_state.h
Also renamed desired_resource_state to d3d12_desired_resource_state,
since it's also in the header now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21528>
Rob Clark [Fri, 24 Feb 2023 22:58:32 +0000 (14:58 -0800)]
tu/kgsl: Propagate tu_physical_device_init() errors
Should fix dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Fri, 17 Feb 2023 19:51:49 +0000 (11:51 -0800)]
tu+meson: Re-work KMD selection
Now that turnip can support multiple kernel-mode drivers in a single
build, re-work the meson option to have a single list of KMDs, rather
than special options to enable kgsl for turnip or virtio for gallium.
It is temporarily a bit awkward as gallium does not yet support kgsl
and turnip does not yet support virtio. But both of those are planned
or in-progress, so long term a single list is the most sensible option.
TODO freedreno/drm support to build with only virtio support.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Fri, 17 Feb 2023 19:10:24 +0000 (11:10 -0800)]
turnip: Refactor device loading
1) Allow the two different entrypoints for drm vs non-drm (kgsl) to
coexist.
2) Split the generic drm related device initialization from the msm
specifics. This will simplify adding support for additional drm
based kernel mode drivers (ie. virtgpu)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Fri, 17 Feb 2023 18:13:41 +0000 (10:13 -0800)]
turnip: Handle kgsl vs drm specifics at runtime
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Fri, 17 Feb 2023 18:07:56 +0000 (10:07 -0800)]
turnip: Move QueueWaitIdle entrypoint to kgsl
Handle in the same way as other kgsl specific entrypoints.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Fri, 17 Feb 2023 17:41:10 +0000 (09:41 -0800)]
turnip: Allow knl backend specific entrypoints
Because kgsl sync primitives are not drm_syncobj, the kgsl kernel
support needs the ability to patch in it's own entrypoints related
to fences, etc. The current entrypoint table magic using weak syms
won't work if we are building both kgsl and drm support into one
binary, so switch to runtime patching in the kgsl specific entry-
points.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Thu, 16 Feb 2023 21:56:14 +0000 (13:56 -0800)]
turnip: Split out vfuncs for kernel interface
To allow support for multiple KMD's to coexist, split out vfuncs. This
doesn't quite *yet* let us have kgsl and msm coexist, because of the
different vk entrypoints needed by the kgsl backend.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Thu, 16 Feb 2023 21:22:47 +0000 (13:22 -0800)]
turnip: drm code-motion
Move a few functions around in prep for next commit. Only code-motion.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Thu, 16 Feb 2023 19:43:20 +0000 (11:43 -0800)]
turnip: Move things to prep for multi-kernel support
The end goal is a single build that supports kgsl (non-drm) as well
as msm and virtgpu (both drm). First lets move around some files to
accomodate that.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
Rob Clark [Thu, 16 Feb 2023 19:24:00 +0000 (11:24 -0800)]
vk/runtime: Allow enumerate and try_create_for_drm to coexist
For drivers that can support both drm and non-drm kernel mode drivers it
is useful to be able to provide both entrypoints.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21394>
David Heidelberg [Sat, 25 Feb 2023 15:38:24 +0000 (16:38 +0100)]
ci/freedreno: add flaking KHR-GL45.buffer_storage.map_persistent_dispatch
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21531>
Erik Faye-Lund [Tue, 21 Feb 2023 14:05:16 +0000 (15:05 +0100)]
docs: update link to intel optimization reference manual
Seems this document has moved since last we updated this link. But
instead of chasing the exact CDN link, let's link to the document on
Intel's website. There's both a download-link there, as well as the
ability to read the document online.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21448>
Erik Faye-Lund [Tue, 21 Feb 2023 14:08:56 +0000 (15:08 +0100)]
ci: correct typo in name of linkcheck job
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21448>
David Heidelberg [Thu, 16 Feb 2023 21:17:02 +0000 (22:17 +0100)]
intel: use c_see2_arg instead of explicit -msse2
This allows us to also inherit `-mfpmath=sse` added in previous commit.
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>
David Heidelberg [Thu, 16 Feb 2023 21:11:50 +0000 (22:11 +0100)]
intel: enable -mfpmath=sse on x86
It's not enabled by default until `-msse2` and -ffast-math is passed.
We pass only the `-msse2`. Let's align it with main `meson.build`.
See: https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html (-mfpmath).
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21371>
Gert Wollny [Fri, 24 Feb 2023 16:27:30 +0000 (17:27 +0100)]
r600/sfn: Fix minimum required registers
Don't count the local registers, just the arrays, because local
registers might be renamed during register allocation.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8100
Fixes:
9fd9f3cd10cf58549f850aeca9103d8cca5a5f81
r600/sfn: Set minimum required registers based on array allocation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21523>
Konstantin Seurer [Wed, 22 Feb 2023 16:48:23 +0000 (17:48 +0100)]
radv/rt: Merge cull_mask and flags
Since cull_mask is only one byte, we can trivially store it in the same
register as the flags. This leaves us with a 2% performance gain in
Quake II RTX:
Totals from 7 (14.00% of 50) affected shaders:
VGPRs: 720 -> 688 (-4.44%)
CodeSize: 213052 -> 212980 (-0.03%); split: -0.05%, +0.02%
MaxWaves: 67 -> 70 (+4.48%)
Instrs: 39429 -> 39394 (-0.09%); split: -0.15%, +0.06%
Latency: 1096258 -> 1096943 (+0.06%); split: -0.05%, +0.11%
InvThroughput: 230661 -> 222963 (-3.34%); split: -3.42%, +0.08%
VClause: 1208 -> 1206 (-0.17%); split: -0.25%, +0.08%
Copies: 5321 -> 5269 (-0.98%); split: -1.22%, +0.24%
Branches: 1903 -> 1902 (-0.05%)
PreVGPRs: 650 -> 645 (-0.77%)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>
Konstantin Seurer [Wed, 22 Feb 2023 16:47:58 +0000 (17:47 +0100)]
nir: Add cull_mask_and_flags_amd intrinsic
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>
Lionel Landwerlin [Fri, 17 Feb 2023 12:31:00 +0000 (14:31 +0200)]
anv: remove assert typed write support when using NULL surface
A number of apps hit this assert in debug mode.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21382>
Ryan Neph [Thu, 23 Feb 2023 17:00:12 +0000 (09:00 -0800)]
ci: uprev virglrenderer
Update virglrenderer to bring in venus protocol fixes described in
https://gitlab.freedesktop.org/olv/venus-protocol/-/issues/4.
Signed-off-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21496>
Philipp Zabel [Thu, 23 Feb 2023 14:54:15 +0000 (15:54 +0100)]
zink: fix build with -Dvulkan-beta=true
Fix a build error with -Dvulkan-beta=true:
../src/gallium/drivers/zink/zink_screen.c: In function ‘zink_internal_create_screen’:
../src/gallium/drivers/zink/zink_screen.c:2764:20: error: ‘struct zink_device_info’ has no member named ‘have_KHR_portability_subset’
2764 | if (screen->info.have_KHR_portability_subset) {
| ^
../src/gallium/drivers/zink/zink_screen.c:2765:60: error: ‘struct zink_device_info’ has no member named ‘portability_subset_feats’
2765 | screen->have_triangle_fans = (VK_TRUE == screen->info.portability_subset_feats.triangleFans);
| ^
Fixes:
e02cdb397e62 ("zink: prefer vulkan_core.h over vulkan.h")
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21491>
Mike Blumenkrantz [Fri, 24 Feb 2023 20:56:05 +0000 (15:56 -0500)]
zink: fix slab allocator sizing
now that the mem type is passed directly to pb, there have to be enough
slabs to allocate all the mem types (not heaps), so create memoryTypeCount
slabs to allow this
fixes #8369
Fixes:
f6d3a5755f6 ("zink: zink_heap isn't 1-to-1 with memoryTypeIndex"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21526>
Patrick Lerda [Fri, 17 Feb 2023 02:01:37 +0000 (03:01 +0100)]
vbo/save: fix possible crash related to fixup_vertex()
Indeed, buffer_in_ram could be reallocated by fixup_vertex()
which triggers this issue.
For instance, with "piglit/gl-1.0-dlist-materials -auto -fbo":
==28392==ERROR: AddressSanitizer: heap-use-after-free on address 0x607000010024 at pc 0x7f3f416fcf18 bp 0x7f3f33d12800 sp 0x7f3f33d127f8
WRITE of size 4 at 0x607000010024 thread T6
#0 0x7f3f416fcf17 in _save_Materialfv ../src/mesa/vbo/vbo_save_api.c:1405
#1 0x7f3f418199de in _mesa_unmarshal_Materialfv src/mapi/glapi/gen/marshal_generated0.c:5006
#2 0x7f3f413c6863 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:65
#3 0x7f3f4124d368 in util_queue_thread_func ../src/util/u_queue.c:309
#4 0x7f3f41391eba in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#5 0x7f3f4c619c6b in start_thread glibc-2.35/nptl/pthread_create.c:442
#6 0x7f3f4c69e1fb in __clone3 (/lib64/libc.so.6+0x10c1fb)
0x607000010024 is located 20 bytes inside of 80-byte region [0x607000010010,0x607000010060)
freed by thread T6 here:
#0 0x7f3f4f093b48 in __interceptor_realloc (/usr/lib64/libasan.so.6+0xb1b48)
#1 0x7f3f416e5b0c in grow_vertex_storage ../src/mesa/vbo/vbo_save_api.c:417
#2 0x7f3f416e69bc in fixup_vertex ../src/mesa/vbo/vbo_save_api.c:1266
#3 0x7f3f416fb13e in _save_Materialfv ../src/mesa/vbo/vbo_save_api.c:1405
#4 0x7f3f418199de in _mesa_unmarshal_Materialfv src/mapi/glapi/gen/marshal_generated0.c:5006
#5 0x7f3f413c6863 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:65
#6 0x7f3f4124d368 in util_queue_thread_func ../src/util/u_queue.c:309
#7 0x7f3f41391eba in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
#8 0x7f3f4c619c6b in start_thread glibc-2.35/nptl/pthread_create.c:442
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21419>
Iván Briano [Thu, 23 Feb 2023 22:41:54 +0000 (14:41 -0800)]
anv: stop tracking color blend state in the pipeline
Now that all color blend bits are dynamic, emit_cb_state() is doing
almost nothing and half of that is wrong.
In the case that color write enable is dynamic, at the time the pipeline
state is emitted, it sees all the color attachments as having write
disabled and stores the WriteDisabled bit for each channel.
When all dynamic state is flushed, we have the right values already but
the values recorded into the command buffer get ORed with the ones
stored in the pipeline, and so WriteDisabled tag along when they
shouldn't.
Since all disabled color attachments are handled already when dynamic
state is flushed, there's no point in doing so at pipeline creation
time too. And since the only other thing done by emit_cb_state() is
writing three hardcoded values, they might as well be taken care of in
the same place as everything else.
Fixes CTS from the future:
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_equation_*dynamic*
dEQP-VK.pipeline.*.extended_dynamic_state.*.color_blend_all_*
Fixes:
fc3fd7c69e8 (anv: dynamic color write mask)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
Iván Briano [Thu, 23 Feb 2023 20:20:56 +0000 (12:20 -0800)]
anv: fix testing for dynamic color blend bits
Fixes:
fc3fd7c69e8 (anv: dynamic color write mask)
Fixes:
9dc6bed9a10 (anv: dynamic state for logic op enable)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
Iván Briano [Thu, 23 Feb 2023 19:52:58 +0000 (11:52 -0800)]
vulkan: track the right value on CmdSetColorWriteMasks
Fixes:
092be5a3290 ("vulkan: Add more dynamic color blend states")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21509>
Marek Olšák [Mon, 20 Feb 2023 05:50:24 +0000 (00:50 -0500)]
nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd
This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication
for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce
context rolls, and also the register will be removed in the future.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 05:00:45 +0000 (00:00 -0500)]
amd/gpu_info: add a workaround for SI_FORCE_FAMILY=gfx1100
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Wed, 25 Jan 2023 00:15:35 +0000 (19:15 -0500)]
amd: implement conformant TRUNC_COORD behavior for gfx11
For testing, the conformant behavior can be enabled by setting
conformant_trunc_coord to true manually and running this to enable
the conformant behavior in hw:
umr -w *.*.regTA_CNTL2 0x40000
The layer index rounding and TRUNC_COORD resetting workarounds can disabled
in the shader compiler.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Tue, 21 Feb 2023 13:04:41 +0000 (08:04 -0500)]
radeonsi/gfx11: change the default of COMPUTE_DISPATCH_INTERLEAVE to 256
This is an internal recommendation.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Tue, 21 Feb 2023 07:16:37 +0000 (02:16 -0500)]
radeonsi: don't set PACKET_TO_ONE_PA for line stippling
A hw guy told me this.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 09:40:59 +0000 (04:40 -0500)]
radeonsi: reorganize si_init_depth_surface for better readability
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 09:40:34 +0000 (04:40 -0500)]
radeonsi: reorganize si_initialize_color_surface for better readability
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 09:39:47 +0000 (04:39 -0500)]
radeonsi: reorganize emit_db_render_state and simplify VRS code
for better readability
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 5 Feb 2023 00:06:14 +0000 (19:06 -0500)]
amd/registers: only define SPI and COMPUTE registers in the 0xB000 range
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 09:33:38 +0000 (04:33 -0500)]
radeonsi: don't clamp z_samples to fix Unreal Tournament 99
Fixes:
a29218b5 - radeonsi/gfx11: always set MSAA_NUM_SAMPLES=0 for DCC_DECOMPRESS
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8261
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Wed, 25 Jan 2023 01:31:19 +0000 (20:31 -0500)]
amd: query the per-SIMD VGPR counts from the kernel, don't hardcode them
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 20 Feb 2023 05:26:15 +0000 (00:26 -0500)]
radeonsi: rename esgs_itemsize -> esgs_vertex_stride
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 20 Feb 2023 05:25:01 +0000 (00:25 -0500)]
radeonsi: correct and clean up obsolete vs_state_bits comments
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 20 Feb 2023 05:22:48 +0000 (00:22 -0500)]
radeonsi: always add 1 to lshs_vertex_stride now that LS_OUT_PATCH_SIZE is gone
LS_OUT_PATCH_SIZE limited the maximum value.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 20 Feb 2023 05:13:35 +0000 (00:13 -0500)]
radeonsi: remove unused VS_STATE_LS_OUT_PATCH_SIZE
This became unused when we switched to nir_lower_hs_inputs_to_mem.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 20 Feb 2023 04:46:46 +0000 (23:46 -0500)]
radeonsi: remove a gfx11 check in si_shader_gs (legacy GS)
Gfx11 doesn't support legacy GS.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 09:38:03 +0000 (04:38 -0500)]
radeonsi: reformat emit_cb_render_state, create_blend_state, create_rs_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 09:05:02 +0000 (04:05 -0500)]
radeonsi: remove returns from si_emit_global_shader_pointers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 19 Feb 2023 08:51:54 +0000 (03:51 -0500)]
amd: replace SI_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIAN
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Fri, 17 Feb 2023 23:44:29 +0000 (18:44 -0500)]
amd/registers: unify VRS combiner definition names between gfx103 and gfx11
use gfx11 names
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 14:58:50 +0000 (09:58 -0500)]
amd,radeonsi: remove unused LLVM functions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 09:51:28 +0000 (04:51 -0500)]
radeonsi: disable Smart Access Memory because CPU access has large overhead
It will be remove completely in the next commit.
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8176
Cc: mesa-stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 09:44:28 +0000 (04:44 -0500)]
radeonsi: replace si_screen::has_out_of_order_rast with the radeon_info field
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 07:33:32 +0000 (02:33 -0500)]
radeonsi/gfx11: ignore alpha_is_on_msb because the hw ignores it
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 05:36:23 +0000 (00:36 -0500)]
radeonsi: set PA_SU_VTX_CNTL consecutively with PA_CL_GB_VERT_CLIP_ADJ
because they are all next to each other.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 05:09:00 +0000 (00:09 -0500)]
radeonsi: use SPI_SHADER_USER_DATA_HS_0 definition instead of LS_0
The value is the same, but LS_0 is for gfx9 only, and HS_0 is for everything
except gfx9.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 03:22:22 +0000 (22:22 -0500)]
radeonsi: remove no-op setting of THDS_PER_SUBGRP
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 03:20:44 +0000 (22:20 -0500)]
radeonsi: change si_shader::ctx_reg to a nameless union for better readability
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 03:09:34 +0000 (22:09 -0500)]
radeonsi: move a few DB_SHADER_CONTROL states into si_shader_ps
They can be set si_shader_ps.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Tue, 24 Jan 2023 08:53:36 +0000 (03:53 -0500)]
radeonsi/gfx11: set CB_COLORi_INFO.MAX_COMP_FRAG on GFX1103_R2
Fixes:
caa09f66ae4 - amd: add chip identification for gfx1100-1103
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Wed, 8 Feb 2023 03:48:41 +0000 (22:48 -0500)]
radeonsi/gfx11: don't set non-existent VGT_STRMOUT_BUFFER_CONFIG
Fixes:
9fecac091f3 - radeonsi/gfx11: scattered register deltas
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sun, 5 Feb 2023 05:13:50 +0000 (00:13 -0500)]
radeonsi/gfx11: fix the CU_EN clear mask for RSRC4_GS
Fixes:
9fecac091f3 - radeonsi/gfx11: scattered register deltas
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Sat, 18 Feb 2023 08:56:57 +0000 (03:56 -0500)]
amd: bump AMD_MAX_SE and change the CU mask type to 16 bits
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Tue, 24 Jan 2023 08:49:42 +0000 (03:49 -0500)]
amd: add missing gfx11 register definitions
Fixes:
caa09f66ae4 - amd: add chip identification for gfx1100-1103
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 6 Feb 2023 22:47:56 +0000 (17:47 -0500)]
amd: fix LOD_BIAS on gfx6-9 and adjust the lod bias CAP
Fixes:
e673bb4ae44 - amd,util: fix how lod bias is converted to fixed-point
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Mon, 6 Feb 2023 05:12:50 +0000 (00:12 -0500)]
radeonsi: fix COMPAT_MODE on gfx8-9
It was set in the wrong dword.
Fixes:
e673bb4ae44 ("amd,util: fix how lod bias is converted to fixed-point")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Marek Olšák [Fri, 24 Feb 2023 10:16:59 +0000 (05:16 -0500)]
Revert "radeonsi/ci: Update stoney test expectations"
This reverts commit
53cc5092885d5d8dd01a66302e2f762f5b00e045.
This MR fixes it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
Faith Ekstrand [Tue, 21 Feb 2023 14:39:30 +0000 (08:39 -0600)]
spirv: Always emit deref_buffer_array_length intrinsics
All the drivers have been converted to setting this option now except
imagination and they don't support SSBOs yet.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 14:37:19 +0000 (08:37 -0600)]
v3dv: Set spirv_options::use_deref_buffer_array_length
It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 13:50:56 +0000 (07:50 -0600)]
lavapipe: Set spirv_options::use_deref_buffer_array_length
It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 13:49:58 +0000 (07:49 -0600)]
turnip: Set spirv_options::use_deref_buffer_array_length
It'll get lowered to get_ssbo_size by nir_lower_explicit_io() so the
driver should never notice this change.
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 13:42:30 +0000 (07:42 -0600)]
panvk: Drop our manual SSBO size handling
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 13:41:34 +0000 (07:41 -0600)]
hasvk: Drop our manual SSBO size handling
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 13:41:01 +0000 (07:41 -0600)]
anv: Drop our manual SSBO size handling
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Faith Ekstrand [Tue, 21 Feb 2023 13:37:28 +0000 (07:37 -0600)]
nir/lower_io: Handle buffer_array_length for more address modes
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
Sil Vilerino [Wed, 22 Feb 2023 13:44:26 +0000 (08:44 -0500)]
frontend/va: Remove duplicate code in format support checking/reporting.
In config.c there are multiple copies of the code checking for VA_FORMAT_RT_*, this can lead
to confusion and is hard to maintain without knowing to change the code in all the places.
This commit extracts out the duplicated code into a function that checks format support
for a given profile and entrypoint, then this function is called from several places that
had the copies of this code in vlVaCreateConfig/vlVaGetConfigAttributes.
Please also note that after this change, all entrypoints/profiles will be checked for all
formats in the pipe_screen: YUV420/YUV420_10/YUV422/RGB32/YUV400/YUV444
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21466>
Sil Vilerino [Wed, 22 Feb 2023 03:40:56 +0000 (22:40 -0500)]
frontend/va: Add format support checks for VA_RT_FORMAT_* in VaCreateConfig/VaGetConfigAttributes
Before this change some formats like YUV420, YUV422 and RGB32 are hardcoded as supported
in VaCreateConfig/VaGetConfigAttributes. This is not always the case, different gallium
drivers and hardware will support different formats. The frontend should delegate the support
check call by using the is_video_format_supported(...) function from pipe_screen.
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Tested-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21466>
Roland Scheidegger [Thu, 23 Feb 2023 22:08:10 +0000 (23:08 +0100)]
lavapipe, nir: Fix wrong array index scaling in nir_collect_src_uniforms
The scaling needs to be ubo * MAX_INLINABLE_UNIFORMS, not
ubo * PIPE_MAX_CONSTANT_BUFFERS, otherwise accesses beyond buffer size
will result for ubo >= 4 (and we'd also access the wrong values later
for other non-zero ubo indices).
Fixes:
a7696a4d98bc ("lavapipe: Fix bad array index scale factor in lvp_inline_uniforms pass")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21506>
Gert Wollny [Fri, 24 Feb 2023 09:25:06 +0000 (10:25 +0100)]
r600/sfn: Fix readport cylce map
This is currently of no consequence, because the bank swizzle
codes are only used to check legal ALU group configuration
and the bank swizzles are not yet allocated to the instruictions
here.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21516>
Gert Wollny [Fri, 24 Feb 2023 09:14:01 +0000 (10:14 +0100)]
r600/sfn: be more conservative with channel use in multi-slot ops
The current approach to check the bank swizzle doesn't allow to
re-evaluate bank-swizzle for instructions that where emitted
earlier, so we might end up with impossile constellations when we
allow three uses of the same channel
Fixes:
edabd5cd8425
r600/sfn: check used channels when evaluating allowed mask
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8350
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21516>
Konstantin Seurer [Fri, 20 Jan 2023 20:52:06 +0000 (21:52 +0100)]
radv: Use indirect header filling for compact builds
Sets the accel struct size fields to the correct values which should
allow for more compaction.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Fri, 20 Jan 2023 20:51:32 +0000 (21:51 +0100)]
radv/bvh: Add a shader for filling the header
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Fri, 20 Jan 2023 18:55:30 +0000 (19:55 +0100)]
radv/bvh: Move the size header field up
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Fri, 20 Jan 2023 18:40:25 +0000 (19:40 +0100)]
radv: Move the geometry infos before the BVH
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Fri, 20 Jan 2023 18:30:20 +0000 (19:30 +0100)]
radv: Use compact encoding
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Fri, 20 Jan 2023 18:29:05 +0000 (19:29 +0100)]
radv/bvh: Implement compact encoding
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Thu, 19 Jan 2023 21:16:59 +0000 (22:16 +0100)]
radv: Add a build config for compact builds
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Thu, 19 Jan 2023 21:10:24 +0000 (22:10 +0100)]
radv/bvh/encoder: Move dst_node initialization into the loop
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Thu, 19 Jan 2023 21:02:22 +0000 (22:02 +0100)]
radv/bvh/encode: Introduce is_root_node
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Thu, 19 Jan 2023 20:56:25 +0000 (21:56 +0100)]
radv/bvh/encode: Move bvh_offset NULL check to the top of the loop
NULL nodes don't have to be encoded and they also don't carry over any
information to their children.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Thu, 19 Jan 2023 20:39:59 +0000 (21:39 +0100)]
radv/bvh: Replace is_final_tree with bvh_offset
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konstantin Seurer [Thu, 19 Jan 2023 19:55:06 +0000 (20:55 +0100)]
radv/bvh/encode: Use the node type for identifying internal nodes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
Konrad Dybcio [Thu, 23 Feb 2023 10:36:58 +0000 (11:36 +0100)]
freedreno: Add A2xx REG_A2XX_RBBM_PM_OVERRIDE2 bitfields
Required for good-looking kernel code
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480>
Konrad Dybcio [Thu, 23 Feb 2023 01:03:36 +0000 (02:03 +0100)]
freedreno: Add A2xx perf counter reg values
Required for good-looking kernel code
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[rob: fixup CI expectations]
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21480>
Karmjit Mahil [Mon, 23 Jan 2023 23:54:06 +0000 (23:54 +0000)]
pvr: Remove component_alignment
We don't support output register subdivision so no need to keep
track of how many bytes have been allocated within the output regs.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>
Karmjit Mahil [Mon, 9 Jan 2023 15:55:20 +0000 (15:55 +0000)]
pvr: Remove unused msaa_mode field
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>
Karmjit Mahil [Mon, 9 Jan 2023 16:04:16 +0000 (16:04 +0000)]
pvr: Setup SPM EOT state
On entering SPM we need to store the tile data for the current
render into the scratch buffer so we need to setup an EOT program
to do so.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>
Karmjit Mahil [Mon, 9 Jan 2023 16:03:53 +0000 (16:03 +0000)]
pvr: Move PBE START_POS into csb enum helpers header
This commit adds 'pvr_pbestate_source_pos()' and moves
`enum pvr_pbe_source_start_pos` into pvr_csb_enum_helpers.h .
The enum will be needed in other files in the commits following.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21386>
Samuel Pitoiset [Tue, 8 Nov 2022 16:43:18 +0000 (17:43 +0100)]
radv: advertise VK_EXT_image_sliced_view_of_3d on GFX10+
Pass dEQP-VK.pipeline.monolithic.sliced_view_of_3d_image.* on NAVI21.
Looks like older generations can't support it.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>
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