zink: Always set a blend state for shader-db

If we're compiling shaders in shader-db, with shader-db's ./run and
ZINK_DEBUG=shaderdb, we won't get much state set on the graphics pipeline, since
shader-db doesn't actually do any rendering. For a driver like RADV, that is
*almost* ok... Since we use dynamic vertex input, we don't need to make up any
state for vertex inputs; since we use dynamic rendering, we don't need to make
up any render attachments. All of that being said, we *do* need to make up a
blend state to ensure that the Vulkan driver doesn't optimize away all of
store_derefs in the fragment shader (and in turn, optimize the entire fragment
shader away, if there are no image/SSBO writes.) So set the obvious blend state,
fixing fragment shaders in shader-db with zink + radv.

I don't know why other people would want to use Zink with shader-db, but for me
it's an easy way to test ACO, at least until radeonsi gains aco support.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22948>

spirv: Use NIR_PASS for spirv2nir --optimize

This allows us to use NIR_DEBUG=print to see each step.
Also use an OPT macro to make code slightly more readable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22764>

spirv: Do more on spirv2nir --optimize

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22764>

intel/mi_builder: fixup tests for newer kernel uAPI

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22966>

anv: Set memory types supported by Xe KMD

Due the lack of APIs to set mmap modes, Xe KMD can't support the same
memory types as i915.
So here adding a i915 and Xe function to set memory types supported
by each KMD.

Iris function iris_xe_bo_flags_to_mmap_mode() has a table with all the
mmaps modes of each type of placement.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22906>

radeonsi: Use vcn version instead of CHIP family for VCNs

Decouple it from CHIP family, based on HW query infomation.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>

amd: Add vcn ip version info

And make it support for kernel w/wo ip_discovery.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>

radeonsi: Remove redundant vcn_decode from info

Use the number of queue instead.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>

dzn: Fix segmentation fault when Direct3D 12 user mode
driver from at least one of GPUs is not available.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22961>

agx: Optimize multiplies

We have an imad instruction and our iadd has a small immediate shift on the
second source. Together, these allow expressing lots of integer multiplies more
efficiently. Add some rules to optimize these now that the backend compiler can
ingest the optimized forms.

Half-register changes are from load_const scheduling changing in some vertex
shaders.

   total instructions in shared programs: 1539092 -> 1537949 (-0.07%)
   instructions in affected programs: 167896 -> 166753 (-0.68%)

   total bytes in shared programs: 10543012 -> 10533866 (-0.09%)
   bytes in affected programs: 1218068 -> 1208922 (-0.75%)

   total halfregs in shared programs: 483180 -> 483448 (0.06%)
   halfregs in affected programs: 1942 -> 2210 (13.80%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

agx: Fix packing of imsub instructions

The negate for imad is on the third source (a * b - c), not the second source.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

agx: Handle imadshl_agx, imsubshl_agx

Same hardware instructions as iadd/isub/imad/imsub, just with the extra input
represented in NIR as required.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

nir: Model AGX-specific multiply-shift-add

Models `(a * b) + (c << d)` in general, as implemented in various forms on AGX.
This will be fused with backend NIR opt algebraic rules, both for the literal
pattern as well as to strength reduce certain multiplications, e.g. replacing
a * 5 with `a + (a << 2)` expressed as imadshl_agx(a, 1, a, 2).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

agx: Use nir_alu_src_as_uint

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

pan/bi: Use nir_alu_src_as_uint

Fixes some theoretical issues with swizzle handling. Unsure if this could cause
actual end-to-end miscompiles.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

nir: Add nir_alu_src_as_uint helper

We have a few ALU instructions that take a constant source. Technically, they
have a swizzle so you can't just nir_src_as_uint them, even though a bunch of
backends do. To help backends do the right thing, add a helper that's just as
easy to use that will chase the swizzle properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>

anv: fixup workaround 16011411144

We're missing it for the memcpy with streamout

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 5cc4075f95 ("anv, iris: Add Wa_16011411144 for DG2")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22930>

egl/loader: move crtc resource infrastructure as common helper

Patch moves (and renames) the infrastructure to fix compilation
failures when dri3 is not enabled in the build.

Fixes: 3170b63314f ("loader: Add infrastructure for tracking active CRTC resources");
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8476
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22897>

aco: also reassign p_extract_vector post ra

Foz-DB Navi21:
Totals from 1223 (0.91% of 134864) affected shaders:
CodeSize: 6923888 -> 6913516 (-0.15%)
Instrs: 1293744 -> 1291151 (-0.20%)
Latency: 16928653 -> 16925035 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 2985304 -> 2984775 (-0.02%); split: -0.02%, +0.00%
VClause: 32260 -> 32319 (+0.18%)
SClause: 54952 -> 54949 (-0.01%)
Copies: 83968 -> 81377 (-3.09%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>

aco: Assert that operands have the same byte offset when reassigning split vectors

This can not happen because the post-RA optimizer doesn't support sub dword
writes at the moment, but everytime I look at this I wonder if there might
be a bug here.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>

vulkan/pipeline_cache: don't log warnings for internal caches

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22850>

Revert "intel/compiler: make uses_pos_offset a tri-state"

This reverts commit 5489033fa8568ecacafe32ceab36f89f2e14f3dc.

The problem I was trying to address is that we were programming the
3DSTATE_PS::PositionXYOffsetSelect bit differently with GPL (CENTROID)
than without (NONE).

I failed to understand that this bit also impacts the thread payload
layout. GPL fragment shaders don't know ahead of time if pos_offset is
going to be used. It'll be choosen at runtime base on push constant
bits. So we need to program this bit different just to have a payload
matching the compiled shader code.

This fixes the freedoom replay with GPL FS shader in SIMD32.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22938>

v3d/ci: annotate failures

Annotate some of the failures with the root cause.

Remove also some tests that are actually skipped.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22953>

amd/drm-shim: add amdgpu drm-shim

This is enough to run offscreen apps such as vulkaninfo or deqp-vk.

v2: remove unnecessary idep_amdgfxregs_h dependency

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21892>

drm-shim: apply file overrides for open

loader_get_pci_driver calls os_read_file on linux to get the pci id, and
os_read_file uses open instead of fopen.

This allows loader_get_pci_driver to work rather than falling back to
loader_get_kernel_driver_name.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22951>

microsoft/compiler: Do basic I/O analysis for dependency tables

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22949>

microsoft/compiler: Allocate space for I/O and viewID dependency tables before instruction processing

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22949>

tu: Re-enable bufferDeviceAddressCaptureReplay

We cannot immidiately free VMA range when BO is freed, we have to
wait until kernel stops considered BO as busy and frees its internal
VMA range. Otherwise userspace and kernel VMA will get desynchronized.

To fix this and re-enable replaying of BDA we place BO's information
into a queue. The queue is drained:
- On BO allocation;
- When we cannot allocate an iova passed from the client.

For more information about this see:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/7106

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

tu: Move queue deletion to last

For zombie vma tracking, we'll need access to the queue at bo deletion
time.  This simplest way to make that work is just move queue deletion
to late in device teardown.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

tu: Move VMA heap to the logical device

Since last commit drm fd is being created on per logical device
granularity, which means each logical device has its own
address space. So VMA heap could be moved to logical device.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

tu: Create drm fd per logical device

The main reason is to simplify BO managment when
bufferDeviceAddressCaptureReplay would be enabled.

Having to track some BO information in physical device and some
info in logical device gets challenging when BOs are shared
between logical devices.

Other benefits:
- Isolation from hangs in other logical devices;
- Each logical device limited only by its own address space size.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>

ci/zink+anv: Skip a couple more long tests pre-merge.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>

ci: Re-enable some piglit tests that should be fast enough post-uprev.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>

Uprev Piglit to 536975d94a40cf76a69fcfa786c2513eccd0c989
https://gitlab.freedesktop.org/mesa/piglit/-/compare/79a084c56b6dd79f7c3a97b57a72963121ebb1e6...536975d94a40cf76a69fcfa786c2513eccd0c989

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>

zink: Don't flag legacy_shadow_mask for RED-only reads in the shader.

It is very common in games to read just the .x channel of a vec4 shadow
result (since GL defaults to either LUMINANCE or RED depth mode depending
on context).  So, we can avoid shader recompiles to handle the other
components, in that case.

Fixes some recompiles in CS:GO.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>

zink: Fix silly void * type in rewrite_tex_dest.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>

zink: Explain some of the current pathway for shadow sampling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>

mesa: Fix precompile of GLSL programs with shadow samplers.

Reduces fp variant recompiles on google's CS:GO trace on zink+anv from 115
to 31.

Fixes: 0843d4cbc354 ("nir: switch to a normal sampler for ARB program with not depth textures")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22928>

mesa: Fix debug logging of fp compile compare func.

When we're doing COMPARE_FUNC_ALWAYS, that's not part of a shader
precompile miss.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22928>

ac: enable SHADOW_GLOBAL_CONFIG for preemptible ib

SHADOW_GLOBAL_CONFIG is mandatory for mid command buffer preemmption.

Fixes: 69014d8c94f (radeonsi: implement CP register shadowing)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22916>

nir/lower_io: Emit less iadd(x, 0)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22890>

freedreno/a5xx+a6xx: Don't allocate LRZ for z32

We don't do LRZ in this case, so no point in allocating the LRZ buffer.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Actually use LRZ for ms

We know the z value after the fallback clear.  But we need to set
rsc->lrz_valid _after_ the fallback clear invalidates it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Move LRZ clears to gmem

If we have multiple LRZ clears, emit them all at once.  This also avoids
redundant LRZ clears if app does multiple clears in sequence.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: New subpass on mid-frame clears

If we get a mid-frame clear, split out a new subpass rather than having
to fall-back to u_blitter clears.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Per-subpass LRZ

Allow the LRZ buffer to be re-allocated if a mid-frame depth clear
starts a new subpass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Introduce batch subpasses

Just the scaffolding for now, nothing actually creates multiple sub-
passes yet.  For now, only planning to use this for a6xx, as other
gens are doing clears on 3d.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Split tile loads and clears

This will give better visibility in perfetto, and prepares for the next
commit where we could have per-subpass clears.

While we are at it, start adopting vulkan terms for tile load/store.  No
need to be pointlessly different.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Switch to batch->cleared

batch->fast_cleared will be per-subpass.  But we can use the cleared
bitmask instead in the few places where we just need to know if there
was a clear in any subpass.  For the conditional-ib it is even
preferable since we know a clear touched the contents of the tile so
we know what the result of the conditional would be.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Simplify per-tile conditional IBs

Handle the logic which decides between conditional or unconditional IB
in one place.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Add ctx->emit_sysmem()

Once we introduce subpass, it won't be just a single IB.  But per
subpass clears + IB.  So interoduce a sysmem counterpart for
emit_tile().

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/a6xx: Move LRZ clear to blitter

This is where it belongs.  And will simplify moving LRZ clears to
fd6_gmem.cc

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

freedreno/batch: Add helper to set fb state

Stop open-coding and add a helper.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>

zink: disable always zs feedback loop on radv

this shouldn't have been enabled

Fixes: 56fb2580642 ("zink: replace mixed_zs with zs feedback loops")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22946>

anv: apply ANV_BO_ALLOC_IMPLICIT_SYNC for external memory

This is necessary to make anv work with clients like VA-API which relies
on implicit fencing only. The bahavior matches iris i915_batch_submit.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22937>

ci: bump bin/ci/ deps to support python 3.11

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22943>

pvr: add GUARD_SIZE_DEFAULT for CDM and VDM control stream links 1 and 2

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22631>

pvr: use PVR_DW_TO_BYTES for stream_link_space calculation

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22631>

aco: Initialize vcmpx field in get_cmp_info.

Fixes: 578d0a19341a5df2be555e19396a20c81d79c7a9
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22885>

aco: Don't allow any VALU instruction to write m0.

Fixes: d5398b62da1913e7224c826da0dbd5fa88436f18
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22885>

vulkan/wsi/wayland: add 16-bit formats

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20234>

broadcom/compiler: increase peephole limit to 24 instructions

This helps by reducing the number of branches with their corresponding
delay slots, at the expense of additional register pressure. It also helps
a lot with SFU stalls, probably because removing control-flow blocks
gives us more QPU scheduling flexibility to hide them.

Shader-db results below correspond to the "closed shaders" set, since the
full set is very dominated by the massive impact this change has on Skia's
shaders (for the better), so this is probably more representative of real
impact:

total instructions in shared programs: 11887255 -> 11854898 (-0.27%)
instructions in affected programs: 538170 -> 505813 (-6.01%)
helped: 1653
HURT: 43
Instructions are helped.

total threads in shared programs: 385924 -> 385872 (-0.01%)
threads in affected programs: 236 -> 184 (-22.03%)
helped: 22
HURT: 48
Inconclusive result (%-change mean confidence interval includes 0).

total uniforms in shared programs: 3552808 -> 3547894 (-0.14%)
uniforms in affected programs: 157486 -> 152572 (-3.12%)
helped: 1673
HURT: 35
Uniforms are helped.

total max-temps in shared programs: 2062403 -> 2064720 (0.11%)
max-temps in affected programs: 18209 -> 20526 (12.72%)
helped: 168
HURT: 369
Max-temps are HURT.

total spills in shared programs: 1937 -> 1994 (2.94%)
spills in affected programs: 79 -> 136 (72.15%)
helped: 0
HURT: 1

total fills in shared programs: 2652 -> 2717 (2.45%)
fills in affected programs: 115 -> 180 (56.52%)
helped: 0
HURT: 1

total sfu-stalls in shared programs: 19349 -> 18010 (-6.92%)
sfu-stalls in affected programs: 2321 -> 982 (-57.69%)
helped: 674
HURT: 74
Sfu-stalls are helped.

total inst-and-stalls in shared programs: 11906604 -> 11872908 (-0.28%)
inst-and-stalls in affected programs: 541339 -> 507643 (-6.22%)
helped: 1656
HURT: 43
Inst-and-stalls are helped.

total nops in shared programs: 245740 -> 238085 (-3.12%)
nops in affected programs: 19282 -> 11627 (-39.70%)
helped: 1335
HURT: 76
Nops are helped.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22922>

radv/ci: stop setting MESA_SPIRV_LOG_LEVEL

Use the default VTN logging level which is warning.

Suggested-by: Emma Anholt <emma@anholt.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6263
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22917>

spirv: ignore SpvDecorationInvariant warning on struct members

Similar to SpvDecorationRestrict, looks like it's also incorrectly
generated by glslang.

This will allow RADV/CI to leave MESA_SPIRV_LOG_LEVEL as default
(ie. only warnings).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22917>

radv: advertise LINEAR filter support for multiplanar/subsampled

It seems like radv supports this but doesn't advertise it.

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22875>

drirc: Set limit_trig_input_range option for Nier games

Resolves ambient occlusion rendering in Replicant
Resolves grass and ocean animations in Automata, and maybe more.

Both of these games have shaders that expect trig values to work across
large ranges with good precision.

Closes #7656

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22894>

v3d: apply proper clamping when setting up RT

Ensure the render target values are in the proper range.

This fixes `spec@!opengl 3.0@render-integer`.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22733>

v3d: upgrade V3D 4.1 to 4.2 version

Some of the new features require at least V3D 4.2. And actually, 4.2 is
the version used by the Raspberry Pi 4 hardware.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22733>

v3d: add per hw-version caller macro

Instead of hardcoding conditionals to know which hardwared-based version
of a function to call, just wrap them in a macro to use

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22733>

radv/rt: store stack_sizes per stage instead of per group

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>

radv/rt: use vk_multialloc for radv_ray_tracing_pipeline

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>

radv/rt: refactor radv_rt_pipeline_compile()

This patch moves the NIR shader creation into radv_rt_pipeline_compile()
and simplifies radv_rt_pipeline_create().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>

radv/rt: unify radv_rt_pipeline_create() and radv_rt_pipeline_library_create()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>

radv/rt: unify radv_ray_tracing_lib_pipeline and radv_ray_tracing_pipeline

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>

radv/rt: change base of radv_ray_tracing_lib_pipeline to radv_compute_pipeline

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>

anv: enable graphics pipeline libraries by default

Since we are disabling mesh, which has issues with gpl, enable gpl by
default now, leaving the renamed environment variable as a way to
disable it for debug purposes.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22910>

anv: put EXT_mesh_shader behind an environment variable

We are seeing frequent hangs in other workloads when something using
mesh shaders runs at the same time, so gate the feature behind an
environment variable until we figure out what's going on.

v2: (Sagar)
 - Give the mesh enabled variable a more descriptive name

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22910>

zink: also cache swapchain semaphores

a semaphore is a semaphore, as they say

Fixes: 7399b2241f8 ("zink: move semaphore caching to zink_reset_batch_state()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22935>

zink: block more flushes during unordered blits

Fixes: 89aa3635932 ("zink: block oom flushes during unordered blits")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>

zink: adjust bindless texel buffer handle before indexing

buffer handle ids are offset by ZINK_MAX_BINDLESS_HANDLES, but the actual
index is zero-based

Fixes: 99ba529feed ("zink: implement descriptor buffer handling of bindless texture")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>

zink: compare desc set to detect bindless vars in separate shaders

the bindless flag here isn't set, so this check did nothing

Fixes: e3b746e3a31 ("zink: use GPL to handle (simple) separate shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>

zink: bind bindless db set when updating separate shader db sets

this otherwise doesn't bind a bindless set and hangs

Fixes: e3b746e3a31 ("zink: use GPL to handle (simple) separate shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>

zink: set debug callback on context

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>

zink: add perf_debug for "interesting" shader compiles

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>

zink: make mesa_logw separate from perf_debug

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>

zink: add ZINK_DEBUG=nobgc

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>

zink: add ZINK_DEBUG=noopt

it's often useful to disable optimized pipeline compiles for debugging

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>

vc4/ci: disable VC4 jobs

Some test is causing a GPU reset, which blocks merge requests.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22927>

dzn/ci: Remove 'exclude' for graphicsfuzz cases

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22926>

dzn: Run nir_opt_remove_phis before nir_lower_returns

Otherwise nir_lower_returns can produce invalid NIR by not updating
a phi in a non-trivial if.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22926>

frontends/va/config: check for QVBR support when creating

Fixes: 30a6363c8f6 ("frontend/va: Support QVBR rate control mode")
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22905>

frontends/va/context: check min supported resolution when creating

Fixes: c987eed9cd7 ("frontends/va: report min width and min height values if available")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8981
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22905>

frontends/va/config: add disable packed headers as valid config

Fixes: 306c6e12a59 ("frontends/va: define va av1 encoding caps")
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22905>

radeonsi: set proper drm_amdgpu_cs_chunk_fence alignment

The 'struct drm_amdgpu_cs_chunk_fence' is processed as
'struct drm_amdgpu_cs_chunk_data' which is a union.
This change ensures the proper alignment for this structure
to be processed as 'struct drm_amdgpu_cs_chunk_data'.

The presence of __u64 as one member of
'struct drm_amdgpu_cs_chunk_data' makes the
whole structure expected to be 64-bit aligned.

This is a minor issue detected by the gcc sanitizer (ubsan), for instance at the libdrm library:
../amdgpu/amdgpu_cs.c:937:26: runtime error: member access within misaligned address 0x63100001484c for type 'struct drm_amdgpu_cs_chunk_data', which requires 8 byte alignment
0x63100001484c: note: pointer points here
  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
                ^

Fixes: ae7e4d7619e0 ("amd: rename ring_type --> amd_ip_type and match the kernel enum values")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22920>

iris: Add function to return mmap mode for aux map

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22240>

iris: Add function to return mmap mode for userptr bos

Similar to what was done to alloc buffer but now for userptr bos.
There is no changes in i915 modes but Xe may different values in
future.

While at it, also setting bo->real.heap to IRIS_HEAP_SYSTEM_MEMORY
as it was already implicit set as IRIS_HEAP_SYSTEM_MEMORY is the
value 0 of the enum.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22240>

iris: Add a function to return allocated bo mmap mode

i915 and Xe kmd can have different mmaps modes, so here extracting
the code to handle it to function.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22240>

lavapipe: honor dst base array layer when resolving color attachments

CC: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22924>

zink/ci: document new flakes on RADV

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22923>

zink/ci: document recent fixes on RADV

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22923>