Alexey Bataev [Mon, 7 Aug 2017 15:25:49 +0000 (15:25 +0000)]
[SLP] General improvements of SLP vectorization process.
Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:
1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the
array. This array is processed only after the vectorization of the
first-after-these instructions key node is finished. Vectorization goes
in reverse order to try to vectorize as much code as possible.
Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon
Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits
Differential Revision: https://reviews.llvm.org/D29826
llvm-svn: 310260
Matt Arsenault [Mon, 7 Aug 2017 14:58:43 +0000 (14:58 +0000)]
Fix typo in comment
llvm-svn: 310259
Matt Arsenault [Mon, 7 Aug 2017 14:58:04 +0000 (14:58 +0000)]
AMDGPU: Cleanup subtarget features
Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.
Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.
llvm-svn: 310258
Alexey Bataev [Mon, 7 Aug 2017 14:51:52 +0000 (14:51 +0000)]
Revert "[SLP] General improvements of SLP vectorization process."
This reverts commit r310255.
llvm-svn: 310257
Nirav Dave [Mon, 7 Aug 2017 14:07:49 +0000 (14:07 +0000)]
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.
Relanding after case to insert explicit truncation as necessary.
Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.
Reviewers: efriedma, RKSimon, spatel
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35566
llvm-svn: 310256
Alexey Bataev [Mon, 7 Aug 2017 14:03:17 +0000 (14:03 +0000)]
[SLP] General improvements of SLP vectorization process.
Summary:
Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:
1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the array. This array is processed only after the vectorization of the first-after-these instructions key node is finished. Vectorization goes in reverse order to try to vectorize as much code as possible.
Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon
Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits
Differential Revision: https://reviews.llvm.org/D29826
llvm-svn: 310255
Nirav Dave [Mon, 7 Aug 2017 13:55:27 +0000 (13:55 +0000)]
[TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true
Relanding after fixing UB issue with DefaultOffsets.
Consider the following instruction: "inst.eq $dst, $src" where ".eq"
is an optional flag operand. The $src and $dst operands are
registers. If we parse the instruction "inst r0, r1", the flag is not
present and it will be marked in the "OptionalOperandsMask" variable.
After the matching is complete we call the "convertToMCInst" method.
The current implementation works only if the optional operands are at
the end of the array. The "Operands" array looks like [token:"inst",
reg:r0, reg:r1]. The first operand that must be added to the MCInst
is the destination, the r0 register. The "OpIdx" (in the Operands
array) for this register is 2. However, since the flag is not present
in the Operands, the actual index for r0 should be 1. The flag is not
present since we rely on the default value.
This patch removes the "NumDefaults" variable and replaces it with an
array (DefaultsOffset). This array contains an index for each operand
(excluding the mnemonic). At each index, the array contains the
number of optional operands that should be subtracted. For the
previous example, this array looks like this: [0, 1, 1]. When we need
to access the r0 register, we compute its index as 2 -
DefaultsOffset[1] = 1.
Patch by Alexandru Guduleasa!
Reviewers: SamWot, nhaustov, niravd
Reviewed By: niravd
Subscribers: vitalybuka, llvm-commits
Differential Revision: https://reviews.llvm.org/D35998
llvm-svn: 310254
Simon Dardis [Mon, 7 Aug 2017 13:30:03 +0000 (13:30 +0000)]
[DebugInfo][DWARF] Use PRIx64 explicitly in output.
llvm-svn: 310253
Michael Zuckerman [Mon, 7 Aug 2017 13:22:39 +0000 (13:22 +0000)]
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF16 stride 4).
This patch expands the support of lowerInterleavedStore to 16x8i stride 4.
LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=16) and we plan to include more patterns in the future.
The patch goal is to optimize the following sequence:
At the end of the computation, we have ymm2, ymm0, ymm12 and ymm3 holding
each 16 chars:
c0, c1, , c16
m0, m1, , m16
y0, y1, , y16
k0, k1, ., k16
And these need to be transposed/interleaved and stored like so:
c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....
Differential Revision: https://reviews.llvm.org/D35829
llvm-svn: 310252
Dmitry Preobrazhensky [Mon, 7 Aug 2017 13:14:12 +0000 (13:14 +0000)]
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35902
llvm-svn: 310251
Simon Dardis [Mon, 7 Aug 2017 12:29:38 +0000 (12:29 +0000)]
[llvm-objdump] Use PRIx64 for output of ARM64_RELOC_ADDEND
llvm-svn: 310250
Simon Pilgrim [Mon, 7 Aug 2017 12:24:33 +0000 (12:24 +0000)]
[X86][AVX] Added test for broadcast shuffle with undefs (PR34041)
llvm-svn: 310249
Kamil Rytarowski [Mon, 7 Aug 2017 10:59:44 +0000 (10:59 +0000)]
Add NetBSD support in sanitizer_test_utils.h
Summary:
NetBSD ships with printf_l(3) like FreeBSD.
NetBSD does not ship with memalign, pvalloc, malloc with "usable size"
and is the same here as Darwin, Android, FreeBSD and Windows.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, vitalybuka, kcc, fjricci, filcab
Reviewed By: vitalybuka
Subscribers: srhines, llvm-commits, emaste, kubamracek, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D36373
llvm-svn: 310248
Kamil Rytarowski [Mon, 7 Aug 2017 10:58:48 +0000 (10:58 +0000)]
Add NetBSD support in asan_errors.cc
Summary:
Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, fjricci, vitalybuka, filcab, kcc
Reviewed By: vitalybuka
Subscribers: llvm-commits, kubamracek, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D36374
llvm-svn: 310247
Kamil Rytarowski [Mon, 7 Aug 2017 10:57:58 +0000 (10:57 +0000)]
Add NetBSD support in asan_interceptors.h
Summary:
Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, filcab, kcc, fjricci, vitalybuka
Reviewed By: vitalybuka
Subscribers: kubamracek, llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D36375
llvm-svn: 310246
Kamil Rytarowski [Mon, 7 Aug 2017 10:57:03 +0000 (10:57 +0000)]
Enable LLVM asan support for NetBSD/i386
Summary:
Verified to work and useful to run check-asan, as this target tests 32-bit and 64-bit execution.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, filcab, dim, vitalybuka
Reviewed By: vitalybuka
Subscribers: #sanitizers, cfe-commits
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D36378
llvm-svn: 310245
Vitaly Buka [Mon, 7 Aug 2017 09:08:44 +0000 (09:08 +0000)]
[asan] Return sizeof missed by r309914
llvm-svn: 310244
Andre Vieira [Mon, 7 Aug 2017 08:41:05 +0000 (08:41 +0000)]
[ARM] Fix assembly and disassembly for VMRS/VMSR
This patch addresses two issues with assembly and disassembly for VMRS/VMSR:
1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
accepted for non ARMv8-A targets.
2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only
ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.
This patch addresses those issues and adds tests for these cases.
Differential Revision: https://reviews.llvm.org/D36306
llvm-svn: 310243
Vitaly Buka [Mon, 7 Aug 2017 07:35:33 +0000 (07:35 +0000)]
[asan] Fix asan dynamic shadow check before copyArgsPassedByValToAllocas
llvm-svn: 310242
Vitaly Buka [Mon, 7 Aug 2017 07:12:34 +0000 (07:12 +0000)]
[asan] Disable checking of arguments passed by value for --asan-force-dynamic-shadow
Fails with "Instruction does not dominate all uses!"
llvm-svn: 310241
Vitaly Buka [Mon, 7 Aug 2017 07:12:33 +0000 (07:12 +0000)]
Add -asan-force-dynamic-shadow test
llvm-svn: 310240
Guy Blank [Mon, 7 Aug 2017 05:51:14 +0000 (05:51 +0000)]
[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks
The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types.
But before calling CodeGenAndEmitDAG we build the DAG for the basic block.
So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'.
This patch sets the flag to false before SDAG building each basic block.
Differential Revision:
https://reviews.llvm.org/D33435
llvm-svn: 310239
Davide Italiano [Mon, 7 Aug 2017 01:57:21 +0000 (01:57 +0000)]
[Reassociate] Use a range loop for clarity. NFCI.
While here, rename `i` to `Rank` as the latter is more
self-explanatory (and this code also uses `I` two lines below to
identify an Instruction).
llvm-svn: 310238
Davide Italiano [Mon, 7 Aug 2017 01:49:09 +0000 (01:49 +0000)]
[Reassociate] Try to bail out early when canonicalizing.
This commit rearranges the checks to avoid calls to getRank()
when not needed (e.g. when RHS == LHS).
llvm-svn: 310237
Tobias Grosser [Mon, 7 Aug 2017 00:10:11 +0000 (00:10 +0000)]
[ScopInfo] Make Scop::canAlwaysBeHoisted a member function
llvm-svn: 310236
Tobias Grosser [Sun, 6 Aug 2017 23:50:25 +0000 (23:50 +0000)]
[ScopInfo] Move Scop::addInvariantLoads to isl++ [NFC]
llvm-svn: 310235
Craig Topper [Sun, 6 Aug 2017 23:30:49 +0000 (23:30 +0000)]
[InstCombine] Remove shift handling from OptAndOp.
Summary: This is all handled by SimplifyDemandedBits.
Reviewers: spatel, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D36382
llvm-svn: 310234
Craig Topper [Sun, 6 Aug 2017 23:11:49 +0000 (23:11 +0000)]
[InstCombine] Support (X ^ C1) & C2 --> (X & C2) ^ (C1&C2) for vector splats.
llvm-svn: 310233
Craig Topper [Sun, 6 Aug 2017 22:17:21 +0000 (22:17 +0000)]
[InstCombine] Support '(C - X) ^ signmask -> (C + signmask - X)' and '(X + C) ^ signmask -> (X + C + signmask)' for vector splats.
llvm-svn: 310232
Tobias Grosser [Sun, 6 Aug 2017 21:42:38 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getPwAffOnly to isl++ [NFC]
llvm-svn: 310231
Tobias Grosser [Sun, 6 Aug 2017 21:42:25 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getDomains to isl++ [NFC]
llvm-svn: 310230
Tobias Grosser [Sun, 6 Aug 2017 21:42:16 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getInvalidContext to isl++ [NFC]
llvm-svn: 310229
Tobias Grosser [Sun, 6 Aug 2017 21:42:09 +0000 (21:42 +0000)]
[ScopInfo] Move Scop::getAssumedContext to isl++ [NFC]
llvm-svn: 310228
Simon Pilgrim [Sun, 6 Aug 2017 20:50:19 +0000 (20:50 +0000)]
[SLPVectorizer][X86] Cleanup test case. NFCI
Remove excess attributes/metadata
llvm-svn: 310227
Erik Pilkington [Sun, 6 Aug 2017 20:46:33 +0000 (20:46 +0000)]
[demangler] Fix another oss-fuzz bug
llvm-svn: 310226
Tobias Grosser [Sun, 6 Aug 2017 20:19:26 +0000 (20:19 +0000)]
[ScopInfo] Move Scop::addNonEmptyDomainConstraints to isl++ [NFC]
llvm-svn: 310225
Tobias Grosser [Sun, 6 Aug 2017 20:11:59 +0000 (20:11 +0000)]
[ScopInfo] Translate Scop::getParamSpace to isl++ [NFC]
llvm-svn: 310224
Martin Storsjo [Sun, 6 Aug 2017 19:58:13 +0000 (19:58 +0000)]
[llvm-dlltool] Map the "arm64" machine type
Differential Revision: https://reviews.llvm.org/D36365
llvm-svn: 310223
Martin Storsjo [Sun, 6 Aug 2017 19:57:49 +0000 (19:57 +0000)]
[test] Remove an unintentional -x cl flag in an aarch64-windows test
This test was only intended to test compiling C, not OpenCL.
Differential Revision: https://reviews.llvm.org/D36363
llvm-svn: 310222
Tobias Grosser [Sun, 6 Aug 2017 19:52:38 +0000 (19:52 +0000)]
[ScopInfo] Translate Scop::getContext to isl++ [NFC]
llvm-svn: 310221
Tobias Grosser [Sun, 6 Aug 2017 19:31:27 +0000 (19:31 +0000)]
[ScopInfo] Translate Scop::getIdForParam to isl++ [NFC]
llvm-svn: 310220
Tobias Grosser [Sun, 6 Aug 2017 19:22:27 +0000 (19:22 +0000)]
[ScopInfo] Move get*Writes/getReads/getAccesses to isl++
llvm-svn: 310219
Tobias Grosser [Sun, 6 Aug 2017 18:59:19 +0000 (18:59 +0000)]
Remove functional changes that sneaked in by accident in r308892
llvm-svn: 310218
Matt Arsenault [Sun, 6 Aug 2017 18:13:23 +0000 (18:13 +0000)]
AMDGPU: Fix typo in feature description
llvm-svn: 310217
Tobias Grosser [Sun, 6 Aug 2017 17:53:04 +0000 (17:53 +0000)]
[ScopInfo] Move ScopStmt::setAstBuild/getAstBuild to isl++
llvm-svn: 310216
Tobias Grosser [Sun, 6 Aug 2017 17:45:28 +0000 (17:45 +0000)]
[ScopInfo] Move ScopStmt::getSchedule to isl++
llvm-svn: 310215
Tobias Grosser [Sun, 6 Aug 2017 17:31:38 +0000 (17:31 +0000)]
[ScopInfo] Move getPredecessorDomainConstraints to isl++ [NFC]
llvm-svn: 310214
Tobias Grosser [Sun, 6 Aug 2017 17:25:14 +0000 (17:25 +0000)]
[ScopInfo] Move InvariantAccess to isl++ [NFC]
llvm-svn: 310213
Tobias Grosser [Sun, 6 Aug 2017 17:25:09 +0000 (17:25 +0000)]
[ScopInfo] Update comments to refer to isl++ [NFC]
llvm-svn: 310212
Tobias Grosser [Sun, 6 Aug 2017 17:25:05 +0000 (17:25 +0000)]
[ScopInfo] Move ScopArrayInfo::ScopArrayInfo to isl++ [NFC]
llvm-svn: 310211
Tobias Grosser [Sun, 6 Aug 2017 17:24:59 +0000 (17:24 +0000)]
[ScopInfo] Move ScopStmt::ScopStmt to isl++ [NFC]
llvm-svn: 310210
Tobias Grosser [Sun, 6 Aug 2017 16:39:52 +0000 (16:39 +0000)]
Move ScopInfo::getDomain(), getDomainSpace(), getDomainId() to isl++
llvm-svn: 310209
Sanjay Patel [Sun, 6 Aug 2017 16:27:07 +0000 (16:27 +0000)]
[x86] use more shift or LEA for select-of-constants
We can convert any select-of-constants to math ops:
http://rise4fun.com/Alive/d7d
For this patch, I'm enhancing an existing x86 transform that uses fake multiplies
(they always become shl/lea) to avoid cmov or branching. The current code misses
cases where we have a negative constant and a positive constant, so this is just
trying to plug that hole.
The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start
with a select in IR, create a select DAG node, convert it into a sext, convert it
back into a select, and then lower it to sext machine code.
Some notes about the test diffs:
1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR.
2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. I
think we could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on
a different reg? That's a post-DAG problem though.
3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if
that's a regression, but I think those would always be nearly equivalent.
4. pr22338.ll and sext-i1.ll - These tests have undef operands, so I don't think we actually care about these diffs.
5. sbb.ll - This shows a win for what I think is a common case: choose -1 or 0.
6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again.
7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops.
Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass.
Differential Revision: https://reviews.llvm.org/D35340
llvm-svn: 310208
Tobias Grosser [Sun, 6 Aug 2017 16:11:53 +0000 (16:11 +0000)]
Move ScopStmt::Domain to isl++
llvm-svn: 310207
Tobias Grosser [Sun, 6 Aug 2017 15:56:45 +0000 (15:56 +0000)]
Update to a newer version of isl++
llvm-svn: 310206
Tobias Grosser [Sun, 6 Aug 2017 15:51:16 +0000 (15:51 +0000)]
Update to isl-0.18-812-g565da6e
This update is mostly a maintenance update, but also exposes a couple of new
functions that will be needed for the next version of the isl++ bindings.
llvm-svn: 310205
Tobias Grosser [Sun, 6 Aug 2017 15:47:04 +0000 (15:47 +0000)]
[Scopinfo] Fix memory corruption issue that sneaked into the previous commit
llvm-svn: 310204
Tobias Grosser [Sun, 6 Aug 2017 15:36:48 +0000 (15:36 +0000)]
[ScopInfo] Move InvalidDomain to isl++ [NFC]
llvm-svn: 310203
Simon Pilgrim [Sun, 6 Aug 2017 13:21:09 +0000 (13:21 +0000)]
[X86] Add comment to match closing Defs = [FPSW]. NFCI.
llvm-svn: 310202
Simon Pilgrim [Sun, 6 Aug 2017 12:17:10 +0000 (12:17 +0000)]
[X86][X87] Regenerate inline-asm tests
llvm-svn: 310201
Meador Inge [Sun, 6 Aug 2017 12:02:17 +0000 (12:02 +0000)]
[AVR] Compute code model if one is not provided
The patch from r310028 fixed things to work with the new
`LLVMTargetMachine` constructor that came in on r309911.
However, the fix was partial since an object of type
`CodeModel::Model` must be passed to `LLVMTargetMachine`
(not one of `Optional<CodeModel::Model>`).
This patch fixes the problem in the same fashion that r309911
did for other machines: by checking if the passed optional
code model has a value and using `CodeModel::Small` if not.
llvm-svn: 310200
Tobias Grosser [Sun, 6 Aug 2017 11:41:10 +0000 (11:41 +0000)]
[Polly] Fix for the JSON Exporter
Summary:
Small patch to fix the JSON exporter.
Currently, using "opt -polly-export-jscop" does not generate jscop files, but gives an error:
*** Error in `opt': corrupted double-linked list: 0x0000000000bc4bb0 ***
Updated the function getAccessRelationStr() to work with the current version of getAccessRelation(), fixing the JSON exporter
Reviewers: bollu, grosser
Reviewed By: grosser
Subscribers: grosser, llvm-commits, pollydev
Tags: #polly
Differential Revision: https://reviews.llvm.org/D36370
llvm-svn: 310199
Simon Pilgrim [Sun, 6 Aug 2017 11:22:33 +0000 (11:22 +0000)]
[X86][X87] Add test case for PR34080
Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets.
pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations).
llvm-svn: 310198
Tobias Grosser [Sun, 6 Aug 2017 11:21:09 +0000 (11:21 +0000)]
Add missing 'REQUIRES: pollyacc' line
llvm-svn: 310197
Tobias Grosser [Sun, 6 Aug 2017 11:10:38 +0000 (11:10 +0000)]
[GPGPU] Make sure managed arrays are prepared at the beginning of the scop
Summary:
This resolves some "instruction does not dominate use" errors, as we used to
prepare the arrays at the location of the first kernel, which not necessarily
dominated all other kernel calls.
Reviewers: Meinersbur, bollu, singam-sanjay
Subscribers: nemanjai, pollydev, llvm-commits, kbarton
Differential Revision: https://reviews.llvm.org/D36372
llvm-svn: 310196
Craig Topper [Sun, 6 Aug 2017 06:28:41 +0000 (06:28 +0000)]
[InstCombine] Support ~(c-X) --> X+(-c-1) and ~(X-c) --> (-c-1)-X for splat vectors.
llvm-svn: 310195
Tobias Grosser [Sun, 6 Aug 2017 03:04:15 +0000 (03:04 +0000)]
[GPGPU] Rename all, not only the first libdevice function
llvm-svn: 310194
Siddharth Bhat [Sun, 6 Aug 2017 02:39:05 +0000 (02:39 +0000)]
[Polly] [PPCGCodeGeneration] Deal with loops outside the Scop correctly in PPCGCodeGeneration.
A Scop with a loop outside it is not handled currently by
PPCGCodeGeneration. The test case is such that the Scop has only one inner loop
that is detected. This currently breaks codegen.
The fix is to reuse the existing mechanism in `IslNodeBuilder` within
`GPUNodeBuilder.
Differential Revision: https://reviews.llvm.org/D36290
llvm-svn: 310193
Siddharth Bhat [Sun, 6 Aug 2017 02:07:11 +0000 (02:07 +0000)]
[IslNodeBuilder] [NFC] Refactor creation of loop induction variables of loops outside scops.
This logic is duplicated, so we refactor it into a separate function.
This will be used in a later patch to teach PPCGCodeGen code generation
for loops that are outside the scop.
Differential Revision: https://reviews.llvm.org/D36310
llvm-svn: 310192
Craig Topper [Sat, 5 Aug 2017 23:35:54 +0000 (23:35 +0000)]
[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled. Clang part
Summary:
On older processors this instruction encoding is treated as a NOP.
MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.
This change also seems to also be consistent with gcc behavior.
Fixes PR34079
Reviewers: RKSimon, zvi
Reviewed By: RKSimon
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D36362
llvm-svn: 310191
Craig Topper [Sat, 5 Aug 2017 23:34:44 +0000 (23:34 +0000)]
[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled
Summary:
On older processors this instruction encoding is treated as a NOP.
MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.
This change also seems to also be consistent with gcc behavior.
Fixes PR34079
Reviewers: RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36361
llvm-svn: 310190
Chandler Carruth [Sat, 5 Aug 2017 22:48:37 +0000 (22:48 +0000)]
[ADT] Add a much simpler loop to DenseMap::clear when the types are
POD-like and we can just splat the empty key across memory.
Sadly we can't optimize the normal loop well enough because we can't
turn the conditional store into an unconditional store according to the
memory model.
This loop actually showed up in a profile of code that was calling clear
as a serious source of time. =[
llvm-svn: 310189
Craig Topper [Sat, 5 Aug 2017 22:44:38 +0000 (22:44 +0000)]
[InstCombine] Regenerate test28_sub test case in xor.ll that I forgot to commit after fixing a typo in r310186.
llvm-svn: 310188
Tobias Grosser [Sat, 5 Aug 2017 20:03:13 +0000 (20:03 +0000)]
[Polly] Fix typo. NFC.
Reviewers: grosser, Meinersbur, bollu
Differential Revision: https://reviews.llvm.org/D36356
llvm-svn: 310187
Craig Topper [Sat, 5 Aug 2017 20:00:44 +0000 (20:00 +0000)]
[InstCombine] Fold (C - X) ^ signmask -> (C + signmask - X).
llvm-svn: 310186
Craig Topper [Sat, 5 Aug 2017 20:00:42 +0000 (20:00 +0000)]
[InstCombine] Teach the code that pulls logical operators through constant shifts to handle vector splats too.
llvm-svn: 310185
Craig Topper [Sat, 5 Aug 2017 20:00:41 +0000 (20:00 +0000)]
[InstCombine] Support vector splats in foldSelectICmpAnd.
Unfortunately, it looks like there's some other missed optimizations in the generated code for some of these cases. I'll try to look at some of those next.
llvm-svn: 310184
Dinar Temirbulatov [Sat, 5 Aug 2017 18:43:52 +0000 (18:43 +0000)]
[SLPVectorizer] Add extra parameter to setInsertPointAfterBundle to handle different opcodes, NFCI.
Differential Revision: https://reviews.llvm.org/D35769
llvm-svn: 310183
Kamil Rytarowski [Sat, 5 Aug 2017 18:10:51 +0000 (18:10 +0000)]
Add NetBSD support in sanitizer_errno.h
Summary:
NetBSD ships with __errno (value for __errno_location) like Android.
Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, vitalybuka, fjricci, kcc, filcab
Reviewed By: vitalybuka
Subscribers: llvm-commits, srhines, kubamracek, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D36360
llvm-svn: 310182
Sanjay Patel [Sat, 5 Aug 2017 15:19:18 +0000 (15:19 +0000)]
[InstCombine] refactor trunc(binop) transforms; NFCI
In addition to moving the shift transforms over, we may want to
detect too-wide rotate patterns here (PR34046).
llvm-svn: 310181
Florian Hahn [Sat, 5 Aug 2017 15:14:06 +0000 (15:14 +0000)]
[ARM] The ARM backend is MachineVerifier clean now.
Summary: Thanks everyone involved in fixing the outstanding issues.
Reviewers: rovka, MatzeB, efriedma
Reviewed By: MatzeB
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36153
llvm-svn: 310180
Kamil Rytarowski [Sat, 5 Aug 2017 13:36:49 +0000 (13:36 +0000)]
Add NetBSD support in sanitizer_unwind_linux_libcdep.cc
Summary:
NetBSD is a POSIX-like and BSD-family system.
Reuse FreeBSD and Linux code.
NetBSD uses DWARF ExceptionHandler.
Part of the code inspired by the original work on libsanitizer in GCC 5.4 by Christos Zoulas.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, kcc, filcab, vitalybuka
Reviewed By: vitalybuka
Subscribers: srhines, emaste, llvm-commits, kubamracek, aprantl, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D36314
llvm-svn: 310179
Florian Hahn [Sat, 5 Aug 2017 12:13:13 +0000 (12:13 +0000)]
[ARM] Add registers to debuginfo MIR test cases.
Summary:
MIRParserImpl::computeFunctionProperties uses MRI.getNumVirtRegs() to
set the NoVReg property. By adding a bunch of registers to the MIR test
cases, the NoVReg property is not set when importing the MIR. Otherwise
NoVReg is set after instruction selection while the machine instructions
still contain virtual registers, causing expensive checks to fail.
Reviewers: efriedma, MatzeB, aprantl
Reviewed By: MatzeB, aprantl
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D36152
llvm-svn: 310178
Tobias Grosser [Sat, 5 Aug 2017 09:44:11 +0000 (09:44 +0000)]
Add forgotten CMakeLists.txt file in unit-test
llvm-svn: 310177
Tobias Grosser [Sat, 5 Aug 2017 09:39:00 +0000 (09:39 +0000)]
Fix spelling error in previous commit
llvm-svn: 310176
Tobias Grosser [Sat, 5 Aug 2017 09:38:09 +0000 (09:38 +0000)]
[unittests] Add unittest for getPartialTilePrefixes
In https://reviews.llvm.org/D36278 it was pointed out that the behavior of
getPartialTilePrefixes is not very well understood. To allow for a better
understanding, we first provide some basic unittests.
llvm-svn: 310175
Chandler Carruth [Sat, 5 Aug 2017 08:33:16 +0000 (08:33 +0000)]
[LCG] Remove yet another variable only used inside of asserts.
llvm-svn: 310174
Benjamin Kramer [Sat, 5 Aug 2017 08:28:48 +0000 (08:28 +0000)]
[LCG] Fold otherwise unused variable into assert.
No functionality change intended.
llvm-svn: 310173
Matt Arsenault [Sat, 5 Aug 2017 07:50:18 +0000 (07:50 +0000)]
IPRA: Don't crash on null getCallPreservedMask
Kernels aren't callable, so they don't have a call preserved mask.
llvm-svn: 310172
Chandler Carruth [Sat, 5 Aug 2017 07:37:00 +0000 (07:37 +0000)]
[LCG] Completely remove the parent set and leaf tracking for RefSCCs.
After the previous series of patches, this is now trivial and deletes
a pretty astonishing amount of complexity. This has been a long time
coming, as the move toward a PO sequence of RefSCCs started eroding the
underlying use cases for this half of the data structure.
Among the biggest advantages here is that now there aren't two
independent data structures that need to stay in sync.
Some of my profiling has also indicated that updating the parent sets
was among the most expensive parts of the lazy call graph. Eliminating
it whole sale is likely to be a nice win in terms of compile time.
Last but not least, I had discussed with some folks previously keeping
it around for asserts and other correctness checking, but once the
fundamentals of the parent and child checking were implemented without
the parent sets their value in correctness checking was tiny and no
where near worth the cost of the complexity required to keep everything
up-to-date.
llvm-svn: 310171
Chandler Carruth [Sat, 5 Aug 2017 06:24:09 +0000 (06:24 +0000)]
[LCG] Re-implement the basic isParentOf, isAncestorOf, isChildOf, and
isDescendantOf methods on RefSCCs in terms of the forward edges rather
than the parent sets.
This is technically slower, but probably not interestingly slower, and
all of these routines were already so expensive that they're guarded
behind both !NDEBUG and EXPENSIVE_CHECKS.
This removes another non-critical usage of parent sets.
I've also added some comments to try and help clarify to any potential
users the costs of these routines. They're mostly useful for debugging,
asserts, or other queries.
llvm-svn: 310170
Chandler Carruth [Sat, 5 Aug 2017 05:47:37 +0000 (05:47 +0000)]
[LCG] Add the concept of a "dead" node and use it to avoid a complex
walk over the parent set.
When removing a single function from the call graph, we previously would
walk the entire RefSCC's parent set and then walk every outgoing edge
just to find the ones to remove. In addition to this being quite high
complexity in theory, it is also the last fundamental use of the parent
sets.
With this change, when we remove a function we transform the node
containing it to be recognizably "dead" and then teach the edge
iterators to recognize edges to such nodes and skip them the same way
they skip null edges.
We can't move fully to using "dead" nodes -- when disconnecting two live
nodes we need to null out the edge. But the complexity this adds to the
edge sequence isn't too bad and the simplification of lazily handling
this seems like a significant win.
llvm-svn: 310169
Shoaib Meenai [Sat, 5 Aug 2017 05:01:07 +0000 (05:01 +0000)]
[lld] Allow rel iplt symbols with dynamic symbol table
Emit these symbols as long as we're building in a static configuration,
even if we're emitting a dynamic symbol table. This is consistent with
both bfd and gold.
Ordinarily, the combination of -static and -export-dynamic wouldn't make
much sense. Unfortunately, cmake versions prior to 3.4 forcefully
injected -rdynamic [1], so it seems worthwhile to support.
[1] https://cmake.org/cmake/help/v3.4/policy/CMP0065.html
Differential Revision: https://reviews.llvm.org/D36350
llvm-svn: 310168
Joel Jones [Sat, 5 Aug 2017 04:30:55 +0000 (04:30 +0000)]
[AArch64] LSE Atomics reorg - part 1
Add memory synchronization semantics to LSE Atomics.
The memory semantics feature will be added in a subsequent patch.
In this patch, several corrections were added to the existing LSE Atomics
implementation, based on the ARM Errata D11904 from 05/12/2017.
Patch by: steleman
Differential Revision: https://reviews.llvm.org/D35319
llvm-svn: 310167
Rui Ueyama [Sat, 5 Aug 2017 04:07:21 +0000 (04:07 +0000)]
Replace CRLF.
llvm-svn: 310166
Chandler Carruth [Sat, 5 Aug 2017 04:04:06 +0000 (04:04 +0000)]
[LCG] Replace an implicit bool operator with a named function. (NFC)
The definition of 'false' here was already pretty vague and debatable,
and I'm about to add another potential 'false' that would actually make
much more sense in a bool operator. Especially given how rarely this is
used, a nicely named method seems better.
llvm-svn: 310165
Chandler Carruth [Sat, 5 Aug 2017 03:37:39 +0000 (03:37 +0000)]
[LCG] When removing a dead function and clearing out the data
structures, actually null out the graph pointers as well. We won't ever
update these, and we certainly shouldn't be calling any methods on them,
so it seems good to defensively nuke them.
llvm-svn: 310164
Chandler Carruth [Sat, 5 Aug 2017 03:37:39 +0000 (03:37 +0000)]
[LCG] Rather than walking the directed graph structure to update graph
pointers in node objects, just walk the map from function to node.
It doesn't have stable ordering, but works just as well and is much
simpler. We don't need ordering when just updating internal pointers.
llvm-svn: 310163
Chandler Carruth [Sat, 5 Aug 2017 03:37:38 +0000 (03:37 +0000)]
[LCG] Remove the complex walk of the parent sets to update graph
pointers.
This is completely unnecessary as we have a trivial list of RefSCCs now
that we can walk.
llvm-svn: 310162
Chandler Carruth [Sat, 5 Aug 2017 03:37:37 +0000 (03:37 +0000)]
[LCG] Remove the use of the parent sets to compute connectivity when
merging RefSCCs.
The logic to directly use the reference edges is simpler and not
substantially slower (despite the comments to the contrary) because this
is not actually an especially hot part of LCG in practice.
llvm-svn: 310161