Samuel Pitoiset [Thu, 26 Nov 2020 11:03:55 +0000 (12:03 +0100)]
radv/winsys: fix the sysmem submission path for GFX6
Oops.
Fixes:
cba6ec309ab ("radv: Fix -Wshadow warnings")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7790>
James Park [Thu, 26 Nov 2020 10:05:22 +0000 (02:05 -0800)]
radv: Const aco_compiler_statistic_info usage
Necessary for upcoming const correctness change to aco struct.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7787>
Samuel Pitoiset [Thu, 26 Nov 2020 11:27:10 +0000 (12:27 +0100)]
radv: fix missing initialization of the predication value
It's expected to be 0.
Fixes:
62d9ca696e0 ("radv: use 32-bit predication for conditional rendering on GFX10.3+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7789>
Alejandro Piñeiro [Tue, 24 Nov 2020 21:25:21 +0000 (22:25 +0100)]
v3dv: remove non-conformant warning
The driver is now Vulkan 1.0 conformant.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7758>
Alejandro Piñeiro [Tue, 24 Nov 2020 21:24:21 +0000 (22:24 +0100)]
docs/features: update list of v3dv supported features
We have been implementing some features without updating the file, and
we even had some that were supported for a while.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
v2: include VK_KHR_wayland_surface as !7303 got merged
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7758>
Pierre-Eric Pelloux-Prayer [Tue, 24 Nov 2020 10:13:48 +0000 (11:13 +0100)]
ac: use bigger storage for ac_arg::arg_index / ac_shader_args::arg_count
AC_MAX_ARGS is now 384 so uint8_t isn't enough.
Fixes:
6f130342658 ("ac/llvm: prepare for passing VS->TCS IO via VGPRs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7750>
Pierre-Eric Pelloux-Prayer [Mon, 23 Nov 2020 12:48:42 +0000 (13:48 +0100)]
radeonsi/gfx10: flush gfx cs on ngg -> legacy transition
with a sequence like this:
glClear(STENCIL)
glBeginTransformFeedback()
...
glEndTransformFeedback()
glClear(STENCIL)
The second clear sometimes may produce an unexpected result.
Calling si_flush_gfx_cs() when doing ngg -> legacy transition seems to be a
valid workaround (both for the synthetic reproducer and the real Blender bug).
Using flush flags or events (BOTTOM_OF_PIPE_TS, RESET_TO_LOWEST_VGT) didn't help.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7750>
James Park [Sat, 31 Oct 2020 23:18:34 +0000 (16:18 -0700)]
util,radv: Cross-platform monotonic condition variable
cnd_t operates on REALTIME clock, and isn't suitable for MONOTONIC use.
Clone the API, and implement using a monotonic clock.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Tue, 3 Nov 2020 18:03:13 +0000 (10:03 -0800)]
util/os_time: Safe os_time_get_nano for Windows
Avoid small possibility of reading torn write on 32-bit platforms.
If frequency caching is desired, it's probably better to initialize from
C++ and extern "C" instead. It's not a tremendous optimization though.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Wed, 12 Aug 2020 02:28:09 +0000 (19:28 -0700)]
c11/threads: Remove Windows XP support
Enable and remove EMULATED_THREADS_USE_NATIVE_CV. Delete legacy code.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Wed, 12 Aug 2020 02:26:39 +0000 (19:26 -0700)]
c11/threads: Remove Win32 null checks
Nonsensical to pass null. glibc doesn't check, and neither should we.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
James Park [Wed, 12 Aug 2020 02:24:12 +0000 (19:24 -0700)]
c11/threads: Fix Win32 timed functions
mtx_timedlock and cnd_timedwait now use relative milliseconds.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7138>
Thong Thai [Mon, 21 Sep 2020 17:56:05 +0000 (13:56 -0400)]
frontends/va/postproc: Convert destination when deinterlacing
When the VAAPI deinterlacing filter is chained with other VAAPI
post-processing filters, the image might get deinterlaced multiple
times, as the filters after the deinterlacing filter might still see an
interlaced buffer.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6803>
Thong Thai [Mon, 21 Sep 2020 17:53:16 +0000 (13:53 -0400)]
frontends/va/postproc: Use the actual image height when blitting
Updates the height of the blitting parameter to use the actual image
height instead of the buffer height, otherwise when scaling, garbage
lines are shown in the output.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6803>
Caio Marcelo de Oliveira Filho [Tue, 24 Nov 2020 06:04:51 +0000 (21:04 -0900)]
intel/disasm: Don't rely on FALLTHROUGHTs to print unsupported SFID
The code works but is a bit fragile if we ever add a case that has a
less strict requirement (a smaller gen) than the case above. To avoid
having to reason about this, refactor code to use a variable to
indicate whether the SFID is supported or not.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7742>
Boris Brezillon [Sat, 21 Nov 2020 15:03:32 +0000 (16:03 +0100)]
panfrost: Fix stride calculation for Z32_S8X24/X32_S8X24 formats
Z32_S8X24 variants are actually stored in 2 planes (one per component),
we have to adjust the bytes_per_pixel value accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Sat, 21 Nov 2020 14:58:41 +0000 (15:58 +0100)]
panfrost: Calculate the row stride at resource creation time
So we don't have to calculate it again when we create a texture or
framebuffer descriptor.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Sat, 21 Nov 2020 14:52:28 +0000 (15:52 +0100)]
panfrost: Fix panfrost_needs_explicit_stride() for block-based formats
The expected stride calculation does not take the block width into
account, thus creating an expected line stride that's bigger than
required. Fix that by dividing the width by the block width.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Sat, 21 Nov 2020 14:44:10 +0000 (15:44 +0100)]
panfrost: Expose panfrost_block_dim()
So we can use it from pan_resource.c to retrieve the tile size based on
a modifier.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 08:32:40 +0000 (09:32 +0100)]
panfrost: Enable MSAA on bifrost when deqp debug option is set
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:12:53 +0000 (10:12 +0100)]
panfrost: Unconditionally align strides on 64 bytes for linear resources
If we don't do that we end up with DATA_INVALID faults when accessing
3D textures on Bifrost.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:38:09 +0000 (10:38 +0100)]
panfrost: Set the layer stride
Needed for 3D textures.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:35:55 +0000 (10:35 +0100)]
panfrost: Add two helpers to calculate the surface pointer and strides
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Thu, 19 Nov 2020 09:14:42 +0000 (10:14 +0100)]
panfrost: Clarify bit 2:28 meaning in the Midgard texture descriptor
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Wed, 18 Nov 2020 14:22:59 +0000 (15:22 +0100)]
panfrost: Add a minus(1) modifier to the Levels field
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 11:14:02 +0000 (12:14 +0100)]
panfrost: Increase blit shader BO size on Bifrost
Otherwise we hit 'offset + program->compiled.size < total_size' assert.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 16:27:40 +0000 (17:27 +0100)]
pan/bi: LOD is a 8.8 fixed point
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:25:41 +0000 (11:25 +0100)]
pan/bi: Always emit a LOD/CUBE word for FETCH instructions
There's no flag/mode to reflect when a LOD is zero on FETCH instructions,
we have to emit the LOD/CUBE word unconditionally.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:23:35 +0000 (11:23 +0100)]
pan/bi: Only update LOD mode on TEX operations
If we don't add this check we clobber fetch mode when a 0 LOD is
specified on a txf instruction.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:20:35 +0000 (11:20 +0100)]
panfrost: Set sample_count when packing bifrost texture descriptors
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 18:09:26 +0000 (19:09 +0100)]
panfrost: Set depth for 3D textures on Bifrost
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 18:18:42 +0000 (19:18 +0100)]
panfrost: Fix decoding of texture payloads
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 10:19:43 +0000 (11:19 +0100)]
panfrost: Get rid of the Sample Count enum
Sample count just needs a log2 modifier. While at it, rename the
"Multisample count" field "Sample count" to be consistent with
other descriptors.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 19:44:52 +0000 (20:44 +0100)]
panfrost: Stop forcing depth to nr_samples
Those are two different things, and the fact that Midgard use the same
offset in the texture descriptor for both things is just an
implementation detail.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Alyssa Rosenzweig [Mon, 9 Nov 2020 19:31:01 +0000 (14:31 -0500)]
panfrost: Fix RAW8/16/32 component replication
Fixes dEQP-GLES3.functional.fbo.msaa.4_samples.r32f
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Alyssa Rosenzweig [Mon, 9 Nov 2020 19:43:36 +0000 (14:43 -0500)]
panfrost: Account for sample count in tib offsets
I don't know if we have tests for MRT + MSAA but that would hit this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Boris Brezillon [Tue, 17 Nov 2020 11:12:08 +0000 (12:12 +0100)]
nir: Fix LOD source type for txf_ms instructions
txf_ms takes an integer LOD, not a float.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
Rhys Perry [Thu, 12 Nov 2020 14:32:57 +0000 (14:32 +0000)]
aco/ngg: fix division-by-zero in assertion
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
Rhys Perry [Thu, 12 Nov 2020 14:21:00 +0000 (14:21 +0000)]
aco: fix GS with no outputs
With NGG, ngg_gs_known_vtxcnt[0] would be false and ngg_gs_finale() would
assert.
With legacy GS, I don't know why the assertion was there.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
Rhys Perry [Wed, 18 Nov 2020 19:13:19 +0000 (19:13 +0000)]
radv/llvm,aco/ngg: fix large shift exponent in ngg_gs_vertex_lds_addr
When vertices_out=0, we will try to shift 1u by UINT32_MAX.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7576>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:34:25 +0000 (17:34 -0500)]
pan/bi: Implement shader-db stats
v2: Drop register tracking since it was wrong, and meaningful accounting
is tricky for Bifrost (which wants round robin RA for at least some
registers)... we'll cross that bridge when we get there, possibly
preferring a "max liveness" estimate to the raw RA output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Tue, 24 Nov 2020 19:53:55 +0000 (14:53 -0500)]
pan/bi: Ensure TEXC src0 is not marked SSA
Prevents attempts to spill tied TEXC src/dest, resulting in a crash,
seen in shaders/tesseract/229.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Boris Brezillon [Tue, 17 Nov 2020 20:48:27 +0000 (21:48 +0100)]
pan/bi: Emit a combine even if we only pass one staging reg to TEXC
We need that to account for potential swizzling on the source reg.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Tue, 24 Nov 2020 18:56:52 +0000 (13:56 -0500)]
pan/bi: Fix off-by-one in RA
Could result in trying to allocate R64 which is clearly wrong.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:09:27 +0000 (17:09 -0500)]
pan/bi: Fix varying writemask handling
Allows shaders/supertuxkart/1.shader_test and
shaders/unity/24-Tree.shader_test to compile.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:04:43 +0000 (17:04 -0500)]
pan/bi: Implement sampler1D
Enough to get shaders/humus-celshading/1.shader_test compiling, no idea
if it actually works but it looks reasonable.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 22:34:17 +0000 (17:34 -0500)]
pan/mdg: Fix shader-db counter
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Tue, 24 Nov 2020 18:57:12 +0000 (13:57 -0500)]
panfrost: Enable indirect uniform indexing
It works fine, and without it, the lowering bloats GLES2 shaders (by a
factor of 20x for one shader on t-rex!)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Alyssa Rosenzweig [Fri, 13 Nov 2020 21:59:16 +0000 (16:59 -0500)]
panfrost: Add PAN_GPU_ID debug option
I'd like to run shader-db locally without turning on the Bifrost
machine. I'm lazy, it's just for debug builds, ok? 😇
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Rhys Perry [Tue, 24 Nov 2020 14:53:04 +0000 (14:53 +0000)]
nir/unsigned_upper_bound: decrement num_sources_left before recursing
Otherwise, search_phi_bcsel() will be called with a buf_size that is
slightly lower than it has to be.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7748>
Rhys Perry [Tue, 24 Nov 2020 10:52:56 +0000 (10:52 +0000)]
nir/unsigned_upper_bound: fix buffer overflow in search_phi_bcsel
It should only recurse if there's enough space to add the phi sources.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
72ac3f60261 ("nir: add nir_unsigned_upper_bound and nir_addition_might_overflow")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7748>
Rhys Perry [Tue, 24 Nov 2020 20:40:56 +0000 (20:40 +0000)]
aco: fix v_mul_hi_u32_u24 format
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes:
57c152af9ce ("aco: select v_mul_{hi}_u32_u24 for 24-bit multiplications")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3874
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7759>
Erik Faye-Lund [Tue, 24 Nov 2020 22:35:08 +0000 (23:35 +0100)]
Revert "util: Add helpers for various one-time-init patters"
This reverts commit
bda4d6e0d01116db59a0a03b0c703a7af6e11949.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:59 +0000 (23:34 +0100)]
Revert "nir: Use get_once() helper for one-time init's"
This reverts commit
c9062df1d57df19a56288c1749d4b6d22d7c1418.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:51 +0000 (23:34 +0100)]
Revert "freedreno/ir3: Use get_once() for one-time init"
This reverts commit
b4ad27a986e1c6899cbf23355c3e9c6de345a323.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:46 +0000 (23:34 +0100)]
Revert "gallium/hud: Use do_once for one-time init"
This reverts commit
2e81ec5e009e3fbeef3fe1a76f2dfee428b7c160.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:39 +0000 (23:34 +0100)]
Revert "mesa/st: Use do_once for one-time init"
This reverts commit
bcb2981e145f0c2a54a637e20b6c55eaf316c04f.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:33 +0000 (23:34 +0100)]
Revert "util: Fix helgrind complaint about one-time init"
This reverts commit
f8c7a43f33d4647c16c4892d56706a14e5d6bf17.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:34:24 +0000 (23:34 +0100)]
Revert "mesa: Fix helgrind complaint about one-time init"
This reverts commit
f7102ac376a23a394786085a2b0dffa94c13150c.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:33:14 +0000 (23:33 +0100)]
Revert "gallium/trace: Fix helgrind complaint about one-time init"
This reverts commit
1aa055539f32fcb3c78d908d1635bb3a3d517bc2.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Erik Faye-Lund [Tue, 24 Nov 2020 22:33:06 +0000 (23:33 +0100)]
Revert "tgsi: Fix helgrind complaint about one-time init"
This reverts commit
d91fe7d1c65179e64a6ca294135ac1bad2b16fb9.
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7760>
Samuel Pitoiset [Mon, 23 Nov 2020 10:59:55 +0000 (11:59 +0100)]
radv: always use 32-bit predication on compute queues
It seems that only gfx queue doesn't support it, except on GFX10.3
which supports all queues.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
Samuel Pitoiset [Mon, 23 Nov 2020 10:57:49 +0000 (11:57 +0100)]
radv: use 32-bit predication for conditional rendering on GFX10.3+
It's now supported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
Samuel Pitoiset [Mon, 23 Nov 2020 10:51:25 +0000 (11:51 +0100)]
ac: add gpu_info::has_32bit_predication
32-bit predication is now supported with GFX10.3.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7732>
Ella-0 [Fri, 20 Nov 2020 08:57:07 +0000 (08:57 +0000)]
v3dv: Wayland WSI support
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7303>
Jason Ekstrand [Fri, 7 Aug 2020 03:17:17 +0000 (22:17 -0500)]
intel/rt: Implement push constants as global memory reads
They're not really "push" anymore but that's because there is no such
thing as push constants in bindless shaders on Intel. They should be
fast enough, though. There is some room for debate here as to whether
we want to do the pull in NIR or push it into the back-end. The
advantage of doing it in the back-end is that it'd be easier to use
MOV_INDIRECT for indirect push constant access rather than falling back
to a dataport message.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:42:14 +0000 (16:42 -0500)]
intel/rt: Add support for hit attributes
For triangle geometry, the hit attributes are always two floats which
contain the barycentric coordinates of the hit. For procedural
geometry, they're an arbitrary blob of data passed from the intersection
shader to the hit shaders. In our implementation, we stash that data
right after the HW RayQuery in the ray stack.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:31:05 +0000 (16:31 -0500)]
intel/rt: Add a helper to create the raygen trampoline shader
Unlike graphics and compute pipelines, Vulkan ray-tracing pipelines do
not have a single entrypoint. Instead, the raygen shader is specified
as a one-element shader binding table in the vkCmdTraceRay call. This
means that raygen shaders have to be bindless shaders just like any
other ray tracing shader. To launch them, we have a tiny compute shader
that acts as a trampoline and sets up the hotzone and uses btd_spawn to
fire off the raygen shader.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:22:15 +0000 (16:22 -0500)]
intel/rt: Add lowering for combined intersection/any-hit shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:09:55 +0000 (16:09 -0500)]
intel/rt: Add lowering for ray-walk intrinsics in any-hit shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 21:49:50 +0000 (16:49 -0500)]
intel/rt: Add support for shader buffer record memory
Most of the work for this is done for us by spirv_to_nir which gives us
a load_global from a memory address based on the shader_record_ptr
system values.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 20:59:30 +0000 (15:59 -0500)]
intel/rt: Implement the new ray-tracing system values
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 20:51:58 +0000 (15:51 -0500)]
intel/rt: Implement traceRay()
This is a little bit more work than executeCallable() because we also
have to set up the MemRay data structure which the ray traversal
hardware uses to keep its state.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 20:45:45 +0000 (15:45 -0500)]
intel/fs: Add and implement intel-specific ray-tracing intrinsics
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Fri, 4 Sep 2020 01:20:22 +0000 (20:20 -0500)]
intel/rt: Implement support for shader call payloads
Both traceRay() and executeCallable() take a payload parameter which
gets passed from the caller to the callee and which the callee can write
to pass data back to the caller. We implement these by passing a
pointer to the data structure in the callee to the caller as the second
QWord on its stack. Coming out of spirv_to_nir, the incoming call
payloads get the nir_var_shader_call_data variable mode allowing us to
easily identify them. Outgoing call payloads get assigned the
nir_var_shader_temp mode and will have been turned into function_temp by
nir_lower_global_vars_to_local. All we have to do is crawl the shader
looking for references to the nir_var_shader_call_data variable and
rewrite those to use the passed in pointer. nir_lower_explicit_io will
do the rest for us.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 20:16:26 +0000 (15:16 -0500)]
intel/rt: Add a helper to create a trivial return shader
These are required for ray-tracing. There are many cases where the
ray-tracing hardware may decide to execute some but not all of our
shaders. In these cases, it needs a shader to execute at the end which
will pop the stack back to the shader which called traceRay().
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 19:25:52 +0000 (14:25 -0500)]
intel/rt: Add a pass to lower shader call instructions
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 18:53:34 +0000 (13:53 -0500)]
intel/rt: Add return instructions at the end of ray-tracing shaders
Each callable ray-tracing shader shader stage has to perform a return
operation at the end. In the case of raygen shaders, it retires the
bindless thread because the raygen shader is always the root of the call
tree. In the case of any-hit shaders, the default action is accep the
hit. For callable, miss, and closest-hit shaders, it does a return
operation. The assumption is that the calling shader has placed a
BINDLESS_SHADER_RECORD address for the return in the first QWord of the
callee's scratch space. The return operation simply loads this value
and calls a btd_spawn intrinsic to jump to it.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 18:16:53 +0000 (13:16 -0500)]
intel/rt: Add support for scratch in ray-tracing shaders
In ray-tracing shader stages, we have a real call stack and so we can't
use the normal scratch mechanism. Instead, the invocation's stack lives
in a memory region of the RT scratch buffer that sits after the HW ray
stacks. We handle this by asking nir_lower_io to lower local variables
to 64-bit global memory access. Unlike nir_lower_io for 32-bit offset
scratch, when 64-bit global access is requested, nir_lower_io generates
an address calculation which starts from a load_scratch_base_ptr. We
then lower this intrinsic to the appropriate address calculation in
brw_nir_lower_rt_intrinsics.
When a COMPUTE_WALKER command is sent to the hardware with the BTD Mode
bit set to true, the hardware generates a set of stack IDs, one for each
invocation. These then get passed along from one shader invocation to
the next as we trace the ray. We can use those stack IDs to figure out
which stack our invocation needs to access. Because we may not be the
first shader in the stack, there's a per-stack offset that gets stored
in the "hotzone".
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 18:20:07 +0000 (13:20 -0500)]
intel/rt: Add lowering functions for each ray-tracing stage
These will eventually contain per-stage lowering for various ray-tracing
things. This is separate from brw_nir_lower_rt_intrinsics because, for
reasons that will become apparent later, brw_nir_lower_rt_intrinsics has
to be run very late in the compile process, right before brw_compile_bs.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 17:59:49 +0000 (12:59 -0500)]
intel/rt: Add a pass to lower the new ray-tracing intrinsics
The new intrinsics we added for doing address calculations are all
things we fetch from the RT_DISPATCH_GLOBALS struct. We could emit an
RT_DISPATCH_GLOBALS load at every point we want it and trust NIR to CSE
it for us but it's easier to use intermediate intrinsics.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 17:44:57 +0000 (12:44 -0500)]
intel/rt: Add builder helpers for accessing RT data structures
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 17 Jun 2020 04:05:16 +0000 (23:05 -0500)]
intel/fs: Add and implement a load_global_const_block intrinsic
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Thu, 6 Aug 2020 17:53:47 +0000 (12:53 -0500)]
intel/rt: Add a brw_rt.h header with #defines for basic RT data structures
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 21 Oct 2020 19:46:50 +0000 (14:46 -0500)]
intel/compiler: Add support for bindless shaders
The Intel bindless thread dispatch model is very simple. When a compute
shader is to be used for bindless dispatch, it can request a set of
stack IDs. These are allocated per-dual-subslice by the hardware and
recycled automatically when the stack ID is returned. Passed to the
bindless dispatch are a global argument address, a stack ID, and an
address of the BINDLESS_SHADER_RECORD to invoke. When the bindless
shader is dispatched, it is passed its stack ID as well as the global
and local argument pointers. The local argument pointer is the address
of the BINDLESS_SHADER_RECORD plus some offset which is specified as
part of the BINDLESS_SHADER_RECORD.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 21 Oct 2020 19:46:39 +0000 (14:46 -0500)]
intel/debug: Add a debug flag for ray-tracing shaders
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 5 Aug 2020 00:24:24 +0000 (19:24 -0500)]
nir/lower_io: Support shader_call_data in vars_to_explicit_types
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Tue, 28 Jul 2020 23:01:41 +0000 (18:01 -0500)]
nir/lower_io: Allow ray_hit_attrib in lower_vars_to_explicit_types
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Fri, 15 May 2020 17:07:22 +0000 (12:07 -0500)]
nir: Add a helper to get the live set at a cursor
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 21 Oct 2020 19:32:10 +0000 (14:32 -0500)]
intel/genxml: Add BVH data structures
These describe the Intel BVH format used for storing acceleration
structures.
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 21 Oct 2020 20:02:57 +0000 (15:02 -0500)]
intel/genxml: Add RT_DISPATCH_GLOBALS and RT_*_SBT_HANDLE structs
The RT_DISPATCH_GLOBALS struct is half HW-defined by the ray-tracing
spec and half SW-defined. However, due to the addresses in it, it's
convenient for it to all be in GenXML.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Fri, 12 Jun 2020 21:31:34 +0000 (16:31 -0500)]
intel/genxml: Support truncated addresses
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Fri, 12 Jun 2020 21:32:11 +0000 (16:32 -0500)]
intel/genxml/pack: Stash the cloned address field
The cloned version is the one that has updated start and end bits
fields. We're about to start passing those through to a new
__gen_address function and we need the correct start/end in order to do
that reliably.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 21 Oct 2020 19:32:10 +0000 (14:32 -0500)]
intel/genxml: Add the BINDLESS_SHADER_RECORD data structure
This is the first of the HW data structures added for ray-tracing.
These are added to their own file because it's not really associated
with any hardware we've enabled in Mesa just yet. Eventually, these
will likely get folded into the appropriate genX.xml file as they are
hardware data structures and needed to be tracked as such.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Wed, 21 Oct 2020 20:04:11 +0000 (15:04 -0500)]
intel/dev: Add a gen_device_info::has_ray_tracing bit
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Tue, 24 Nov 2020 04:54:01 +0000 (22:54 -0600)]
spirv: Emit nir_jump_halt after TerminateRay or IgnoreIntersection
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Jason Ekstrand [Fri, 15 May 2020 20:46:08 +0000 (15:46 -0500)]
nir: Add a halt instruction type
Halt is like a return for the entire shader or exit() if you prefer to
think of it that way. Once an invocation hits a halt, it's 100% dead.
Any writes to output variables which happened before the halt do,
however, still apply.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7356>
Mark Janes [Wed, 25 Nov 2020 01:31:59 +0000 (17:31 -0800)]
meson: add idep_mesautil to components using simple_mtx.h
If valgrind is installed, these components need to find valgrind.h.
Fixes:
53f7d539cd9 ("util: Add helgrind support for simple_mtx")
Closes: #3876
Acked-by: Rob Clark <robclark@freedesktop.org>
Erik Faye-Lund [Tue, 24 Nov 2020 17:20:56 +0000 (18:20 +0100)]
Revert "zink: initial implementation of shader keys"
This reverts commit
2be2a500a396fe1dc0e121816e4056874cdd43fc.
Fixes:
2be2a500a39 ("zink: initial implementation of shader keys")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7754>
Erik Faye-Lund [Tue, 24 Nov 2020 17:20:49 +0000 (18:20 +0100)]
Revert "zink: refcount the shader cache"
This reverts commit
b9fdc21bba0724271520462f3f04ba72ae106a26.
Fixes:
b9fdc21bba0 ("zink: refcount the shader cache")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7754>