Timothy Arceri [Wed, 9 Nov 2016 03:00:22 +0000 (14:00 +1100)]
st/mesa: pass gl_program to st_bind_ubos()
We no longer need anything from gl_linked_shader.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Wed, 9 Nov 2016 02:41:50 +0000 (13:41 +1100)]
st/mesa: pass gl_program to st_bind_images()
We no longer need anything from gl_linked_shader.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 9 Nov 2016 02:37:39 +0000 (13:37 +1100)]
st/mesa: stop passing gl_linked_shader to set_affected_state_flags()
We now get everything we need from the gl_program param.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 9 Nov 2016 02:35:11 +0000 (13:35 +1100)]
st/mesa/glsl: set num_images directly in shader_info
This change also removes the now duplicate NumImages field.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 9 Nov 2016 00:57:33 +0000 (11:57 +1100)]
st/mesa: pass gl_program to st_bind_ssbos()
We no longer need to pass gl_shader_program.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 4 Jan 2017 05:21:34 +0000 (16:21 +1100)]
nir: add another comparison simplification
On BDW:
total instructions in shared programs:
13061877 ->
13060965 (-0.01%)
instructions in affected programs: 133569 -> 132657 (-0.68%)
helped: 566
HURT: 0
total cycles in shared programs:
256611784 ->
256599536 (-0.00%)
cycles in affected programs: 861016 -> 848768 (-1.42%)
helped: 379
HURT: 73
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 9 Aug 2016 08:44:38 +0000 (01:44 -0700)]
nir: Turn bcsel of +/- 1.0 and 0.0 into b2f sequences.
On BDW:
total instructions in shared programs:
13074882 ->
13068703 (-0.05%)
instructions in affected programs: 1823116 -> 1816937 (-0.34%)
helped: 4187
HURT: 537
total cycles in shared programs:
256622718 ->
256425382 (-0.08%)
cycles in affected programs:
123790120 ->
123592784 (-0.16%)
helped: 3823
HURT: 2037
total spills in shared programs: 15276 -> 14929 (-2.27%)
spills in affected programs: 9446 -> 9099 (-3.67%)
helped: 352
HURT: 1
total fills in shared programs: 20496 -> 20144 (-1.72%)
fills in affected programs: 13040 -> 12688 (-2.70%)
helped: 352
HURT: 1
LOST: 2
GAINED: 21
v2: Rely on 'a' being a well-formed boolean (Connor, Eric).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 9 Aug 2016 00:05:18 +0000 (17:05 -0700)]
nir: Convert ineg(b2i(a)) to a if it's a boolean.
On BDW:
total instructions in shared programs:
13071119 ->
13070371 (-0.01%)
instructions in affected programs: 83424 -> 82676 (-0.90%)
helped: 505
HURT: 45 (all TCS, all hurt by a single instruction)
total cycles in shared programs:
256601322 ->
256588932 (-0.00%)
cycles in affected programs: 819410 -> 807020 (-1.51%)
helped: 450
HURT: 57
total loops in shared programs: 2950 -> 2942 (-0.27%)
loops in affected programs: 8 -> 0
helped: 7
HURT: 0
v2: Drop unnecessary 'a@bool' annotation (Connor, Eric).
Add a comment explaining the rule (Ian).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 7 Mar 2016 23:46:47 +0000 (15:46 -0800)]
i965: Move TES input VUE map calculation out a layer.
In Vulkan, we'll compile the TCS and TES at the same time, so I can just
pass the TCS output VUE map to brw_compile_tes as the TES input VUE map.
So, we only need to do this in GL. Move it to the GL-specific layer.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Thu, 25 Feb 2016 19:55:23 +0000 (11:55 -0800)]
i965: Pass NULL for gl_program when compiling TES.
This isn't needed, and Vulkan doesn't have one.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Mon, 26 Sep 2016 00:59:42 +0000 (17:59 -0700)]
i965: Move TES spacing/domain/topology setup to brw_compile_tes().
Moving this down a layer lets us share code between Vulkan and GL.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 15 Nov 2016 06:17:44 +0000 (22:17 -0800)]
i965: Access TES shader info via NIR.
NIR exists in both GL and Vulkan, but gl_program is GL specific.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Sun, 25 Sep 2016 00:59:55 +0000 (17:59 -0700)]
mesa: Introduce a compiler enum for tessellation spacing.
It feels weird using GL_* enums in a Vulkan driver.
v2: Fix the TESS_SPACING -> PIPE_TESS_SPACING conversion.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 22 Nov 2016 22:43:57 +0000 (14:43 -0800)]
compiler: Change shader_info->tes.vertex_order into a ccw boolean.
The vertex order is either clockwise or counterclockwise. We can just
store a "ccw" boolean rather than GLenum values. I don't want to use
GLenums in a Vulkan driver, and even in GL a simple boolean works fine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Sat, 7 Jan 2017 01:22:56 +0000 (17:22 -0800)]
anv/pipeline: Call NIR passes using NIR_PASS_V
This lets us get validation without having to do it manually.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Sat, 7 Jan 2017 01:25:35 +0000 (17:25 -0800)]
anv/pipeline: Only call remove_dead_variables once
It can handle multiple modes at a time now so there's no reason to call
it repeatedly.
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Sat, 7 Jan 2017 21:58:42 +0000 (13:58 -0800)]
Revert recent GLSL slot counting fiasco.
I apparently broke mark_whole_variable in ir_set_program_inouts.
It was passing a type that wasn't var->type, so the wrapper didn't
work out. It's all broken, revert it and start over.
Fixes all kinds of things on other drivers.
Revert "glsl: Make is_fixed_function_array actually check for varyings."
This reverts commit
42699e12711668a142b7acf11c168cf4301c1295.
Revert "glsl: Mark whole variable used for ClipDistance and TessLevel*."
This reverts commit
5c580e64cc206ab160e1767c42e4d6c81f67da4d.
Revert "glsl: Override the # of varying slots for ClipDistance and TessLevel*."
This reverts commit
8b5749f65ac434961308ccb579fb8a816e4f29d5.
Revert "glsl: Create and use a new ir_variable::count_attribute_slots() wrapper."
This reverts commit
6aa5cb34d03765b7be8611aa516bc201bd337f73.
Kenneth Graunke [Sat, 7 Jan 2017 20:55:17 +0000 (12:55 -0800)]
glsl: Make is_fixed_function_array actually check for varyings.
We can't check VARYING_SLOT_* locations until we've determined that
the variable is actually a varying.
Fixes assert failures in drivers which actually use this path,
such as radeonsi and i915.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99314
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kai Wasserbäch [Sat, 7 Jan 2017 13:38:23 +0000 (14:38 +0100)]
drirc: Allow extension midshader for Divinity: Original Sin (EE)
See also <https://bugs.freedesktop.org/show_bug.cgi?id=93551#c27> where
this was first observed as a requirement.
Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Thu, 5 Jan 2017 23:26:24 +0000 (10:26 +1100)]
glsl: fix opt_minmax redundancy checks against baserange
Marking operations as redundant if they are equal to the base
range is fine when the tree structure is something like this:
max
/ \
max b
/ \
3 max
/ \
3 a
But the opt falls apart with a tree like this:
max
/ \
max max
/ \ / \
3 a b 3
The problem is that both branches are treated the same: descending in
the left branch will prune the constant, and then descending the right
branch will prune the constant there as well, because limits[0] wasn't
updated to take the change on the left branch into account, and so we
still get [3,\infty) as baserange.
In order to fix the bug we just disable the marking of redundant expressions
when they match the baserange.
NIR algebraic opt will clean up the first tree for anyway, hopefully
other backends are smart enough to do this also.
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Sat, 10 Dec 2016 06:32:08 +0000 (22:32 -0800)]
i965/compiler: Use the new nir_opt_copy_prop_vars pass
We run this after nir_lower_vars_to_ssa so that as many load/store_var
intrinsics as possible before copy_prop_vars executes. This is because the
pass isn't particularly efficient (it does a lot of linear walks of a
linked list) so we'd like as much of the work as possible to be done before
copy_prop_vars runs.
Shader DB results on Sky Lake:
total instructions in shared programs:
12020290 ->
12013627 (-0.06%)
instructions in affected programs: 26033 -> 19370 (-25.59%)
helped: 16
HURT: 13
total cycles in shared programs:
137772848 ->
137549012 (-0.16%)
cycles in affected programs: 6955660 -> 6731824 (-3.22%)
helped: 217
HURT: 237
total loops in shared programs: 3208 -> 3208 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0
total spills in shared programs: 4112 -> 4057 (-1.34%)
spills in affected programs: 483 -> 428 (-11.39%)
helped: 2
HURT: 0
total fills in shared programs: 5519 -> 5102 (-7.56%)
fills in affected programs: 993 -> 576 (-41.99%)
helped: 2
HURT: 0
LOST: 0
GAINED: 0
Broadwell had similar results. On older hardware, the impact isn't as
large because they don't advertise GL 4.5. Of the hurt programs, all but
one are hurt by a single instruction and the one is hurt by 3 instructions.
All of the helped programs, on the other hand, are helped by at least 3
instructions and one kerbal space program shader is helped by 44.59%.
The real star of the show, however, is the Gl43CSDof synmark2 benchmark
which has two shaders which are cut by 28% and 40% and the over-all runtime
performance of the benchmark on my Sky Lake laptop is improved by around
25-30% (it's a bit hard to be exact due to thermal throttling).
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Sat, 10 Dec 2016 06:31:26 +0000 (22:31 -0800)]
nir: Add a local variable-based copy propagation pass
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Sat, 10 Dec 2016 20:00:12 +0000 (12:00 -0800)]
nir/builder: Add a helper for getting the most recently added instruction
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Sat, 10 Dec 2016 19:32:29 +0000 (11:32 -0800)]
nir/builder: Add a load_deref_var helper
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Sat, 10 Dec 2016 03:37:12 +0000 (19:37 -0800)]
nir/dead_variables: Remove shader-local variables that are only written
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Fri, 6 Jan 2017 23:33:35 +0000 (15:33 -0800)]
nir/dead_variables: Removed shared variables when requested
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Fri, 6 Jan 2017 20:50:47 +0000 (12:50 -0800)]
anv/formats: Use the real format for B4G4R4A4_UNORM_PACK16 on gen8
Because border color is handled pre-swizzle, when we move the alpha
channel around in the format, the OPAQUE_BLACK border colors don't work
correctly on B4G4R4A4_UNORM_PACK16 with the hack. This fixes the
following Vulkan CTS tests on Broadwell:
dEQP-VK.pipeline.sampler.view_type.2d_array.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.1d_array.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.2d.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.1d.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
dEQP-VK.pipeline.sampler.view_type.3d.format.b4g4r4a4_unorm_pack16.address_modes.all_mode_clamp_to_border_opaque_black
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 6 Jan 2017 20:20:14 +0000 (12:20 -0800)]
isl: Mark A4B4G4R4_UNORM as supported on gen8
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
Pierre-Loup A. Griffais [Fri, 6 Jan 2017 20:57:17 +0000 (12:57 -0800)]
radv: fix depth transitions with layerCount = VK_REMAINING_ARRAY_LAYERS
Interpreting layerCount literally would try to create billions of image
views in radv_process_depth_image_inplace().
Signed-off-by: Pierre-Loup A. Griffais <pgriffais@valvesoftware.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Thu, 24 Nov 2016 09:50:10 +0000 (01:50 -0800)]
i965: Rework gl_TessLevel*[] handling to use NIR compact arrays.
Treating everything as scalar arrays allows us to drop a bunch of
special case input/output munging all throughout the backend.
Instead, we just need to remap the TessLevel components to the
appropriate patch URB header locations in remap_patch_urb_offsets().
We also switch to treating the TES input versions of these as ordinary
shader inputs rather than system values, as remap_patch_urb_offsets()
just makes everything work out without special handling.
This regresses one Piglit test:
arb_tessellation_shader-large-uniforms/GL_TESS_CONTROL_SHADER-array-at-limit
The compiler starts promoting the constant arrays assigned to gl_TessLevel*
to uniform arrays. Since the shader also has a uniform array that uses
the maximum number of uniform components, this puts it over the uniform
component limit enforced by the linker. This is arguably a bug in the
constant array promotion code (it should avoid pushing us over limits),
but is unlikely to penalize any real application.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 14 Dec 2016 03:50:25 +0000 (19:50 -0800)]
i965: Inline store_output helper in quads workaround code.
It's only used in one place, it ignores the offset parameter currently,
and I want to add more parameters...at which point, passing in a bunch
of integers seems less obvious than writing it out.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 6 Dec 2016 07:09:18 +0000 (23:09 -0800)]
nir: Make glsl_to_nir compact scalar TessLevel arrays.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 6 Dec 2016 10:45:52 +0000 (02:45 -0800)]
i965: Make unify_interfaces not spread VARYING_BIT_TESS_LEVEL_*.
This is harmless today because gl_TessLevelInner/Outer in the TES is
currently treated as system values. However, when we move to treating
them as inputs, this would cause a bug: with no TCS present, it would
propagate TES reads of VARYING_SLOT_TESS_LEVEL into the VS output VUE
map slots. This is totally bogus - those don't even exist in the VS.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Tue, 6 Dec 2016 09:50:03 +0000 (01:50 -0800)]
glsl: Support gl_TessLevelInner/Outer[] as TES input variables.
Upcoming reworks in i965 are going to make it easy to handle this
like any other input. Having it as a system value will just require
additional code for no benefit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Sun, 15 Nov 2015 12:22:10 +0000 (04:22 -0800)]
glsl: Mark whole variable used for ClipDistance and TessLevel*.
There's no point in trying to mark partial array access for
gl_ClipDistance, gl_TessLevelOuter, or gl_TessLevelInner - they're
special built-in variables that control fixed function hardware,
and will likely be used in an all-or-nothing fashion.
Since these arrays only occupy 1-2 varying slots, we have to avoid
our normal processing which increments the slot value by the array
index.
(I wrote this code before i965 switched from ir_set_program_inouts
to nir_shader_gather_info. It's not used by anyone today, and I'm
not sure how valuable it is...the alternative to GLSL IR lowering
is NIR compact arrays, at which point you should use nir_gather_info.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Sun, 15 Nov 2015 12:37:50 +0000 (04:37 -0800)]
glsl: Override the # of varying slots for ClipDistance and TessLevel*.
Right now, this shouldn't have any effect, as all drivers use
LowerClipDist and LowerTessFactors to turn the float[] arrays into
vectors.
However, it should help make it possible for drivers to avoid that
lowering.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Sun, 15 Nov 2015 12:32:52 +0000 (04:32 -0800)]
glsl: Create and use a new ir_variable::count_attribute_slots() wrapper.
This wraps glsl_type::count_attribute_slots(), but will soon contain a
couple of overrides for a couple of GLSL built-ins variables.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Marek Olšák [Fri, 6 Jan 2017 21:01:46 +0000 (22:01 +0100)]
gallium/radeon: use the internal clear_buffer callback to fix r600g
r600g doesn't set pipe_context::clear_buffer.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99303
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Roland Scheidegger [Thu, 22 Dec 2016 02:55:17 +0000 (03:55 +0100)]
llvmpipe: do transpose/untwiddle after conversion for 8bit formats
Generally we should do tranpose after conversion, if the format has less than
32 bits per channel (if it has 32 bits, conversion is going to be a no-op
anyway...). This is obviously because there's less vectors to deal with.
Though the advantage for 16 bit formats isn't that big, and in fact with AVX
there isn't really any (as the 32bit unpacks can be done with 256bit, but
the smaller ones cannot, although that would change again with proper AVX2
support).
Only makes sense for 2d and not 1d cases. And to keep things easy, only handle
1,2 and 4 channels (rgbx is just fine).
For rgba unorm8 format the backend conversion sums up to these instruction
totals (not counting the movs for SSE2 due to 2-op syntax - generally every 2
unpacks need an additional mov).
SSE2 AVX
transpose: 32 unpack 16 unpack
untwiddle: 0 8 (128bit low/high permutes)
convert: 16 mul + 16 cvt 8 mul + 8 cvt
32->8bit: 12 pack 8 (128bit extract) + 12 pack
When doing transpose/untwiddle afterwards we get:
convert: 16 mul + 16 cvt 8 mul + 8 cvt
32->8bit: 12 pack 8 (128bit extract) + 12 pack
transpose/untwiddle 12 unpack 12 unpack
So for SSE2, this drops 20 unpacks (total instruction count 76->56)
whereas for AVX it replaces the 16 256bit unpacks with 8 128bit ones
and drops the 8 lo/hi permutes (in total 60->48). (Albeit to be fair,
the permutes could be dropped even when doing the transpose first,
they are extremely pointless but we'd need to be able to tell
lp_build_conv to reorder the vectors, for AVX2 we're going to need to
be able to tell lp_build_conv about ordering in any case.)
(With different ordering going into conversion, it would be possible
to do 4 unpacks + 4 pshufbs instead of 12 unpacks, but that might not
be better, and not all cpus can do it. Proper AVX2 support should eliminate
the 8 128bit extracts, reduce these 12 packs to 6 and the 12 unpacks to 2
pshufb + 2 permq ideally (+ 2 final 128bit extracts).)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 22 Dec 2016 02:51:40 +0000 (03:51 +0100)]
gallivm: generalize 4x4f->1x16ub special case conversion
This special packing path can be easily extended to handle not just
float->unorm8 but also float->snorm8 and uint32->uint8 and int32->int8
(i.e. all interesting cases for llvmpipe fs backend code).
The packing parts all stay the same (only the last step packing will
be signed->signed instead of signed->unsigned but luckily even sse2 can do
both).
While here also note some bugs with that (we keep the bugs identical to
what we did before on x86, albeit other archs may differ). In particular
float->unorm8 too large values will still get clamped to 0, not 255, and for
float->snorm8 NaNs will end up as -1, not 0 (but we do the clamp against 1.0
there to prevent too large values ending up as -1.0 - this is inconsistent
to unorm8 handling but is what we ended up before, I'm not sure we can get
away without it). This is quite fishy in any case as we depend on
arch-dependent behavior of the iround (my understanding is in fact with
altivec the conversion would actually saturate although I've no idea about
NaNs, so probably wouldn't need to do anything for snorm).
(There are only minimal piglit tests for unorm clamping behavior AFAICT, in
particular nothing seems to test values which are too large to be handled by
the float->int conversion.)
For uint32->uint8 we also do a min against MAX_INT, since the source for
the packs is always signed (again, on x86 - should probably be able to
express these arch-dependent bits better some day).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 22 Dec 2016 02:49:22 +0000 (03:49 +0100)]
llvmpipe: use alpha from already converted color if possible
For rgbx formats, there is no point in doing alpha conversion again (and
with different tranpose even, so llvm can't eliminate it).
Albeit it looks like there's some minimal changes needed in the blend code
(found by code inspection, no test seemed to complain) if we do this -
the blend factors are already sanitized if we have no destination alpha,
however for src_alpha_saturate it looks like it still might make a
difference (note that we forced has_alpha to true before for some formats
and nothing complained, but this seems safer).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Thu, 22 Dec 2016 02:48:05 +0000 (03:48 +0100)]
llvmpipe: use scalar load instead of vectors for small vectors in fs backend
llvm has _huge_ problems trying to load things like <4 x i8> vectors and
stitching such loads together to form 128bit vectors. My understanding
of the problem is that the type legalizer tries to extend that to
really a <4 x i32> vector and not a <16 x i8> vector with the 4 elements
first then followed by padding, so the shuffles for then combining things
together are more or less impossible - you can in fact see the pmovzxd
llvm generates. Pre-4.0 llvm just gives up on it completely and does a 30+
pextrb/pinsrb sequence instead.
It looks like current llvm has fixed this behavior (my guess would be
due to better shuffle combination and load/shuffle folds), but we can
avoid this by just loading as <1 x i32> values, combine that and only
cast at the end. (I suspect it might also work if we'd pad the loaded
vectors immediately before shuffling them together, instead of directly
stitching 2 such vectors together pairwise before combining the pair.
But this _might_ lose the ability to load the values directly into
their right place in the vector with pinsrd.). But using 32bit values
is probably easier for llvm as it will never give it funny ideas how
the vector should look like.
(This is possibly only a problem for 1x8bit formats, since 2x8bit will
end up fetching 64bit hence only two vectors are stitched together,
not 4, but we use the same strategy anyway.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Ian Romanick [Tue, 8 Nov 2016 18:10:35 +0000 (10:10 -0800)]
i965: Enable several GLES 3.1 extensions on HSW+
The only reason we didn't previously enable this was the dependency on
OpenGL ES 3.1. These should have been enabled as soon as HSW got
stencil texturing. We also needed to fixup setting MaxViewports.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 8 Nov 2016 18:10:34 +0000 (10:10 -0800)]
i965: Always set MaxViewports and related limits
Since
9d6ca7c3, there should be no performance hit for having
MaxViewports > 1. Always set this context state. This eliminates the
need to update this conditional as we add support for OES_viewport_array
on older GPUs.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Thu, 29 Dec 2016 12:41:42 +0000 (13:41 +0100)]
winsys/amdgpu: fix a race condition between fence updates and IB submissions
The CS thread is needed to ensure proper ordering of operations and can't
be disabled (without complicating the code).
Discovered by Nine CSMT, which ended up in a deadlock.
Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 25 Dec 2016 17:11:59 +0000 (18:11 +0100)]
radeonsi: add TC L2 prefetch for shaders and VBO descriptors
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 13 Oct 2016 10:09:36 +0000 (12:09 +0200)]
radeonsi: add CP DMA flags for greater control over synchronization
for L2 prefetch
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 13 Oct 2016 09:40:09 +0000 (11:40 +0200)]
radeonsi: cleanly communicate which CP DMA packet is first
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 27 Dec 2016 17:35:32 +0000 (18:35 +0100)]
gallium/radeon: add new HUD query num-SDMA-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 27 Dec 2016 16:54:18 +0000 (17:54 +0100)]
gallium/radeon: rename the num-ctx-flushes query to num-GFX-IBs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 25 Dec 2016 18:48:55 +0000 (19:48 +0100)]
radeonsi: add HUD queries for cache flush stats
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 25 Dec 2016 17:34:16 +0000 (18:34 +0100)]
radeonsi: don't count fast clears and prefetches into CP DMA stats
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 26 Dec 2016 21:33:46 +0000 (22:33 +0100)]
radeonsi: don't wait for compute shaders in texture_barrier
it doesn't interact with compute shaders in any way
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 21 Dec 2016 14:16:54 +0000 (15:16 +0100)]
radeonsi: assume that a TES without POSITION precedes GS
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 21 Dec 2016 14:15:30 +0000 (15:15 +0100)]
radeonsi: unduplicate VS color export code
it's exactly the same as the other ones
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 13 Dec 2016 17:42:08 +0000 (18:42 +0100)]
radeonsi: clean up more HAVE_LLVM #ifdefs
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 13 Dec 2016 17:37:08 +0000 (18:37 +0100)]
gallium/radeon: clean up HAVE_LLVM #ifdefs in r600_get_llvm_processor_name
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kenneth Graunke [Fri, 6 Jan 2017 08:09:53 +0000 (00:09 -0800)]
i965: Properly flush in hsw_pause_transform_feedback().
Fixes a number of transform feedback tests when run with Linux 4.8,
which allows us to use the MI_LOAD_REGISTER_REG command, at which point
we started using this new broken path.
ES3-CTS.functional.transform_feedback.array_element.interleaved.lines.*
and Piglit's arb_transform_feedback2/draw-auto are both fixed by this
patch, for example.
Thanks to Chris Wilson for catching this mistake!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99030
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Fri, 6 Jan 2017 09:13:24 +0000 (01:13 -0800)]
i965: Fix texturing in the vec4 TCS and GS backends.
We were failing to zero m0.2 of the sampler message header for TCS and
GS messages in the simple case. fs_generator has done this for about
a year now, but we missed it in vec4_generator.
Fixes ES31-CTS.core.texture_cube_map_array.sampling,
GL45-CTS.texture_cube_map_array.sampling, and many
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler subtests:
- dynamically_uniform.tessellation_control.isampler3d
- dynamically_uniform.tessellation_control.isamplercube
- dynamically_uniform.tessellation_control.sampler2d
- dynamically_uniform.tessellation_control.usamplercube
- dynamically_uniform.tessellation_control.sampler2darray
- dynamically_uniform.tessellation_control.isampler2darray
- dynamically_uniform.tessellation_control.usampler3d
- dynamically_uniform.tessellation_control.usampler2darray
- dynamically_uniform.tessellation_control.usampler2d
- dynamically_uniform.tessellation_control.sampler3d
- dynamically_uniform.tessellation_control.samplercube
- dynamically_uniform.tessellation_control.isampler2d
- uniform.tessellation_control.isampler3d
- uniform.tessellation_control.isamplercube
- uniform.tessellation_control.usampler2d
- uniform.tessellation_control.usampler3d
- uniform.tessellation_control.sampler2darray
- uniform.tessellation_control.isampler2darray
- uniform.tessellation_control.usampler2darray
- uniform.tessellation_control.sampler2d
- uniform.tessellation_control.usamplercube
- uniform.tessellation_control.sampler3d
- uniform.tessellation_control.samplercube
- uniform.tessellation_control.isampler2d
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tim Rowley [Wed, 4 Jan 2017 22:54:00 +0000 (16:54 -0600)]
swr: [rasterizer core] rename OutputMerger functions
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 22 Dec 2016 00:06:42 +0000 (18:06 -0600)]
swr: [rasterizer core] fix SIMD16 Transpose_16_16
Fix incorrect swizzling in SIMD16 Transpose_16_16 breaking the
two-channel 16-bpc formats like R16G16_FLOAT.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Thu, 22 Dec 2016 00:01:56 +0000 (18:01 -0600)]
swr: [rasterizer core] fix SIMD16 output merger
Honor the colorHottileEnable mask when accessing colorBuffer pointers.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 21 Dec 2016 23:59:44 +0000 (17:59 -0600)]
swr: [rasterizer core] fix SIMD16 PackTraits pack() and unpack()
Fix routines for 8-bit and 16-bit formats used by optimized tile store.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 19 Dec 2016 21:25:52 +0000 (15:25 -0600)]
swr: [rasterizer core] fix SIMD16 transpose functions
Fixed Transpose_16 methods of following formats:
Transpose8_8_8_8
Transpose8_8
Transpose32_32
Transpose16_16_16_16
Transpose16_16_16
Transpose16_16
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Wed, 14 Dec 2016 01:01:08 +0000 (19:01 -0600)]
swr: [rasterizer core] whitespace adjustments
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Kenneth Graunke [Thu, 5 Jan 2017 18:46:39 +0000 (10:46 -0800)]
i965: Don't set EmitNoMainReturn.
A while ago, we stopped using Luca's GLSL IR lower_jumps pass in favor
of nir_lower_returns(). Marek's commit
d3cb79e043338b0e55a3fba8df652f3
put it in do_common_optimization, which resulted in us calling it again.
Dropping the EmitNoMainReturn setting makes us skip that pass again.
Apparently that pass doesn't work properly, because this fixes Piglit's
tests/spec/glsl-1.10/execution/vs-nested-return-sibling-loop.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99287
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Eric Anholt [Thu, 5 Jan 2017 23:37:14 +0000 (15:37 -0800)]
vc4: Rewrite T image handling based on calling the LT handler.
The T images are composed of effectively swizzled-around blocks of LT (4x4
utile) images, so we can reduce the t_utile_address() calls by 16x by
calling into the simpler LT loop.
This also adds support for calling down with non-utile-aligned
coordinates, which will be part of lifting the utile alignment requirement
on our callers and avoiding the RMW on non-utile-aligned stores.
Improves 1024x1024 TexSubImage by 2.55014% +/- 1.18584% (n=46)
Improves 1024x1024 GetTexImage by 2.242% +/- 0.880954% (n=32)
Eric Anholt [Thu, 5 Jan 2017 23:23:32 +0000 (15:23 -0800)]
vc4: Move the utile_width/height functions to header inlines.
I want these inlined in the callers, particularly with the tiling
changes coming up, but we're not building with lto so some caller
would suffer.
Eric Anholt [Thu, 5 Jan 2017 20:15:30 +0000 (12:15 -0800)]
vc4: Make the load/store utile functions static.
They don't have any other callers outside of this file, and I'm hoping
they get inlined soon.
Eric Anholt [Wed, 4 Jan 2017 20:40:37 +0000 (12:40 -0800)]
vc4: Simplify the load/store utile functions.
They now have less of a dependency on the cpp, and don't have to do a
divide.
Hacking up mesa-demos teximage to do only one subtest and not draw
points, I saw 1024x1024 glTexSubImage2D() improve by 4.86939% +/-
1.40408% (n=30) and glGetTexImage() by 2.18978% +/- 0.140268% (n=5).
Eric Anholt [Wed, 4 Jan 2017 19:57:30 +0000 (11:57 -0800)]
vc4: Reuse a list function to simplify bufmgr code.
Eric Anholt [Wed, 4 Jan 2017 19:24:31 +0000 (11:24 -0800)]
vc4: Flush the job early if we're referencing too many BOs.
If we get up toward 256MB (or whatever the CMA area size is),
VC4_GEM_CREATE will start throwing errors. Even if we don't trigger
that, when we flush the kernel's BO allocation for the CLs or bin
memory may end up throwing an error, at which point our job won't get
rendered at all.
Just flush early (half of maximum CMA size) so that hopefully we never
get to that point.
Timothy Arceri [Tue, 8 Nov 2016 22:49:59 +0000 (09:49 +1100)]
st/mesa/glsl: move SamplerTargets to gl_program
This will help allow us to simplify the handling of samplers by
storing them in a single location rather than duplicating them in
both gl_linked_shader and gl_program.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Tue, 8 Nov 2016 23:00:09 +0000 (10:00 +1100)]
st/mesa/glsl: set SamplersUsed directly in gl_program
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 4 Nov 2016 06:05:22 +0000 (17:05 +1100)]
mesa/glsl: set sampler units directly in gl_program
Now that we create gl_program earlier there is no need to mess about
copying things to gl_linked_shader then to gl_program.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 4 Nov 2016 05:41:30 +0000 (16:41 +1100)]
mesa: simplify sampler setting code
There is no need to loop over active samplers the code above this
would have already exited if the sampler was inactive, or errored
if the count was larger than the uniforms array size.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 4 Nov 2016 00:40:10 +0000 (11:40 +1100)]
mesa/glsl: set num_textures per stage directly in shader_info
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Thu, 3 Nov 2016 22:25:36 +0000 (09:25 +1100)]
mesa: make _CurrentFragmentProgram a gl_program struct pointer
Making this point to a gl_program struct rather than a gl_shader_program
struct will allow use to later also make the CurrentProgram array hold
gl_program structs which in turn will allow for code simpilifcation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Fri, 4 Nov 2016 05:04:01 +0000 (16:04 +1100)]
i965: stop passing gl_shader_program to the precompile and codegen functions
We no longer need it.
While we are at it we mark the vs, gs, and wm codegen functions as static.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Wed, 9 Nov 2016 12:50:07 +0000 (23:50 +1100)]
mesa/glsl: remove hack to reset sampler units to zero
Now that we have the is_arb_asm flag we can just skip the
initialisation.
V2: remove hack from standalone compiler where it was never
needed since it only compiles glsl shaders.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Wed, 9 Nov 2016 12:44:39 +0000 (23:44 +1100)]
i965: make use of new is_arb_asm flag
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Wed, 9 Nov 2016 12:38:46 +0000 (23:38 +1100)]
st/mesa/glsl: add new is_arb_asm flag in gl_program
Set the flag via the _mesa_init_gl_program() and NewProgram()
helpers.
In i965 we currently check for the existance of gl_shader_program
to decide if this is an ARB assembly style program or not.
Adding a flag makes the code clearer and will help removes a
dependency on gl_shader_program in the i965 codegen functions.
Also this will allow use to skip initialising sampler units for
linked shaders, we currently memset it to zero again during linking.
Reviewed-by: Eric Anholt <eric@anholt.net>
Timothy Arceri [Tue, 8 Nov 2016 01:07:12 +0000 (12:07 +1100)]
i965: pass gl_program directly to brw_compile_tes()
This is the only thing we use from gl_shader_program so pass it directly.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Mon, 7 Nov 2016 09:54:45 +0000 (20:54 +1100)]
i965: stop passing gl_shader_program to brw_nir_setup_glsl_uniforms()
We can now just get the data needed from the gl_shader_program_data
pointer in gl_program.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Sat, 5 Nov 2016 12:35:11 +0000 (23:35 +1100)]
i965: pass gl_program to brw_upload_ubo_surfaces()
There is no need to pass gl_linked_shader anymore.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 22:34:52 +0000 (09:34 +1100)]
i965: stop passing gl_shader_program to brw_assign_common_binding_table_offsets()
We now get everything we need directly from gl_program so there is
no need for this.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 23:10:02 +0000 (10:10 +1100)]
st/mesa/glsl/i965: move ShaderStorageBlocks to gl_program
Having it here rather than in gl_linked_shader allows us to simplify
the code.
Also it is error prone to depend on the gl_linked_shader for programs
in current use because a failed linking attempt will free infomation
about the current program. In i965 we could be trying to recompile
a shader variant but may have lost some required fields.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 22:24:51 +0000 (09:24 +1100)]
st/mesa/glsl/i965: set num_ssbos directly in shader_info
Here we also remove the duplicate field in gl_linked_shader and always
get the value from shader_info instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 21:55:57 +0000 (08:55 +1100)]
st/mesa/glsl/i965: move per stage UniformBlocks to gl_program
This will help allow us to store pointers to gl_program structs in the
CurrentProgram array resulting in a bunch of code simplifications.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 21:44:22 +0000 (08:44 +1100)]
st/mesa/glsl/i965: set num_ubos directly in shader_info
This also removes the duplicate field in gl_linked_shader, and
gets num_ubos from shader_info instead.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 09:02:21 +0000 (20:02 +1100)]
st/mesa/glsl/i965: move ImageUnits and ImageAccess fields to gl_program
Having it here rather than in gl_linked_shader allows us to simplify
the code.
Also it is error prone to depend on the gl_linked_shader for programs
in current use because a failed linking attempt will free infomation
about the current program. In i965 we could be trying to recompile
a shader variant but may have lost some required fields.
We drop the memset on ImageUnits because gl_program is already
created using rzalloc().
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Mon, 7 Nov 2016 06:08:23 +0000 (17:08 +1100)]
i965: get InfoLog and LinkStatus via the pointer in gl_program
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Mon, 7 Nov 2016 05:43:39 +0000 (16:43 +1100)]
i965: get shared_size from shader_info rather than gl_shader_program
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Mon, 7 Nov 2016 00:43:47 +0000 (11:43 +1100)]
i965: stop depending on gl_shader_program for brw_compute_vue_map() params
This removes another dependency on gl_shader_program from the codegen functions,
this will help allow us to use gl_program for the CurrentProgram array rather
than gl_shader_program.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Fri, 4 Nov 2016 03:09:35 +0000 (14:09 +1100)]
i965: pass gl_program to the brw_*_debug_recompile() functions
Rather then passing gl_shader_program.
The only field use was Name which is the same as the Id field in
gl_program.
For wm and vs we also make the functions static and move them before
the codegen functions.
This change reduces the codegen functions dependency on gl_shader_program.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Roland Scheidegger [Thu, 5 Jan 2017 23:46:15 +0000 (00:46 +0100)]
gallivm: (trivial) fix typo bug with small AoS format unpacking
Fix typo using wrong (uninitialized) build context introduced by
4634cb5921b985f04f2daf00cda2d28036143bd3. (This only affects very rare
small packed formats which have a PIPE_SWIZZLE_0 channel, such as
r4a4, which is never used by mesa/st. Nevertheless it broke lp_test_format.)
Roland Scheidegger [Wed, 21 Dec 2016 03:56:01 +0000 (04:56 +0100)]
gallivm: implement aos unpack (to unorm8) for small unorm formats
Using bit replication. This path now resembles something which might make
sense. (The logic was mostly copied from llvmpipe fs backend.)
I am not convinced though it is actually faster than SoA sampling (actually
I'm quite certain it's always a loss with AVX).
With SoA it's just shift/mask/cvt/mul for getting the colors, whereas
there's still roughly 3 shifts, 3 or/and per channel for AoS
(i.e. for SoA it's exactly the same as it would be for a rgba8 format,
whereas the extra effort for AoS is significant). The filtering
might still be faster (albeit with FMA the instruction count gets down
quite a bit there on the SoA float filtering path on new cpus). And those
small unorm formats often don't have an alpha channel (which makes things
worse relatively for AoS path).
(This also fixes a trivial bug in the llvmpipe fs code this was derived
from, albeit it was only relevant for 4-bit channels.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 21 Dec 2016 03:55:34 +0000 (04:55 +0100)]
gallivm: optimize lp_build_unpack_arith_rgba_aos slightly
This code uses a vector shift which has to be emulated on x86 unless
there's AVX2. Luckily in some cases we can actually avoid the shift
altogether, so do that.
Also make sure we hit the fast lp_build_conv() path when applicable,
albeit that's quite the hack...
That said, this path is taken for AoS sampling for small unorm (smaller
than rgba8) formats, and it is completely hopeless even with those
changes, with or without AVX.
(Probably should have some code similar to the one in the llvmpipe fs
backend code, using bit replication to extend to rgba8888 - rounding
is not quite 100% accurate but if it's good enough there it should be
here as well.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 21 Dec 2016 03:53:41 +0000 (04:53 +0100)]
gallivm: use 2 srcs for 32->16bit conversions in lp_bld_conv_auto
If we only feed one source vector at a time, we cannot use pack intrinsics
(as we only have a 64bit destination dst vector). lp_bld_conv_auto is
specifically designed to alter the length and number of destination vectors,
so this works just fine (if we use single source vectors at a time, afterwards
we immediately reassemble the vectors).
For AVX though this isn't really possible, since we expect 128bit output
already for a single 256bit input. (One day we should handle AVX2 which again
would need multiple inputs, however there's the problem that we get different
ordered output there and we don't want to reorder, so would need to be able
to tell build_conv to handle upper and lower halfs independently.)
A similar strategy would probably work for 32->8bit too (if it doesn't hit
the special case) but I'm going to try something different for that...
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 21 Dec 2016 03:52:16 +0000 (04:52 +0100)]
llvmpipe: (trivial) minimally simplify mask construction
simd instruction sets usually have comparisons for equal, not unequal.
So use a different comparison against the mask itself - which also means
we don't need a all-zero as well as a all-one (for the pxor) reg.
Also add code to avoid scalar expansion of i1 values which we definitely
shouldn't do. There's problems with this though with llvm select
interaction, so it's disabled (basically using llvm select instead of
intrinsics may still produce atrocious code, even in cases where we
figured it should not, albeit I think this could probably be fixed
with some better selection of optimization passes, but I have zero
idea there really).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>