platform/kernel/u-boot.git
4 years agocmd: abootimg: Add abootimg command
Sam Protsenko [Fri, 24 Jan 2020 15:53:42 +0000 (17:53 +0200)]
cmd: abootimg: Add abootimg command

This command can be used to extract fields and image payloads from
Android Boot Image. It can be used for example to implement boot flow
where dtb is taken from boot.img (as v2 incorporated dtb inside of
boot.img). Using this command, one can obtain needed dtb blob from
boot.img in scripting manner, and then apply needed dtbo's (from "dtbo"
partition) on top of that, providing then the resulting image to bootm
command in order to boot the Android.

Also right now this command has the sub-command to get an address and
size of recovery dtbo from recovery image (for non-A/B devices only,
see [1,2] for details).

It can be tested like this:

    => mmc dev 1
    => part start mmc 1 boot_a boot_start
    => part size mmc 1 boot_a boot_size
    => mmc read $loadaddr $boot_start $boot_size
    => abootimg get ver
    => abootimg dump dtb

[1] https://source.android.com/devices/bootloader/boot-image-header
[2] https://source.android.com/devices/architecture/dto/partitions

Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoimage: android: Add routine to get dtbo params
Sam Protsenko [Fri, 24 Jan 2020 15:53:41 +0000 (17:53 +0200)]
image: android: Add routine to get dtbo params

Android Boot Image v1 adds "Recovery DTB" field in image header and
associate payload in boot image itself [1]. Payload should be in
Android DTB/DTBO format [2]. That "Recovery DTB" area should be only
populated for non-A/B devices, and only in recovery image.

Add function to get an address and size of that payload. That function
can be further used e.g. in 'abootimg' command to provide the user a way
to get the address of recovery dtbo from U-Boot shell, which can be
further parsed using 'adtimg' command.

[1] https://source.android.com/devices/bootloader/boot-image-header
[2] https://source.android.com/devices/architecture/dto/partitions

Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoimage: android: Add functions for handling dtb field
Sam Protsenko [Fri, 24 Jan 2020 15:53:40 +0000 (17:53 +0200)]
image: android: Add functions for handling dtb field

Android Boot Image v2 adds "DTB" payload (and corresponding field in the
image header). Provide functions for its handling:

  - android_image_get_dtb_by_index(): Obtain DTB blob from "DTB" part of
    boot image, by blob's index
  - android_image_print_dtb_contents(): Iterate over all DTB blobs in
    "DTB" part of boot image and print those blobs info

"DTB" payload might be in one of the following formats:
  1. concatenated DTB blobs
  2. Android DTBO format

The latter requires "android-image-dt.c" functionality, so this commit
selects that file for building for CONFIG_ANDROID_BOOT_IMAGE option.

Right now this new functionality isn't used, but it can be used further.
As it's required to apply some specific dtbo blob(s) from "dtbo"
partition, we can't automate this process inside of "bootm" command. But
we can do next:
  - come up with some new command like "abootimg" to extract dtb blob
    from boot image (using functions from this patch)
  - extract desired dtbo blobs from "dtbo" partition using "adtimg"
    command
  - merge dtbo blobs into dtb blob using "fdt apply" command
  - pass resulting dtb blob into bootm command in order to boot the
    Android kernel with Android ramdisk from boot image

Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
4 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Sun, 2 Feb 2020 20:26:53 +0000 (15:26 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

- DFU and Cadence USB 3 fixes

4 years agodfu: Add option to skip empty pages when flashing UBI images to NAND
Guillermo Rodríguez [Mon, 16 Dec 2019 15:27:57 +0000 (16:27 +0100)]
dfu: Add option to skip empty pages when flashing UBI images to NAND

Add a new option to enable the DROP_FFS flag when flashing UBI images to
NAND in order to drop trailing all-0xff pages.

This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option.

Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
4 years agousb: cdns3: ep0: Invalidate cache before reading Setup Packet
Vignesh Raghavendra [Mon, 27 Jan 2020 12:25:54 +0000 (17:55 +0530)]
usb: cdns3: ep0: Invalidate cache before reading Setup Packet

Invalidate dcache line before accessing Setup Packet contents. Otherwise
driver will see stale content on non coherent architecture.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
4 years agoMerge tag 'u-boot-rockchip-20200130' of https://gitlab.denx.de/u-boot/custodians...
Tom Rini [Sat, 1 Feb 2020 20:31:04 +0000 (15:31 -0500)]
Merge tag 'u-boot-rockchip-20200130' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- Support redundant boot for rk3399
- Support binman for rockchip platform
- Update ram driver and add ddr4 support for rk3328

4 years agoMerge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot...
Tom Rini [Fri, 31 Jan 2020 18:26:28 +0000 (13:26 -0500)]
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.04 (2nd)

Denali NAND driver changes:
 - Set up more registers in denali-spl for SOCFPGA
 - Make clocks optional
 - Do not assert reset signals in the remove hook
 - associate SPARE_AREA_SKIP_BYTES with DT compatible
 - switch to UCLASS_MTD

UniPhier platform changes:
 - fix a bug in dram_init()
 - specify loadaddr for "source" command

4 years agoARM: uniphier: use $loadaddr for source command
Masahiro Yamada [Thu, 30 Jan 2020 13:20:38 +0000 (22:20 +0900)]
ARM: uniphier: use $loadaddr for source command

If the "source" command is not given the address, it uses
CONFIG_SYS_LOAD_ADDR, which is compile-time determined.

Using the "loadaddr" environment variable is handier because it is
relocated according to the memory base when CONFIG_POSITION_INDEPENDENT
is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoARM: uniphier: set gd->ram_base correctly
Masahiro Yamada [Thu, 30 Jan 2020 13:20:37 +0000 (22:20 +0900)]
ARM: uniphier: set gd->ram_base correctly

gd->ram_base is not set at all if the end address of the DRAM ch0
exceeds the 4GB limit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agomtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISC
Masahiro Yamada [Thu, 30 Jan 2020 13:07:59 +0000 (22:07 +0900)]
mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISC

UCLASS_MTD is a better fit for NAND drivers.

Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile
drivers/mtd/mtd-uclass.c

Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig
of this platform enables NAND_DENALI_DT.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
4 years agoARM: uniphier: remove adhoc reset deassertion for the NAND controller
Masahiro Yamada [Wed, 29 Jan 2020 15:55:57 +0000 (00:55 +0900)]
ARM: uniphier: remove adhoc reset deassertion for the NAND controller

Now that the reset controlling of the Denali NAND driver (denali_dt.c)
works for this platform, remove the adhoc reset deassert code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agomtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatible
Masahiro Yamada [Wed, 29 Jan 2020 15:55:55 +0000 (00:55 +0900)]
mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES based on DT compatible

Currently, the denali NAND driver in U-Boot configures the
SPARE_AREA_SKIP_BYTES based on the CONFIG option.

Recently, Linux kernel merged a patch that associates the proper
value for this register with the DT compatible string.

Do likewise in U-Boot too.

The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agomtd: rawnand: denali_dt: insert udelay() after reset deassert
Masahiro Yamada [Wed, 29 Jan 2020 15:55:54 +0000 (00:55 +0900)]
mtd: rawnand: denali_dt: insert udelay() after reset deassert

When the reset signal is de-asserted, the HW-controlled bootstrap
starts running unless it is disabled in the SoC integration.
It issues some commands to detect a NAND chip, and sets up registers
automatically. Until this process finishes, software should avoid
any register access.

Without this delay function, some of UniPhier boards hangs up while
executing nand_scan_ident(). (denali_read_byte() is blocked)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agomtd: rawnand: denali: Do not reset the block before booting the kernel
Marek Vasut [Tue, 21 Jan 2020 19:03:11 +0000 (20:03 +0100)]
mtd: rawnand: denali: Do not reset the block before booting the kernel

The Denali NAND driver in mainline Linux currently cannot deassert the
reset. The upcoming Linux 5.6 will support the reset controlling, and
also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in
the future kernel will work without relying on any bootloader or firmware.
However, we still need to take care of stable kernel versions for a while.
U-boot should not assert the reset of this controller.

Fixes: ed784ac3822b ("mtd: rawnand: denali: add reset handling")
Signed-off-by: Marek Vasut <marex@denx.de>
[yamada.masahiro: reword the commit description]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agomtd: rawnand: denali_dt: make the core clock optional
Masahiro Yamada [Tue, 21 Jan 2020 19:03:10 +0000 (20:03 +0100)]
mtd: rawnand: denali_dt: make the core clock optional

The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
4 years agomtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA
Marek Vasut [Tue, 21 Jan 2020 19:03:09 +0000 (20:03 +0100)]
mtd: rawnand: denali-spl: Add missing hardware init on SoCFPGA

On Altera SoCFPGA, upon either cold-boot or power-on reset, the
Denali NAND IP is initialized by the BootROM ; upon warm-reset,
the Denali NAND IP is NOT initialized by BootROM. In fact, upon
warm-reset, the SoCFPGA BootROM checks whether the SPL image in
on-chip RAM is valid and if so, completely skips re-loading the
SPL from the boot media.

This does sometimes lead to problems where the software left
the boot media in inconsistent state before warm-reset, and
because the BootROM does not reset the boot media, the boot
media is left in this inconsistent state, often until another
component attempts to access the boot media and fails with an
difficult to debug failure. To mitigate this problem, the SPL
on Altera SoCFPGA always resets all the IPs on the SoC early
on boot.

This results in a couple of register values, pre-programmed by
the BootROM, to be lost during this reset. To restore correct
operation of the IP on SoCFPGA, these values must be programmed
back into the controller by the driver. Note that on other SoCs
which do not use the HW-controlled bootstrap, more registers
may have to be programmed.

This also aligns the SPL behavior with the full Denali NAND
driver, which sets these values in denali_hw_init().

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
4 years agoMerge branch '2020-01-30-master-imports'
Tom Rini [Fri, 31 Jan 2020 01:38:47 +0000 (20:38 -0500)]
Merge branch '2020-01-30-master-imports'

- Assorted minor fixes
- Revert 6dcb8ba4 from upstream libfdt to restore boot-time speed on
  many platforms.

4 years agoRemove redundant YYLOC global declaration
Peter Robinson [Thu, 30 Jan 2020 09:37:15 +0000 (09:37 +0000)]
Remove redundant YYLOC global declaration

Same as the upstream fix for building dtc with gcc 10.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
4 years agoMakefile: Fix the location of the migration file
Fabio Estevam [Wed, 29 Jan 2020 20:05:29 +0000 (17:05 -0300)]
Makefile: Fix the location of the migration file

Since commit e1910d93b890 ("doc: driver-model: Convert MIGRATION.txt to
reST") MIGRATION.txt has been converted to migration.rst, so update
the Makefile references accordingly.

Fixes: e1910d93b890 ("doc: driver-model: Convert MIGRATION.txt to reST")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agotools: buildman: fix typo
Flavio Suligoi [Wed, 29 Jan 2020 08:56:05 +0000 (09:56 +0100)]
tools: buildman: fix typo

Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agonet: fix typo
Flavio Suligoi [Wed, 29 Jan 2020 08:38:56 +0000 (09:38 +0100)]
net: fix typo

Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
4 years agoMAINTAINERS: board: hisi: poplar: update email
Jorge Ramirez-Ortiz [Tue, 28 Jan 2020 22:16:21 +0000 (23:16 +0100)]
MAINTAINERS: board: hisi: poplar: update email

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
4 years agoMAINTAINERS: board: qcom: db820c: update email
Jorge Ramirez-Ortiz [Tue, 28 Jan 2020 22:16:20 +0000 (23:16 +0100)]
MAINTAINERS: board: qcom: db820c: update email

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
4 years agolibfdt: Revert 6dcb8ba4 from upstream libfdt
Tom Rini [Mon, 27 Jan 2020 17:10:31 +0000 (12:10 -0500)]
libfdt: Revert 6dcb8ba4 from upstream libfdt

In upstream libfdt, 6dcb8ba4 "libfdt: Add helpers for accessing
unaligned words" introduced changes to support unaligned reads for ARM
platforms and 11738cf01f15 "libfdt: Don't use memcpy to handle unaligned
reads on ARM" improved the performance of these helpers.

In practice however, this only occurs when the user has forced the
device tree to be placed in memory in a non-aligned way, which in turn
violates both our rules and the Linux Kernel rules for how things must
reside in memory to function.

This "in practice" part is important as handling these other cases adds
visible (1 second or more) delay to boot in what would be considered the
fast path of the code.

Cc: Patrice CHOTARD <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Link: https://www.spinics.net/lists/devicetree-compiler/msg02972.html
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
4 years agoConsistently use nproc for counting the CPUs
Heinrich Schuchardt [Mon, 27 Jan 2020 06:59:46 +0000 (07:59 +0100)]
Consistently use nproc for counting the CPUs

Coreutils command nproc can be used on Linux and BSD to count the number of
available CPU cores. Use this instead of relying on the parsing of the
Linux specific proc file system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agooptee: Replace uninitialized return variable by proper one.
Christoph Müllner [Sun, 26 Jan 2020 22:20:54 +0000 (23:20 +0100)]
optee: Replace uninitialized return variable by proper one.

As hinted by GCC 9, there is a return statement that returns
an uninitialized variable in optee_copy_firmware_node().
This patch addresses this.

Signed-off-by: Christoph Müllner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
4 years agotools: correct Markdown in concurrencytest/README.md
Heinrich Schuchardt [Sat, 25 Jan 2020 22:38:42 +0000 (23:38 +0100)]
tools: correct Markdown in concurrencytest/README.md

Remove incorrect indentation.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
4 years agocommon/board_f.c: Remove arch-specific checks for cpucheck
Ovidiu Panait [Wed, 22 Jan 2020 20:28:25 +0000 (22:28 +0200)]
common/board_f.c: Remove arch-specific checks for cpucheck

This removes the arch-specific checks for "checkcpu" function from the init
sequence. Make "checkcpu" generic and provide a weak nop stub instead.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
4 years agocmd/gpt: Address error cases during gpt rename more correctly
Tom Rini [Tue, 21 Jan 2020 16:53:38 +0000 (11:53 -0500)]
cmd/gpt: Address error cases during gpt rename more correctly

New analysis by the tool has shown that we have some cases where we
weren't handling the error exit condition correctly.  When we ran into
the ENOMEM case we wouldn't exit the function and thus incorrect things
could happen.  Rework the unwinding such that we don't need a helper
function now and free what we may have allocated.

Fixes: 18030d04d25d ("GPT: fix memory leaks identified by Coverity")
Reported-by: Coverity (CID: 275475, 275476)
Cc: Alison Chaiken <alison@she-devel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Jordy <jordy@simplyhacker.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
4 years agoconfigs: firefly-rk3399: Enable CONFIG_MISC_INIT_R and ROCKCHIP_EFUSE
Mark Kettenis [Mon, 13 Jan 2020 10:39:16 +0000 (11:39 +0100)]
configs: firefly-rk3399: Enable CONFIG_MISC_INIT_R and ROCKCHIP_EFUSE

This enables readning the cpuid from e-fuse, and deriving a static
MAC address from it.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rk3308: add alias for emmc/sdmmc
Kever Yang [Wed, 8 Jan 2020 09:38:48 +0000 (17:38 +0800)]
rockchip: rk3308: add alias for emmc/sdmmc

Add alias for mmc/sdmmc so that we can have a fix mmc number for emmc.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: px30: remove CONFIG_OPTEE support
Kever Yang [Tue, 7 Jan 2020 08:59:39 +0000 (16:59 +0800)]
rockchip: px30: remove CONFIG_OPTEE support

Rockchip use CONFIG_SPL_OPTEE for OPTEE support, which is load and run
before U-Boot, but not use CONFIG_OPTEE which is after U-Boot.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3328: update lpddr3 setting
YouMin Chen [Tue, 7 Jan 2020 07:15:22 +0000 (15:15 +0800)]
ram: rk3328: update lpddr3 setting

update lpddr3 setting for fix init fail about "col error".

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3328: add support ddr4 init
YouMin Chen [Tue, 7 Jan 2020 07:15:21 +0000 (15:15 +0800)]
ram: rk3328: add support ddr4 init

Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3328: only do data traning for cs0
Kever Yang [Tue, 7 Jan 2020 07:15:20 +0000 (15:15 +0800)]
ram: rk3328: only do data traning for cs0

No need to do twice data training for rk3328 ddr sdram, we re-use the
setting for both channel. And adjust the sdram_init properly for correct
init flow.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
4 years agodoc: boards: Add rockchip documentation
Jagan Teki [Thu, 9 Jan 2020 18:46:22 +0000 (00:16 +0530)]
doc: boards: Add rockchip documentation

Rockchip has documentation file, doc/README.rockchip but
which is not so readable to add or understand the existing
contents. Even the format that support is legacy readme
in U-Boot.

Add rockchip specific documentation file using new rst
format, which describes the information about Rockchip
supported boards and it's usage steps.

Added minimal information about rk3288, rk3328, rk3368
and rk3399 boards and usage. This would indeed updated
further based on the requirements and updates.

Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: Add Single boot image (with binman, pad_cat)
Jagan Teki [Thu, 9 Jan 2020 18:46:21 +0000 (00:16 +0530)]
rockchip: Add Single boot image (with binman, pad_cat)

All rockchip platforms support TPL or SPL-based bootloader
in mainline with U-Boot proper as final stage. For each
stage we need to burn the image on to flash with respective
offsets.

This patch creates a single boot image component using
- binman, for arm32 rockchip platforms
- pad_cat, for arm64 rockchip platforms.

This would help users to get rid of burning different
boot stage images.

The new image called 'u-boot-rockchip.bin'
which can burn into flash like:

₹ sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64

This would support all rockchip platforms, except rk3128
since it doesn't support for SPL yet.

Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoarm: dts: rk3188: Add rk3188-u-boot.dtsi
Jagan Teki [Thu, 9 Jan 2020 18:46:20 +0000 (00:16 +0530)]
arm: dts: rk3188: Add rk3188-u-boot.dtsi

Add U-Boot specific dtsi file for rk3188 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3188.

Right now, the file is empty, will add required changes
in future patches.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoarm: dts: rk3036: Add rk3036-u-boot.dtsi
Jagan Teki [Thu, 9 Jan 2020 18:46:19 +0000 (00:16 +0530)]
arm: dts: rk3036: Add rk3036-u-boot.dtsi

Add U-Boot specific dtsi file for rk3036 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3036.

Right now, the file is empty, will add required changes
in future patches.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMakefile: rockchip: Support SPL-alone mkimage
Jagan Teki [Thu, 9 Jan 2020 18:46:18 +0000 (00:16 +0530)]
Makefile: rockchip: Support SPL-alone mkimage

Add SPL-alone mkimage tooling support via Makefile for
few platforms or boards used in rockchip family.

With this users would get rid of explicitly creating
mkimage tool for rockchip rksd or rkspi boot modes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMakefile: rockchip: Suffix platform type with tpl name
Jagan Teki [Thu, 9 Jan 2020 18:46:17 +0000 (00:16 +0530)]
Makefile: rockchip: Suffix platform type with tpl name

Most of the platforms uses the platform type on their boot
stage image naming conventions in makefile like,

u-boot-x86-start16-tpl.bin - x86 start16 TPL bin
u-boot-spl-mtk.bin - Mediatek SPL bin

This would help to understand the users to what that
particular image belongs to? and less confused.

On that note, suffix platform type rockchip for existing
u-boot-tpl.img so now it become u-boot-tpl-rockchip.bin

Also, bin is more conventional way to include it on tools
like binman, pad_cat etc in future patches.

Note: usage of platform type doesn't follow consistent order
as of now.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMakefile: Add rockchip image type
Jagan Teki [Thu, 9 Jan 2020 18:46:16 +0000 (00:16 +0530)]
Makefile: Add rockchip image type

Add rockchip image type support. right now the image
type marked with rksd, So create image type variable
with required image type like rksd or rkspi.

Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: rk3399: Add bootcount support
Jagan Teki [Thu, 9 Jan 2020 08:52:19 +0000 (14:22 +0530)]
rockchip: rk3399: Add bootcount support

Add bootcount support for Rockchip rk3399.

The bootcount value is preserved in PMU_SYS_REG0 register,
this would help to support redundent boot.

Once the redundant boot triggers, the altboot command
will look for extlinux-rollback.conf on particular
bootable partition which supposed to be a recovery
partition where redundant boot required.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: Add common reset cause
Jagan Teki [Thu, 9 Jan 2020 08:52:18 +0000 (14:22 +0530)]
rockchip: Add common reset cause

Add cpu reset cause in common cpu-info file.

This would help to print the reset cause for
various resets.

Right now it support rk3288, rk3399. rest of rockchip
platforms doesn't have reset cause support ye but this
code is more feasible to extend the same.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agoarm: rockchip: Add common cru.h
Jagan Teki [Thu, 9 Jan 2020 08:52:17 +0000 (14:22 +0530)]
arm: rockchip: Add common cru.h

Few of the rockchip family SoC atleast rk3288,
rk3399 are sharing some cru register bits so
adding common code between these SoC families
would require to include both cru include files
that indeed resulting function declarations error.

So, create a common cru include as cru.h then
include the rk3399 arch cru include file and move
the common cru register bit definitions into it.

The rest of rockchip cru files will add it in future.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: rk3399: Enable DISPLAY_CPUINFO
Jagan Teki [Thu, 9 Jan 2020 08:52:16 +0000 (14:22 +0530)]
rockchip: rk3399: Enable DISPLAY_CPUINFO

RK3288, RK3399 are now support cpu-info, so enable
DISPLAY_CPUINFO by default.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockchip: Add cpu-info
Jagan Teki [Thu, 9 Jan 2020 08:52:15 +0000 (14:22 +0530)]
rockchip: Add cpu-info

Add cpu information for rockchip soc.

This would help to print the SoC family number, with
associated temparature, clock and reason for reset etc.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agorockpro-rk3399: Enable SPI Flash
Jagan Teki [Sat, 21 Dec 2019 07:54:39 +0000 (13:24 +0530)]
rockpro-rk3399: Enable SPI Flash

Enable winbond SPI flash for ROC-PC-RK3399 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoroc-pc-rk3399: Enable SPI Flash
Jagan Teki [Sat, 21 Dec 2019 07:54:38 +0000 (13:24 +0530)]
roc-pc-rk3399: Enable SPI Flash

Enable winbond SPI flash for ROC-PC-RK3399 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agorockchip: dts: Sync ROC-RK3399-PC changes from Linux
Jagan Teki [Sat, 21 Dec 2019 07:54:37 +0000 (13:24 +0530)]
rockchip: dts: Sync ROC-RK3399-PC changes from Linux

Sync the ROC-RK3399-PC device tree changes from Linux
with below commit details:

commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts:
rockchip: Enable MTD Flash on rk3399-roc-pc")

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoenv: Enable SPI flash env for rockchip
Jagan Teki [Sat, 21 Dec 2019 07:54:36 +0000 (13:24 +0530)]
env: Enable SPI flash env for rockchip

Most of the SPI flash devices in rockchip are 16MiB size.

So, keeping U-Boot proper offset start from 128MiB with 1MiB
size and then start env of 8KiB would be a compatible location
between all variants of flash sizes.

This patch add env start from 0x14000 with a size of 8KiB.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoenv: kconfig: Restrict rockchip env for MMC
Jagan Teki [Sat, 21 Dec 2019 07:54:35 +0000 (13:24 +0530)]
env: kconfig: Restrict rockchip env for MMC

Rockchip do support SPI flash as well, so there is
a possibility of using flash environment for those
use cases.

So, restrict the current env offset, size for MMC.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agork3399: Check MMC env while defining it
Jagan Teki [Sat, 21 Dec 2019 07:54:34 +0000 (13:24 +0530)]
rk3399: Check MMC env while defining it

rk3399 do support SPI flash as well, so there is
a possibility of using flash environment for those
usecases.

So define env device for MMC only when it is used
by specific configuration.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoram: rk3399: don't assume phy_io_config() uses real regs
Thomas Hebb [Fri, 20 Dec 2019 20:28:15 +0000 (12:28 -0800)]
ram: rk3399: don't assume phy_io_config() uses real regs

In the RK3399 DRAM driver, the function set_ds_odt() supports operating
in two different modes, selected by the ctl_phy_reg argument: when true,
the function reads and writes directly from the DRAM registers, accessed
through "chan->pctl->denali_*"; when false, the function reads and
writes from an array, accessed through "params->pctl_regs.denali_*",
which is written to DRAM registers at a later time.

However, phy_config_io(), which is called by set_ds_odt() to do a subset
of its register operations, operates directly on DRAM registers at all
times. This means that it reads incorrect values (and writes new values
prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by
passing in the address of the registers to work with.

This prevents an "Invalid DRV value" error in the SPL debug log and
(presumably) results in a more correct end state. See the following logs
from a RK3399 NanoPi M4 board (4GB LPDDR3):

Before:

  sdram_init() Starting SDRAM initialization...
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 0
  phy_io_config() Invalid DRV value.
  phy_io_config() Invalid DRV value.
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

After:

  sdram_init() Starting SDRAM initialization...
  sdram_init() sdram_init: data trained for rank 2, ch 0
  sdram_init() sdram_init: data trained for rank 2, ch 1
  Channel 0: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  Channel 1: LPDDR3, 933MHz
  BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
  256B stride
  256B stride
  sdram_init() Finish SDRAM initialization...

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
4 years agoMerge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
Tom Rini [Wed, 29 Jan 2020 14:34:13 +0000 (09:34 -0500)]
Merge tag 'for-v2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c

i2c changes for 2020.04
- updates the Designware I2C driver
  - get timings from device tree
  - handle units in nanoseconds
  - make sure that the requested bus speed is not exceeded
  - few smaller clean-ups
- adds enums for i2c speed and update drivers which use them
- global_data: remove unused mxc_i2c specific field

4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung
Tom Rini [Wed, 29 Jan 2020 02:10:32 +0000 (21:10 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsung

- Various exynos fixes

4 years agoPrepare v2020.04-rc1
Tom Rini [Tue, 28 Jan 2020 21:59:30 +0000 (16:59 -0500)]
Prepare v2020.04-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoMerge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
Tom Rini [Tue, 28 Jan 2020 00:57:13 +0000 (19:57 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

- spi cs accessing slaves (Bin Meng)
- spi prevent overriding established bus (Marcin Wojtas)
- support speed in spi command (Marek Vasut)
- add W25N01GV spinand (Robert Marko)
- move cadence_qspi to use spi-mem (Vignesh Raghavendra)
- add octal mode (Vignesh Raghavendra)

4 years agoarm: exynos: odroid: Change autoboot script to use ${mmcbootdev}
Marek Szyprowski [Fri, 17 Jan 2020 13:12:58 +0000 (14:12 +0100)]
arm: exynos: odroid: Change autoboot script to use ${mmcbootdev}

This fixes the default boot command for the SD-card boot case.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
4 years agoMerge branch '2020-01-27-master-imports'
Tom Rini [Tue, 28 Jan 2020 00:54:41 +0000 (19:54 -0500)]
Merge branch '2020-01-27-master-imports'

- Add Dialog DA9063 PMIC support
- s35392a RTC bugfix
- Allow for opt-in of removal of DTB properties from the resulting
  binary.

4 years agopmic: allow dump command for non contiguous register maps
Martin Fuzzey [Tue, 14 Jan 2020 15:56:18 +0000 (15:56 +0000)]
pmic: allow dump command for non contiguous register maps

Some PMICs (such as the DA9063) have non-contiguous register maps.
Attempting to read the non implemented registers returns an error
rather than a dummy value which causes 'pmic dump' to terminate
prematurely.

Fix this by allowing the PMIC driver to return -ENODATA for such
registers, which will then be displayed as '--' by pmic dump.

Use a single error code rather than any error code so that
we can distinguish between a hardware failure reading the PMIC
and a non implemented register known to the driver.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
4 years agopower: regulator: add driver for Dialog DA9063 PMIC
Martin Fuzzey [Tue, 14 Jan 2020 15:56:17 +0000 (15:56 +0000)]
power: regulator: add driver for Dialog DA9063 PMIC

Add a driver for the regulators in the the DA9063 PMIC.

Robert Beckett: move regulator modes to header so board code can set
modes. Correct mode mask used in ldo_set_mode.
Add an option CONFIG_SPL_DM_REGULATOR_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
4 years agopower: pmic: add driver for Dialog DA9063 PMIC
Martin Fuzzey [Tue, 14 Jan 2020 15:56:16 +0000 (15:56 +0000)]
power: pmic: add driver for Dialog DA9063 PMIC

This adds the basic register access operations and child regulator
binding (if a regulator driver exists).

Robert Beckett: simplify accesses by using bottom bit of address as
offset overflow. This avoids the need to track which page we are on.
Add an option CONFIG_SPL_DM_PMIC_DA9063.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
4 years agortc: s35392a: encode command correctly
Ian Ray [Tue, 14 Jan 2020 16:18:20 +0000 (16:18 +0000)]
rtc: s35392a: encode command correctly

The 3-bit "command", or register, is encoded within the device address.
Configure the device accordingly, and pass command in DM I2C read/write
calls correctly.

Signed-off-by: Ian Ray <ian.ray@ge.com>
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
4 years agocmd: sata: Add block unbind device function
Peng Ma [Wed, 4 Dec 2019 10:36:47 +0000 (10:36 +0000)]
cmd: sata: Add block unbind device function

If we didn't unbind the sata from block device, the same devices would
be added after sata remove,
This patch is to resolve this issue as below:

=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY30
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX30
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
=> sata stop
=> sata info
SATA#0:
(3.0 Gbps)
SATA#1:
(3.0 Gbps)
Device 0: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 1: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 2: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005PY300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)
Device 3: Model: INTEL SSDSA2BW300G3D Firm: 4PC10362 Ser#: BTPR247005VX300
            Type: Hard Disk
            Supports 48-bit addressing
            Capacity: 286168.1 MB = 279.4 GB (586072368 x 512)

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agotbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfig
Anatolij Gustschin [Sun, 12 Jan 2020 14:57:43 +0000 (15:57 +0100)]
tbs2910: add custom CONFIG_OF_REMOVE_PROPS list to defconfig

This shrinks the image size: all -3840.0 text -3840.0

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Soeren Moch <smoch@web.de>
4 years agodts: add property removal option CONFIG_OF_REMOVE_PROPS
Anatolij Gustschin [Sun, 12 Jan 2020 14:57:42 +0000 (15:57 +0100)]
dts: add property removal option CONFIG_OF_REMOVE_PROPS

This can be used for device tree size reduction similar as
CONFIG_OF_SPL_REMOVE_PROPS option. Some boards must pass the
built-in DTB unchanged to the kernel, thus we may not cut it
down unconditionally. Therefore enable the property removal
list option only if CONFIG_OF_DTB_PROPS_REMOVE is selected.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
4 years agoarm: exynos: Read default MMC device from XOM[7:5] pins
Marek Szyprowski [Fri, 17 Jan 2020 13:02:44 +0000 (14:02 +0100)]
arm: exynos: Read default MMC device from XOM[7:5] pins

XOM pins provide information for iROM bootloader about the boot device.
Those pins are mapped to lower bits of OP_MODE register (0x10000008),
which is common for all Exynos SoC variants. Set the default MMC device id
to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for
the eMMC).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
4 years agospi: cadence-qspi: Add compatible for TI AM654
Vignesh Raghavendra [Thu, 5 Dec 2019 10:16:07 +0000 (15:46 +0530)]
spi: cadence-qspi: Add compatible for TI AM654

TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: cadence-qspi: Add support for Cadence Octal SPI controller
Vignesh Raghavendra [Thu, 5 Dec 2019 10:16:06 +0000 (15:46 +0530)]
spi: cadence-qspi: Add support for Cadence Octal SPI controller

Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agomtd: spi-nor-core: Add octal mode support
Vignesh Raghavendra [Thu, 5 Dec 2019 10:16:05 +0000 (15:46 +0530)]
mtd: spi-nor-core: Add octal mode support

Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: cadence-qspi: Add direct mode support
Vignesh Raghavendra [Mon, 27 Jan 2020 05:06:40 +0000 (10:36 +0530)]
spi: cadence-qspi: Add direct mode support

Add support for Direct Access Controller mode of Cadence QSPI. This
allows MMIO access to SPI NOR flash providing better read performance.
Direct mode is only exercised if AHB window size is greater than 8MB.
Support for flash address remapping is also not supported at the moment
and can be added in future.

For better performance, driver uses DMA to copy data from flash in
direct mode using dma_memcpy().

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: cadence_qspi: Move to spi-mem framework
Vignesh Raghavendra [Mon, 27 Jan 2020 05:06:39 +0000 (10:36 +0530)]
spi: cadence_qspi: Move to spi-mem framework

Current Cadence QSPI driver has few limitations. It assumes all read
operations to be in Quad mode and thus does not support SFDP parsing.
Also, adding support for new mode such as Octal mode would not be
possible with current configuration. Therefore move the driver over to spi-mem
framework. This has added advantage that driver can be used to support
SPI NAND memories too.
Hence, move driver over to new spi-mem APIs.

Please note that this gets rid of mode bit setting done when
CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
that config option.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agomtd: spinand: winbond: Add support for W25N01GV
Robert Marko [Thu, 16 Jan 2020 13:03:35 +0000 (14:03 +0100)]
mtd: spinand: winbond: Add support for W25N01GV

Linux has supported W25N01GV for a long time, so lets import it.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: ti_qspi: Add support for CS other than CS0
Vignesh Raghavendra [Wed, 11 Dec 2019 13:29:36 +0000 (18:59 +0530)]
spi: ti_qspi: Add support for CS other than CS0

Make sure corresponding setup registers are updated depending on CS.
This ensures that driver can support QSPI flashes on ChipSelects other
than on CS0

Reported-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agospi: prevent overriding established bus settings
Marcin Wojtas [Thu, 21 Nov 2019 04:38:47 +0000 (05:38 +0100)]
spi: prevent overriding established bus settings

The SPI stack relies on a proper bus speed/mode configuration
by calling dm_spi_claim_bus(). However the hitherto code
allowed to accidentally override those settings in
the spi_get_bus_and_cs() routine.

The initially established speed could be discarded by using
the slave platdata, which turned out to be an issue on
the platforms whose slave maximum supported frequency
is not on par with the maximum frequency of the bus controller.

This patch fixes above issue by configuring the bus from
spi_get_bus_and_cs() only in case it was not done before.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agocmd: spi: Permit setting bus frequency
Marek Vasut [Fri, 20 Dec 2019 11:44:57 +0000 (12:44 +0100)]
cmd: spi: Permit setting bus frequency

The 'sspi' command hard-coded 1 MHz bus frequency for all transmissions.
Allow changing that at runtime by specifying '@freq' bus frequency in Hz.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agotest: dm: spi: Fix sandbox dm_test_spi_find()
Bin Meng [Mon, 9 Sep 2019 13:00:03 +0000 (06:00 -0700)]
test: dm: spi: Fix sandbox dm_test_spi_find()

Per sandbox_cs_info(), sandbox spi controller only supports chip
select 0. Current test case tries to locate devices on chip select
1, and any call to spi_get_bus_and_cs() or spi_cs_info() with cs
number 1 should not return 0.

This updates the test case to handle it correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
4 years agodm: spi: Check cs number before accessing slaves
Bin Meng [Mon, 9 Sep 2019 13:00:02 +0000 (06:00 -0700)]
dm: spi: Check cs number before accessing slaves

Add chip select number check in spi_find_chip_select().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
4 years agospi: nxp_fspi: new driver for the FlexSPI controller
Michael Walle [Tue, 17 Dec 2019 23:09:58 +0000 (00:09 +0100)]
spi: nxp_fspi: new driver for the FlexSPI controller

This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.

The port was straightforward:
 - remove the interrupt handling and the completion by busy polling the
   controller
 - remove locks
 - move the setup of the memory windows into claim_bus()
 - move the setup of the speed into set_speed()
 - port the device tree bindings from the original fspi_probe() to
   ofdata_to_platdata()

There were only some style change fixes, no change in any logic. For
example, there are busy loops where the return code is not handled
correctly, eg. only prints a warning with WARN_ON(). This port
intentionally left most functions unchanged to ease future bugfixes.

This was tested on a custom LS1028A board. Because the LS1028A doesn't
have proper clock framework support, changing the clock speed was not
tested. This also means that it is not possible to change the SPI
speed on LS1028A for now (neither is it possible in the linux driver).

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com>
4 years agoMerge tag 'u-boot-clk-26Jan2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
Tom Rini [Mon, 27 Jan 2020 12:19:26 +0000 (07:19 -0500)]
Merge tag 'u-boot-clk-26Jan2020' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk

- Various clock fixes and enhancements

4 years agoi2c: designware_i2c: Do more in the probe() method
Simon Glass [Thu, 23 Jan 2020 18:48:26 +0000 (11:48 -0700)]
i2c: designware_i2c: Do more in the probe() method

Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Separate out the speed calculation
Simon Glass [Thu, 23 Jan 2020 18:48:25 +0000 (11:48 -0700)]
i2c: designware_i2c: Separate out the speed calculation

We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.

Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Move dw_i2c_speed_config to header
Simon Glass [Thu, 23 Jan 2020 18:48:24 +0000 (11:48 -0700)]
i2c: designware_i2c: Move dw_i2c_speed_config to header

This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Add support for fast-plus speed
Simon Glass [Thu, 23 Jan 2020 18:48:23 +0000 (11:48 -0700)]
i2c: designware_i2c: Add support for fast-plus speed

Fast-plus runs at 1MHz and is used by some devices. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: Update drivers to use enum for speed
Simon Glass [Thu, 23 Jan 2020 18:48:22 +0000 (11:48 -0700)]
i2c: Update drivers to use enum for speed

Convert the obvious uses of i2c bus speeds to use the enum.

Use livetree access for code changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: stm32: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:21 +0000 (11:48 -0700)]
i2c: stm32: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: omap: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:20 +0000 (11:48 -0700)]
i2c: omap: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: kona_i2c: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:19 +0000 (11:48 -0700)]
i2c: kona_i2c: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Note: This driver needs to move to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:18 +0000 (11:48 -0700)]
i2c: designware_i2c: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: ast_i2c: Update to use standard enums for speed
Simon Glass [Thu, 23 Jan 2020 18:48:17 +0000 (11:48 -0700)]
i2c: ast_i2c: Update to use standard enums for speed

Update this driver to use the new standard enums for speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: Add enums for i2c speed and address size
Simon Glass [Thu, 23 Jan 2020 18:48:16 +0000 (11:48 -0700)]
i2c: Add enums for i2c speed and address size

Some drivers define their own speed enums and use their own constants for
speed. It makes sense to have a unified defition of the different speeds.

Since many controllers have to do different things for fast/high speed, it
is a good idea to have an enum for the mode.

Add these as well as an enum for the address mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Add spike supression
Simon Glass [Thu, 23 Jan 2020 18:48:15 +0000 (11:48 -0700)]
i2c: designware_i2c: Add spike supression

Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Rewrite timing calculation
Simon Glass [Thu, 23 Jan 2020 18:48:14 +0000 (11:48 -0700)]
i2c: designware_i2c: Rewrite timing calculation

At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.

Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than writing it in code.

The function works by calculating the 'period' of each bit on the bus in
terms of the input clock to the controller (IC_CLK). It makes sure that
the constraints are met and that the different components of that period
add up correctly.

This code was taken from coreboot which has ended up with this same
driver, but now in a much-different form.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Put hold config in a struct
Simon Glass [Thu, 23 Jan 2020 18:48:13 +0000 (11:48 -0700)]
i2c: designware_i2c: Put hold config in a struct

Create a struct to hold the three timing parameters. This will make it
easier to move these calculations into a separate function in a later
patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Drop scl_sda_cfg parameter
Simon Glass [Thu, 23 Jan 2020 18:48:12 +0000 (11:48 -0700)]
i2c: designware_i2c: Drop scl_sda_cfg parameter

Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in
the driver's private data, from which the function can obtain that
information. This allows the function to have access to the full state of
the driver.

Signed-off-by: Sicomp_param1mon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoi2c: designware_i2c: Read device-tree properties
Simon Glass [Thu, 23 Jan 2020 18:48:11 +0000 (11:48 -0700)]
i2c: designware_i2c: Read device-tree properties

The i2c controller defines a few timing properties. Read these in and
store them for use by the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Bring in the binding file
Simon Glass [Thu, 23 Jan 2020 18:48:10 +0000 (11:48 -0700)]
i2c: designware_i2c: Bring in the binding file

Bring in this file from Linux v5.4.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
4 years agoi2c: designware_i2c: Use an accurate bus clock instead of MHz
Simon Glass [Thu, 23 Jan 2020 18:48:09 +0000 (11:48 -0700)]
i2c: designware_i2c: Use an accurate bus clock instead of MHz

At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.

This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.

Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.

Update the bus speed code to work in KHz instead of MHz, which removes
most of the error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>