nir/loop_analyze: Determine iteration counts for more kinds of loops

If loop iterator is incremented with something other than regular
addition, it would be more error prone to calculate the number of
iterations theoretically. What we can do instead, is try to emulate the
loop, and determine the number of iterations empirically.

These operations are covered:
 - imul
 - fmul
 - ishl
 - ishr
 - ushr

Also add unit tests for loop unrollment.

Improves performance of Aztec Ruins (sixonix
gfxbench5.aztec_ruins_vk_high) by -1.28042% +/- 0.498555% (N=5) on Intel
Arc A770.

v2 (idr): Rebase on 3 years. :( Use nir_phi_instr_add_src in the test
cases.

v3 (idr): Use try_eval_const_alu in to evaluate loop termination
condition in get_iteration_empirical. Also restructure the loop
slightly. This fixed off by one iteration errors in "inverted" loop
tests (e.g., nir_loop_analyze_test.ushr_ieq_known_count_invert_31).

v4 (idr): Use try_eval_const_alu in to evaluate induction variable
update in get_iteration_empirical. This fixes non-commutative update
operations (e.g., shifts) when the induction varible is not the first
source. This fixes the unit test
nir_loop_analyze_test.ishl_rev_ieq_infinite_loop_unknown_count.

v5 (idr): Fix _type parameter for fadd and fadd_rev loop unroll
tests. Hopefully that fixes the failure on s390x. Temporarily disable
fmul. This works-around the revealed problem in
glsl-fs-loop-unroll-mul-fp64, and there were no shader-db or fossil-db
changes.

v6 (idr): Plumb max_unroll_iterations into get_iteration_empirical. I
was going to do this, but I forgot. Suggested by Tim.

v7 (idr): Disable fadd tests on s390x. They fail because S390 is weird.

Almost all of the shaders affected (OpenGL or Vulkan) are from gfxbench
or geekbench. A couple shaders in Deus Ex (OpenGL), Dirt Rally (OpenGL),
Octopath Traveler (Vulkan), and Rise of the Tomb Raider (Vulkan) are
helped.

The lost / gained shaders in OpenGL are an Aztec Ruins shader that goes
from SIMD16 to SIMD8. The spills / fills affected are in a single Aztec
Ruins (Vulkan) compute shader.

shader-db results:

Skylake, Ice Lake, and Tiger Lake had similar results. (Tiger Lake shown)
total loops in shared programs: 5514 -> 5470 (-0.80%)
loops in affected programs: 62 -> 18 (-70.97%)
helped: 37 / HURT: 0

LOST:   2
GAINED: 2

Haswell and Broadwell had similar results. (Broadwell shown)
total loops in shared programs: 5346 -> 5298 (-0.90%)
loops in affected programs: 66 -> 18 (-72.73%)
helped: 39 / HURT: 0

fossil-db results:

Skylake, Ice Lake, and Tiger Lake had similar results. (Tiger Lake shown)
Instructions in all programs: 157374679 -> 157397421 (+0.0%)
Instructions hurt: 28

SENDs in all programs: 7463800 -> 7467639 (+0.1%)
SENDs hurt: 28

Loops in all programs: 38980 -> 38950 (-0.1%)
Loops helped: 28

Cycles in all programs: 7559486451 -> 7557455384 (-0.0%)
Cycles helped: 28

Spills in all programs: 11405 -> 11403 (-0.0%)
Spills helped: 1

Fills in all programs: 19578 -> 19588 (+0.1%)
Fills hurt: 1

Lost: 1

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/loop_analyze: Track induction variables incremented by more operations

These operations are covered:

 - imul
 - fmul
 - ishl
 - ishr
 - ushr

The only cases that can be currently affected are those where the
calculated loop-trip count would be zero.

v2 (idr): Split out from original commit. Rebase on lots of other work.

v3 (idr): Move operand size assertion. This code only cares that the
operands have the same size for the iadd and fadd cases. In other
cases, such as shifts, the sizes may not match. Fixes assertion
failures in
tests/spec/arb_gpu_shader_int64/glsl-fs-loop-unroll-ishl-int64.shader_test.

No shader-db or fossil-db changes on any Intel platform.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/loop_analyze: Use try_eval_const_alu and induction variable basis info

This dramatically simplifies will_break_on_first_iteration, and, much
more importantly, makes it significantly more flexible. It is now
possible to handle loops with more complex exit condition and other
kinds of increment operations.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/loop_analyze: Change invert_cond instead of changing the condition

This ensures that scenarios like
nir_loop_analyze_test.iadd_inot_ilt_rev_known_count_5 don't regress in
the next commit. It also means we don't change float comparisons. These
are probably fine... but it still made me a little uneasy.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/loop_analyze: Track induction variable basis information

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/loop_analyze: Add a function to evaluate an ALU as constant

...with a substitution. This function is largely a copy-and-paste of
try_fold_alu (nir_opt_constant_folding.c), and an argument could be made
that this function belongs in that file.

v2: Some changes were mistakenly squashed in to "nir/loop_analyze: Use
try_eval_const_alu and induction variable basis info" that should have
been here.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/tests: Add many loop analysis tests for induction variables modified by imul

Loop analysis doesn't currently treat values updated by multiplication
as induction variables. Future patches will change this.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/tests: Add more loop analysis tests for induction vars updated by shifts

These reverse the order of the comparison (e.g., -2 >= i vs i >= -2). I
split this into a separate commit because the previous commit was so
large.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

nir/tests: Add many loop analysis tests for induction vars updated by shifts

Loop analysis doesn't currently treat values updated by shifts as
induction variables. Future patches will change this.

v2: Don't use the contradiction ilt(x, INT_MIN).

v3: Delete some errant code in UNKNOWN_COUNT_TEST. Noticed by Tim.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3445>

radeonsi/vcn: set bitstream buffer size to encoded bitstream size

initial bitstream size was set to width * height * 2 which is
larger than yuv size. set initial bitstream size to encoded
bitstream size approximately to optimize memory consumption.
This is just an initial size setting, it will get resized later
if it's not big enough. As a result of this change, we don't need to
allocate super big size at the every beginning. Only allocate
big size when needed in order to save some memory

Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Acked-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21918>

dzn: Fix bindless descriptor sets with multiple dynamic buffers that need custom descriptors

Fixes: 5d2b4ee4 ("dzn: Allocate descriptor sets in buffers for bindless mode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Batch command lists together

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Don't do initial-layout barriers for simultaneous-access resources

Fixes: 4daeac01 ("dzn: Enhanced barriers fixes/workarounds")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Attempt to force depth write states for depth access in LAYOUT_GENERIC

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Ensure buffer offsets are aligned

If the app passes us unaligned buffer offsets, we need to align them
down to the nearest aligned offset, and then put the difference into
the descriptor set buffer.

Fixes: 8bd5fbf8 ("dzn: Bind buffers for bindless descriptor sets")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Don't use write-combine memory for cache-coherent UMA

Cache coherent UMA implies that the GPU is reading data through the
CPU caches. Using write-combined CPU pages for such a system would
be bad, since the GPU would then be reading uncached data. One
example of such a system is WARP. This significantly improves WARP's
performance for some apps (including the CTS).

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Ensure pipeline variants are used for dynamic stencil masks

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Align descriptor sets in the bindless buffer

Fixes: 5d2b4ee4 ("dzn: Allocate descriptor sets in buffers for bindless mode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Report some more caps correctly that are supported

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Raise max number of descriptor sets to 8

DOOM Eternal just assumes you support at least 5, which caused corruption
due to overrunning arrays. We can just bump this up. 8 should work with
and without bindless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Fix SRV barrier state on compute command lists

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Add a driconf option for enabling subgroup ops in VS/GS

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

dzn: Add a driconf entry for enabling 8bit loads and stores

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

spirv2dxil: Add some more supported caps

8-bit loads and stores work via lowering, but they do work

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

microsoft/compiler: Fix large shifts

Unlike DXBC, DXIL's shift instructions don't have the implicit behavior
that they only take the 5 bits. This is observable if you try to have
DXC do a shift of a dynamic value, e.g. a constant buffer value, where
the compiler inserts the appropriate 'and' op. We need to do the same.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

microsoft/compiler: Assign 1D wave IDs based on local thread ID

Fixes corruption/flickering seen in DOOM Eternal's decals/lighting.
It seems the shader has an implicit assumption about this property.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

microsoft/compiler: Fix barrier for wave ID computation

Fixes: 2f8a8b59 ("microsoft/compiler: Add lowering passes for basic subgroup vars")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

microsoft/compiler: Fix 8-bit loads and stores when supporting 16-bit DXIL

Shifts should always use 32bit shift values, and when lowering to
masked, we need to use 32-bit atomics. That means that we should also
treat 24bit stores as a single masked op rather than one 16bit unmasked
and one 8bit masked.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225>

glx: Fix error handling yet again in CreateContextAttribs

Unlike the legacy CreateContext path, we would try to send the
GLXCreateContextAttribs request regardless of whether we'd successfully
created the client context state. And there's not a lot on the server
side to go wrong besides BadAlloc, so if the request succeeded but
the client side didn't we'd need to destroy the server context and
synthesize an X error. Since that itself involves more X protocol it's
tricky to get the request number right in the error, and tests and apps
can notice when you get it wrong.

Since we have now fixed client-side validation to generate the right
errors at the right times, this patch does something simpler, we match
CreateContext and fail early if the client-side setup fails. Now there's
no question of what request number to use, because we haven't sent any
protocol, the error is for the request as if it'd been sent.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4763
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>

glx: Disable the indirect fallback in CreateContextAttribs

If your app cares enough to use CreateContextAttribs it's probably not
going to be happy with the pre-GL-1.5 indirect experience.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>

glx/dri: Fix error generation for invalid GLX_RENDER_TYPE

This needs to throw BadValue.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>

dri: Validate more of the context version in validate_context_version

There's two kinds of "bad version" you might encounter here, either the
combination does not name a defined version (like 1.7) or it names
something the driver can't do (like asking r300 to do 4.0). EGL does not
distinguish these cases, but GLX calls them BadMatch and GLXBadFBConfig
respectively.

Since api_mask is the set of driver supported APIs, and we can only
support defined APIs, don't check it early in driCreateContextAttribs,
just let it fall out from validate_context_version.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>

glx/dri: Use X/GLX error codes for our create_context_attribs

This has no functional change because everyone calling this is
discarding the error code, because we're relying on the server to
generate the right thing for us. But we create the direct context first
and the server isn't going to enforce everything we want it to
(supported GL versions for example). Convert out from DRI error codes to
X/GLX error codes so we can fail the right way on the client side. We're
still throwing the error away in all of the callers but that'll change
shortly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12006>

intel/fs: White space fixes

Trivial

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/fs: Preserve meta data more often in brw_nir_move_interpolation_to_top

This pass rarely makes any changes, so work a little harder to preserve
more meta data.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a debugoptimized build, improves
performance of Vulkan CTS "deqp-vk --deqp-case='dEQP-VK.*spir*'" by
-0.2% ± 0.1% (n = 5, pooled s = 0.431885).

v2: Add some parenthesis. Suggested by Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/fs: Linked list micro optimizations in brw_nir_move_interpolation_to_top

Two linked list management changes:

- Use the list head sentinel as the initial cursor. It is, after all, a
  proper node in the list.

- Iterate the list of blocks starting with the second block instead of
  skipping the first block in the loop.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a release build, improves
performance of compiling shaders from batman_arkham_city_goty.foz by
-0.24% ± 0.09% (n = 5, pooled s = 0.324106).

v2: Use nir_cursor instead of direct list manipultion. Suggested by
Lionel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/compiler: Micro optimize regions_overlap

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a release build, improves
performance of compiling shaders from batman_arkham_city_goty.foz by
-1.09% ± 0.084% (n = 5, pooled s = 0.354471)

Reduces the size of a release build by 26k.

   text    data     bss     dec     hex filename
23163641 400720  231360 23795721 16b1809 before/lib64/dri/iris_dri.so
23137264 400720  231360 23769344 16ab100 after/lib64/dri/iris_dri.so

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/fs: Use specialized version of regions_overlap in opt_copy_propagation

Since one of the register must always be either VGRF or FIXED_GRF, much
of regions_overlap and reg_offset can be elided.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a debugoptimized build, improves
performance of Vulkan CTS "deqp-vk --deqp-case='dEQP-VK.*spir*'" by
-0.29% ± 0.097% (n = 5, pooled s = 0.361697).

Using a release build, improves performance of compiling shaders from
batman_arkham_city_goty.foz by -3.3% ± 0.04% (n = 5, pooled s =
0.178312).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/compiler: Micro optimize inst_is_in_block

This function only exists in builds with assertions, so it only matters
there.

On my Ice Lake laptop (using a locked CPU speed and other measures to
prevent thermal throttling, etc.) using a debugoptimized build, improves
performance of Vulkan CTS "deqp-vk --deqp-case='dEQP-VK.*spir*'" by
-5.2% ± 0.16% (n = 5, pooled s = 0.657887).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/compiler: Use NIR_PASS instead of NIR_PASS_V

Reduce debug log spam by only logging the shader if a pass made some
changes. This can also elide some nir_validate calls in debug builds.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

intel/compiler: Remove one overload of backend_instruction::insert_before

The version that takes a list of instructions is not used. I did not do
any archaeology to find out when the last user was removed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22299>

etnaviv: don't read too much from uniform arrays

Fixes: 77af1ca690f ("etnaviv: add disk cache")
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: implement nir_op_uclz and lower find_{msb,lsb} to uclz

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: lower (un)pack_{2x16,2x32}_split and extract_{byte,word}

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: print writemask of store operations

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: handle missing alu conversion opcodes

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: add default clear_buffer and clear_texture APIS

These are required to support rusticl.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: use stderr for compiler error logging

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

etnaviv: abort() instead of assert(0) on compiler error

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22210>

amd/registers: use gfx9 packet definitions for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/registers: update gfx940.json

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/registers: fix the parser to include CP_COHER registers for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/registers: simplify integer division by 0x1000 in the parser

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: don't set registers that don't exist on gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: enable RGBA/ARGB formats on gfx940 jpeg

enable RGBA/ARGB format on gfx940 to aid RGBA/ARGB conversion after decode

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

frontends/va: support crop region in jpeg decode

propogate region of interest co-ordinates for crop region decode

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: reset to default value when ROI/FC is not used

when decoding without ROI/FC feature reset the registers to default value.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: Add decode support for gfx940

Add VCN decode for gfx940

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: Add video capabilities support for gfx940

Add VCN codec caps support for gfx940

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd/common: Add gfx940 codec query support

Add support for GFX940 VCN query

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: set jpeg reg version for gfx940

select appropriate jpeg register version for gfx940

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: support ARGB/RGBA conversion on JPEG 4.0.3

enable ARGB/RGBA conversion feature on JPEG 4.0.3

v2: fix regression caused due to uninitialized variable

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: add support for picture crop on JPEG 4.0.3

set the crop region and enable the feature if requested

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: use register versions for jpeg

update the register version and select appropriate registers during decoder create

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi/vcn: add register definitions for JPEG 4.0.3

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

ac/nir: fix CDNA image lowering for array textures

The x,y coordinates were not added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

ac/nir: implement image opcode emulation for CDNA, enable it in radeonsi

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: add an emulated image descriptor for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

ac/surface: force linear image layout for chips not supporting image opcodes

Image opcodes will be emulated.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: always use ffma32 on gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

radeonsi: use COMPUTE_DISPATCH_SCRATCH_BASE on gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd: add initial code for gfx940

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

amd: add gfx940 register definitions

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>

Revert "broadcom/ci: run gl jobs on arm64, just like vk"

This reverts commit ba4eeaf435f050dfec5472c7919b9b70e38d1bb8.

Looks like we have a lot of memory issues on arm64; revert the pre-merge
CI to armhf until we've been able to figure out the problem and fix it.

Closes https://gitlab.freedesktop.org/mesa/mesa/-/issues/8788

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22335>

nv50,nvc0: Use u_pipe_screen_get_param_defaults

Other than nouveau, every single Gallium driver relies on
u_pipe_screen_get_param_defaults to get the default values of CAPs.

For the driver, this is much more concise. Unsupported new features -- or
supported features that virtually all Gallium drivers support -- do not need to
written out explicitly. Their absence (or presence) is implied as the default.
If there's any doubt over whether the CAP is exposed, it's easy to check in
u_pipe_screen_get_param_defaults.

For the Gallium tree in general, this brings a number of benefits:

* Unused CAPs are easy to delete, because there is only a single place
  (u_pipe_screen_get_param_defaults) where they are referenced and need to be
  deleted from.

* New CAPs are easy to introduce, for the same reason.

* It's straightforward to audit which drivers support (or don't support) a given
  CAP by grepping for the name (for example, when determining whether a CAP is
  unused and can be garbage collected, or a CAP is so widely supported that it
  can be made default.). You still need to check the source code in case it's
  conditionally exposed (common for layered drivers) but the search space is
  limited to drivers that reference the CAP by name.

Unfortunately, all of these benefits rely on all Gallium drivers cooperating.
The status quo is much less nice:

* Unused CAPs need to be deleted both from common code, and also specially from
  nouveau. Why is nouveau special?

* New CAPs need to be added both to common code, and also specially to nouveau.
  Again, why is nouveau special?

* When grepping for CAPs, nouveau (only) needs to be ignored, since it's
  spurious.  Unless sometimes it's not, in which case you need to open nouveau
  source code anyway to check.

Compounding on the fun, you have to do the special nouveau step twice, once for
nvc0 and once for nv50.

Why might it be benefical to list CAPs explicitly instead of relying on the
defaults?

* Maybe easier auditing nouveau driver for CAP correctness? In practice this has
  not been an issue for any of the drivers I've worked on, especially because
  the defaults are quite reasonable.

* Maybe forcing people adding CAPs to think about nouveau specially? This isn't
  fair to the tree in general, why should nouveau get this special
  treatment? Instead, CAPs are generally added to gate functionality that may
  not be supported on all drivers, and the default is disabling the new
  functionality until a developer for a given driver can wire it up. There's
  already no expectation that the person adding CAPs needs to also add the
  functionality to nouveau (if that's even possible) -- unless the CAP is being
  added for the particular nouveau's benefit of course -- so this isn't helpful.

* Maybe forcing people removing CAPs to think about nouveau specially? Similar
  issues apply here, and it's not clear how this would even work.

* Maybe keeping novueau developers aware of CAP churn? Again nouveau should not
  be special here and it isn't sustainable to do this for every driver. So, if
  this is something that nouveau developers want to do -- and they choose not to
  follow Gallium-tagged merge requests -- then the git log of
  src/gallium/include/pipe/p_defines.h or indeed
  src/gallium/auxiliary/util/u_screen.c may be consulted.

So, without an excellent reason why nouveau should be treated specially, and
with several reasons why it should not, let's bring nouveau in line with the
rest of Gallium and rely on the defaults.

I've left in CAPs with attached comments even when they are returning the
default value to preserve information from before the commit. Otherwise, this
commit aims to remove explicit cases that match the default value, as other
drivers generally aim to do.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22245>

Revert "ci: disable Collabora's LAVA lab for maintance"

This reverts commit 86ad0356b6a8cc5f8b338cf7b92149b6e81f08e2.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22329>

intel/common: limit the amount of SLM with Wa_14017341140

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

anv,blorp,iris: Set PreferredSLMAllocationSize on gfx125+

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

intel/genxml: Add the preferred slm size enum for gen125

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

intel/genxml/125: Add preferred SLM allocation size field

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22307>

CI/windows: Increase timeout for build container job

These jobs can take upwards of 40 minutes just to upload
the built container images...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22320>

CI/windows: Update headers and Agility redist to 1.710.0-preview

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22320>

glsl: move some GL ES checks to the NIR linker

Eventually we should aim to remove the GLSL IR linker.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22305>

mesa: add _mesa_is_api_gles2() helper

The glsl compiler has been reworked to avoid passing gl_context around
so that we can avoid expensive recompiles across the code base for
minor changes. This helper will help us avoid passing gl_context around
where its otherwise unrequired.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22305>

ci: disable Collabora's LAVA lab for maintance

This is to inform you of some planned downtime in the LAVA lab as follows:

    Start: 2023-04-06 07:30 GMT
    End: 2023-04-06 09:00 GMT

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22185>

radv: disable tc_compatible_cmask on GFX9 in some cases

There seems to be issues when sample count > 2 on GFX9.  More precisely,
CTS has issues when sample count > 2.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>

radv: add RADV_FMASK_COMPRESSION_PARTIAL

RADV_FMASK_COMPRESSION_PARTIAL means the fmask is decompressed but not
expanded.  It is desired for sampling when the cmask is not
TC-compatible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>

radv: rework radv_layout_fmask_compressed

Rename radv_layout_fmask_compressed and make it return an enum.  We will
add partial compression (fmask decompressed and not expanded) in a
following commit.

Drop the check for VK_IMAGE_USAGE_STORAGE_BIT and
VK_IMAGE_USAGE_TRANSFER_DST_BIT.  When transitioning to
VK_IMAGE_LAYOUT_GENERAL, we should decompress and expand FMASK even when
those usage bits are not set.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21615>

ci/zink: Disable a630 portal-2-v2 due to kernel OOMs.

It's been popular for flakes due to oomkilling or kernel kmalloc failure
recently.  Is it ultimately the source of running out of memory?  Who
knows, but hopefully it's at least a big part of the problem.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

tgsi: Drop TGSI_OPCODE_DFRACEXP.

This is no longer emitted by nir_to_tgsi, so let's drop it.  This unlocks
some more TGSI DCE, since now all instructions have a single dest, but
that's a project for another day.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Drop PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED.

All drivers should now be using the appropriate NIR lowering, so we can
drop this pile of code.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

glsl: Drop frontend lowering of 32-bit frexp.

All the users should now be calling the appropriate NIR lowering function.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nir_to_tgsi: Always lower frexp_exp/sig.

The GLSL frontend was already lowering 32-bit frexp, so only 64-bit frexp
is possible as an op in the incoming NIR.  However, svga and nouveau don't
set PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED, leaving just r600's
non-default TGSI mode potentially using it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

panfrost/midgard: Enable nir_lower_frexp.

Needed for dropping the GLSL frontend lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

agx: Enable nir_lower_frexp.

Needed for Vulkan, and for dropping GLSL frontend lowering for the deqp
coverage override case.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

v3d: Lower frexp in the GL compiler like we do in Vulkan.

Needed for dropping GLSL's frontend lowering.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

zink: Enable nir_lower_frexp.

This will enable GLSL to drop its frexp lowering in the frontend.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nouveau: Enable frexp lowering in the backend.

This would be desired for NVK using this backend, but also for getting
lowering out of the GLSL frontend.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

nouveau: Add missing nir_opt_algebraic_late.

This was needed for nir_lower_frexp, but it's a win anyway.  shader-db
results:

total gpr in shared programs: 1143621 -> 1143502 (-0.01%)
gpr in affected programs: 33918 -> 33799 (-0.35%)

total instructions in shared programs: 7829415 -> 7820124 (-0.12%)
instructions in affected programs: 1204967 -> 1195676 (-0.77%)

total bytes in shared programs: 71802760 -> 71717352 (-0.12%)
bytes in affected programs: 11031888 -> 10946480 (-0.77%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>

ir3: Move turnip's nir_lower_frexp to the shared compiler.

We had NIR lowering for Vulkan, and rely on GLSL's lowering in the
frontend, but this will let us drop the GLSL lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22083>