Simon Glass [Sat, 22 Jan 2022 12:07:24 +0000 (05:07 -0700)]
mmc: fsl: Use brackets around if()
At present the IS_ENABLED() macro has extra brackets, making it possible
to write:
if IS_ENABLED(CONFIG_XXX)
but it is a bit confusing. Add the missing brackets.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Simon Glass [Sat, 22 Jan 2022 12:07:23 +0000 (05:07 -0700)]
mips: Avoid using config_enabled() directly
Use IS_ENABLED() instead, which is the correct macro for checking a CONFIG
option.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 22 Jan 2022 12:07:22 +0000 (05:07 -0700)]
imx: Don't define __ASSEMBLY__ in source files
This is supposed to be a build-system flag. Move it there so we can
define it before linux/kconfig.h is included.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 8 Feb 2022 17:28:04 +0000 (12:28 -0500)]
Merge branch '2022-02-08-TI-platform-updates'
- J721S2 support, IPU support on DRA7, SIERRA PHY mulitlink
configuration support, Nokia RX-51 DM_KEYBOARD conversion
Pali Rohár [Thu, 3 Feb 2022 18:38:50 +0000 (19:38 +0100)]
Nokia RX-51: Convert to CONFIG_DM_KEYBOARD
Signed-off-by: Pali Rohár <pali@kernel.org>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:52 +0000 (13:41 +0530)]
include: configs: j721e_evm: Add support to boot ethfw core in j721e
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:51 +0000 (13:41 +0530)]
arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:50 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add support for skipping configuration
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:49 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:48 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add support for PHY multilink configurations
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:47 +0000 (13:41 +0530)]
phy: cadence: Sierra: Update single link PCIe register configuration
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:46 +0000 (13:41 +0530)]
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:45 +0000 (13:41 +0530)]
phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:44 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add PHY PCS common register configurations
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:43 +0000 (13:41 +0530)]
phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:42 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add support to get SSC type from device tree.
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:41 +0000 (13:41 +0530)]
dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
Add binding to specify Spread Spectrum Clocking mode used
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:40 +0000 (13:41 +0530)]
phy: cadence: Sierra: Prepare driver to add support for multilink configurations
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:39 +0000 (13:41 +0530)]
arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:38 +0000 (13:41 +0530)]
board: ti: j721e: evm.c: Add support for probing SerDes0
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:37 +0000 (13:41 +0530)]
phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:36 +0000 (13:41 +0530)]
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 28 Jan 2022 08:11:35 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add a UCLASS_PHY device for links
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Kishon Vijay Abraham I [Fri, 28 Jan 2022 08:11:34 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Kishon Vijay Abraham I [Fri, 28 Jan 2022 08:11:33 +0000 (13:41 +0530)]
phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Kishon Vijay Abraham I [Fri, 28 Jan 2022 08:11:32 +0000 (13:41 +0530)]
phy: cadence: Sierra: Move all reset_control_get*() to a separate function
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Kishon Vijay Abraham I [Fri, 28 Jan 2022 08:11:31 +0000 (13:41 +0530)]
phy: cadence: Sierra: Move all clk_get_*() to a separate function
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Kishon Vijay Abraham I [Fri, 28 Jan 2022 08:11:30 +0000 (13:41 +0530)]
phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Kishon Vijay Abraham I [Fri, 28 Jan 2022 08:11:29 +0000 (13:41 +0530)]
phy: cadence: Sierra: Fix PHY power_on sequence
Commit
39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Sanket Parmar [Fri, 28 Jan 2022 08:11:28 +0000 (13:41 +0530)]
phy: cadence: sierra: Fix for USB3 U1/U2 state
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar <sparmar@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Keerthy [Thu, 27 Jan 2022 12:17:00 +0000 (13:17 +0100)]
dts: am57xx*: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:59 +0000 (13:16 +0100)]
arm: dts: dra7*/am57xx-idk-evm-u-boot: Add ipu early boot DT changes
Add support for ipu early boot.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:58 +0000 (13:16 +0100)]
arm: dts: dra7: Add ipu and related nodes
Add ipu and the associated nodes.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:57 +0000 (13:16 +0100)]
dts: dra7-ipu-common-early-boot.dtsi: Add all the ipu early boot related nodes
Add all the ipu early boot related nodes
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:56 +0000 (13:16 +0100)]
remoteproc: ipu: Add driver to bring up ipu
The driver enables IPU support. Basically enables the clocks,
timers, watchdog timers and bare minimal MMU and supports
loading the firmware from mmc.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix compile warnings]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:55 +0000 (13:16 +0100)]
remoteproc: uclass: Add remoteproc resource handling helpers
Add remoteproc resource handling helpers. These functions
are primarily to parse the resource table and to handle
different types of resources. Carveout, devmem, trace &
vring resources are handled.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix redefinition of "struct resource_table" and compile warnings ]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:54 +0000 (13:16 +0100)]
linux: bitmap.h: Add find_next_zero_area function
Add find_next_zero_area to fetch the next zero area in the map.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:53 +0000 (13:16 +0100)]
drivers: misc: Makefile: Enable fs_loader compilation at SPL Level
Enable fs_loader compilation at SPL Level.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix compilation failures for J721e platform]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:52 +0000 (13:16 +0100)]
arm: mach-omap2: load/start remoteproc IPU1/IPU2
First check the presence of the ipu firmware in the boot partition.
If present enable the ipu and the related clocks & then move
on to load the firmware and eventually start remoteproc IPU1/IPU2.
do_enable_clocks by default puts the clock domains into auto
which does not work well with reset. Hence adding do_enable_ipu_clocks
function.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix IPU1_LOAD_ADDR and compile warnings]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:51 +0000 (13:16 +0100)]
reset: dra7: Add a reset driver
Add a reset driver to bring IPs out of reset.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Amjad Ouled-Ameur [Thu, 27 Jan 2022 12:16:50 +0000 (13:16 +0100)]
configs: dra7xx_evm: Increase the size of SPL_MULTI_DTB_FIT
Expand SPL_MULTI_DTB_FIT to accommodate new SPL IPU nodes.
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Bryan Brattlof [Wed, 26 Jan 2022 22:07:33 +0000 (16:07 -0600)]
soc: soc_ti_k3: update j721e revision numbering
There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.
CC: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:46 +0000 (20:56 +0530)]
configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig
Enable A72 specific configs for J721S2
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:45 +0000 (20:56 +0530)]
configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig
Enable R5 SPL specific configs for J721S2.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:44 +0000 (20:56 +0530)]
arm: dts: k3-j721s2-ddr: Add DDR support
J721S2 can support two instances for DDR. Therefore, add the device support
for the same and use 4266MT/s as DDR frequency.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:43 +0000 (20:56 +0530)]
arm: dts: k3-j721s2: Add r5 specific dt support
Add initial support for device tree that runs on R5.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:42 +0000 (20:56 +0530)]
arm: dts: Add support for A72 specific J721S2 Common Processor Board
The EVM architecture for J721S2 is similar to that of J721E and J7200. It
is as follows,
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.
Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:41 +0000 (20:56 +0530)]
arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:40 +0000 (20:56 +0530)]
arm: dts: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:39 +0000 (20:56 +0530)]
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
Add pinctrl macros for J721S2 SoC. These macro definitions are
similar to that of J721E, but adding new definitions to avoid
any naming confusions in the soc dts files.
checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:38 +0000 (20:56 +0530)]
dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES
lane mux can select upto 4 different IPs. Define all the possible
functions.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:37 +0000 (20:56 +0530)]
board: ti: j721s2: Add board support for J721S2
Add board support for J721S2 SoC.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:36 +0000 (20:56 +0530)]
soc: ti: k3-socinfo: Add entry for J721S2 SoC
Add support for J721S2 SoC identification.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:35 +0000 (20:56 +0530)]
ram: k3-ddrss: Add support for J721S2 SoC
Add support for DDR subsystem in J721S2 SoC.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:34 +0000 (20:56 +0530)]
power: domain: ti: Add support for J721S2 SoC
Add support for J721S2 SoC.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
David Huang [Tue, 25 Jan 2022 15:26:33 +0000 (20:56 +0530)]
clk: clk-k3: Add support for J721S2 SoC
Add support for J721S2 SoC.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:32 +0000 (20:56 +0530)]
drivers: dma: Add support for J721S2
Add support for DMA in J721S2 SoC.
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
David Huang [Tue, 25 Jan 2022 15:26:31 +0000 (20:56 +0530)]
arm: K3: Add basic support for J721S2 SoC definition
Add basic support for J721S2 SoC definition
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:30 +0000 (20:56 +0530)]
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems
In Multi DDR subystems with interleaving support, the following needs to
configured,
- interleaving granular size and region
- EMIFs to be enabled
- EMIFs with ecc to be enabled
- EMIF separated or interleaved
- number of cycles of unsuccessful EMIF arbitration to wait before
arbitrating for a different EMIF port, by default set to 3
Add support for configuring all the above by using a MSMC device
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:29 +0000 (20:56 +0530)]
ram: k3-ddrss: Add support for multiple instances of DDR subsystems
The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Tue, 25 Jan 2022 15:26:28 +0000 (20:56 +0530)]
ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for
supporting mutliple instances of DDR in the drivers.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Nishanth Menon [Tue, 25 Jan 2022 15:26:27 +0000 (20:56 +0530)]
remoteproc: k3_system_controller: Support optional boot_notification channel
If there is an optional boot notification channel that an SoC uses
separate from the rx path, use the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Tom Rini [Mon, 7 Feb 2022 17:13:53 +0000 (12:13 -0500)]
Merge tag 'u-boot-imx-
20220207' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-
20211022
-------------------
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/10887
- imx8 : Toradex Verdin MX8M Plus
Kontron pitx-imx8m
- imx8ulp: several fixes and improvements
- imx6ull fixes
- switching to binman
Oleksandr Suvorov [Mon, 7 Feb 2022 12:19:18 +0000 (14:19 +0200)]
apalis/colibri_imx6: move setting bootcmd to defconfig
Move setting the default boot command to the
apalis/colibri_imx6_defconfig. It allows replacing the command
without code modification.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marcel Ziswiler [Mon, 7 Feb 2022 10:54:13 +0000 (11:54 +0100)]
board: toradex: add verdin imx8m plus support
This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB
IT V1.0B module. They are strapped to boot from eFuses which are factory
fused to properly boot from their on-module eMMC. U-Boot supports
booting from the on-module eMMC only, SDP support is disabled for now
due to missing i.MX 8M Plus USB support.
Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet both on-module eQoS and FEC (requires PHY on carrier board)
- GPIOs
- I2C
Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper
ATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.
Boot:
U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
Quad die, dual rank failed, attempting dual die, single rank configuration.
Normal Boot
WDT: Started watchdog@
30280000 with servicing (60s timeout)
Trying to boot from BOOTROM
Find img info 0x&
48025a00, size 872
Need continue download 1024
Download 779264, Total size 780424
NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
NOTICE: BL31: Built : 16:52:37, Aug 26 2021
U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
CPU: Freescale i.MX8MP[8] rev1.1 at 1200 MHz
Reset cause: POR
DRAM: 8 GiB
Core: 78 devices, 18 uclasses, devicetree: separate
WDT: Started watchdog@
30280000 with servicing (60s timeout)
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial#
06817281
Carrier: Toradex Verdin Development Board V1.1A, Serial#
10807609
Setting variant to wifi
Net: Hard-coding pdata->enetaddr
eth1: ethernet@
30be0000, eth0: ethernet@
30bf0000 [PRIME]
Hit any key to stop autoboot: 0
Verdin iMX8MP #
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tom Rini [Sat, 5 Feb 2022 21:16:38 +0000 (16:16 -0500)]
Merge tag 'efi-2022-04-rc2-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2022-04-rc2-2
UEFI
* add unit test for RISCV_EFI_BOOT_PROTOCOL
* disable UEFI for Colibri VF610
* add handle for UART
* fix printing of Unicode strings
* simplify enumeration of block devices
Heinrich Schuchardt [Sat, 5 Feb 2022 19:10:03 +0000 (20:10 +0100)]
tools: mkeficapsule: dont use malloc.h
malloc() functions are declared via stdlib.h. Including malloc.h can lead
to build errors e.g. on OS-X.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Simon Glass [Sat, 29 Jan 2022 21:58:39 +0000 (14:58 -0700)]
efi: Drop unnecessary calls to blk_find_device()
When we have the block descriptor we can simply access the device. Drop
the unnecessary function call.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Sat, 29 Jan 2022 21:58:38 +0000 (14:58 -0700)]
efi: Use device_get_uclass_id() where appropriate
Use this function rather than following the pointers, since it is there
for this purpose.
Add the uclass name to the debug call at the end of dp_fill() since it is
quite useful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Sat, 29 Jan 2022 21:58:37 +0000 (14:58 -0700)]
efi: Add debugging to efi_set_bootdev()
The operation of this function can be confusing. Add some debugging so
we can see what it is doing and when it is called.
Also drop the preprocessor usage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Fri, 4 Feb 2022 19:47:09 +0000 (20:47 +0100)]
efi_loader: add handle for UART
When loading an EFI binary via the UART we assign a UART device path to it.
But we lack a handle with that device path.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Fri, 4 Feb 2022 15:36:49 +0000 (16:36 +0100)]
efi_loader: fix text output for Uart() DP nodes
The UEFI specification concerning Uart() device path nodes has been
clarified:
Parity and stop bits can either both use keywords or both use
numbers but numbers and keywords should not be mixed.
Let's go for keywords as this is what EDK II does. For illegal
values fall back to numbers.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Thu, 3 Feb 2022 19:13:17 +0000 (20:13 +0100)]
efi_loader: use %zu to print efi_uintn_t in FMP driver
For printing an unsigned value we should use %u and not %d.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Thu, 3 Feb 2022 21:21:51 +0000 (22:21 +0100)]
efi_loader: use %zu not %zd to print efi_uintn_t
efi_uintnt_t is an unsigned type. We should avoid showing negative numbers.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 29 Jan 2022 18:01:07 +0000 (19:01 +0100)]
efi_loader: fix device path to text protocol
The printing of a file path node must properly handle:
* odd length of the device path node
* UTF-16 character only partially contained in device path node
* buffer overflow due to very long file path
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 29 Jan 2022 17:28:08 +0000 (18:28 +0100)]
test: test UTF-16 truncation in snprintf()
Check that snprintf() returns the correct required buffer length and prints
the correct string for UTF-16 strings.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 29 Jan 2022 15:43:20 +0000 (16:43 +0100)]
lib: fix snprintf() for UTF-16 strings
snprintf() must return the required buffer length.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Sat, 5 Feb 2022 07:45:55 +0000 (08:45 +0100)]
efi_selftest: merge FDT and RISC-V tests
The test for the RISCV_EFI_BOOT_PROTOCOL retrieves the boot hart id via the
protocol and compares it to the value of the boot hart id in the device
tree. The boot hart id is already retrieved from the device tree in the FDT
test.
Merge the two tests to avoid code duplication.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Sunil V L [Fri, 28 Jan 2022 15:18:45 +0000 (20:48 +0530)]
efi_selftest: unit test for RISCV_EFI_BOOT_PROTOCOL
Add a test for the RISCV_EFI_BOOT_PROTOCOL.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Heinrich Schuchardt [Fri, 14 Jan 2022 22:29:09 +0000 (23:29 +0100)]
configs: disable UEFI for Colibri VF610
The size of the board file is limited to 520192 bytes. This conflicts with
the size requirement for the UEFI code.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Marek Vasut [Sun, 28 Nov 2021 02:52:35 +0000 (03:52 +0100)]
ARM: imx6: dh-imx6: Add update_sf script to install U-Boot into SF
Add script to read U-Boot from SD card and write it to matching
locations in the SPI NOR, thus making the SPI NOR bootable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Heiko Thiery [Mon, 31 Jan 2022 16:30:45 +0000 (17:30 +0100)]
board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board support
The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Angus Ainslie [Wed, 2 Feb 2022 22:22:00 +0000 (14:22 -0800)]
mach-imx: iomux-v3: add a define for the SION bit
SION (Software Input On Field) - force the select mode input path
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Angus Ainslie [Wed, 2 Feb 2022 15:31:43 +0000 (07:31 -0800)]
arm: dts: imx8mq kernel dts updates
Update to the 5.16 imx8mq dts files and dt bindings
Changes since v1:
Dropped rfkill.h that is not in linux mainline yet.
Signed-off-by: Angus Ainslie <angus@akkea.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Dario Binacchi [Mon, 31 Jan 2022 07:50:06 +0000 (08:50 +0100)]
mx6: crm_regs: drop BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ
Commit
97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting")
made this macro unused. Then remove it.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Dario Binacchi [Mon, 31 Jan 2022 07:50:05 +0000 (08:50 +0100)]
imx: mx6ull: fix REFTOP_VBGADJ setting
The previous code wrote the contents of the fuse as is in the
REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of
the table in the code comment. This table is also different from the
table in the commit description. But then, which of the two is correct?
If it is assumed that an unprogrammed fuse has a value of 0 then for
backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to
6 (b'110). Therefore, the table in the code comment can be considered
correct as well as this patch.
Fixes:
97c16dc8bf098 ("imx: mx6ull: update the REFTOP_VBGADJ setting")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Heiko Thiery [Sun, 30 Jan 2022 06:38:14 +0000 (07:38 +0100)]
configs/*imxrt10*: remove [SPL_]CLK_COMPOSITE_CCF
This option is selected implicitly when [SPL_]CLK_IMXRT10{20|50} is selected.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Heiko Thiery [Sun, 30 Jan 2022 06:38:12 +0000 (07:38 +0100)]
clk: imx: select [SPL_]CLK_COMPOSITE_CCF for imxrt10{20|50}
The clock composite is required when using the clock framework. So
select it automatically.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Richard Zhu [Fri, 28 Jan 2022 03:41:04 +0000 (04:41 +0100)]
arm64: dts: imx8mm: Add the pcie support
Add the PCIe support on i.MX8MM platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux 854a4766ac12 ("arm64: dts: imx8mm: Add the pcie support")
Richard Zhu [Fri, 28 Jan 2022 03:41:03 +0000 (04:41 +0100)]
arm64: dts: imx8mm: Add the pcie phy support
Add the PCIe PHY support on iMX8MM platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux b9ec888f636f ("arm64: dts: imx8mm: Add the pcie phy support")
Richard Zhu [Fri, 28 Jan 2022 03:41:02 +0000 (04:41 +0100)]
dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy
Add binding for reference clock PAD modes of the i.MX8 PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1638432158-4119-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux f6f787874aa5 ("dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy")
Adam Ford [Thu, 27 Jan 2022 21:10:01 +0000 (15:10 -0600)]
imx: imx8mn_beacon: Remove redundant code
The function to return the default MMC device for the environment
already has a __weak instance doing exactly the same thing. Remove
the superfluous one.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Thu, 27 Jan 2022 21:10:00 +0000 (15:10 -0600)]
imx: imx8mm_beacon: Remove redundant code
The function to return the default MMC device for the environment
already has a __weak instance doing exactly the same thing. Remove
the superfluous one.
Signed-off-by: Adam Ford <aford173@gmail.com>
Oliver Graute [Wed, 26 Jan 2022 21:56:07 +0000 (22:56 +0100)]
imx: imx8qm_rm7720: adjust fdt_addr
The Linux Kernel Image size for arm64 is still growing.
A Kernel with 54 MB at load address 0x80280000 overlaps
with fdt_addr at 0x83000000. So let's increase it to 0x84000000
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Oliver Graute [Wed, 26 Jan 2022 21:55:08 +0000 (22:55 +0100)]
imx: imx8qm_rom7720: Increase CONFIG_SYS_BOOTM_LEN to 64MB
Increase CONFIG_SYS_BOOTM_LEN to 64MB
Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
Adam Ford [Wed, 26 Jan 2022 18:25:23 +0000 (12:25 -0600)]
imx: imx8mn_beacon: Fix USB booting
The i.MX8M Nano can boot over USB using the boot ROM instead of
adding extra code to SPL to support USB drivers, etc. However,
when booting from USB, the environment doesnt' know where to load
and causes a hang. Fix this hang by supporting CONFIG_ENV_IS_NOWHERE=y.
It only falls back to this condition when booting from USB, so it
does not impact MMC booting.
Suggested-by: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Ying-Chun Liu (PaulLiu) [Wed, 26 Jan 2022 12:33:02 +0000 (20:33 +0800)]
arm: dts: add imx8mp-rsb3720-a1 dts file
Add board dts for Advantech's imx8mp-rsb3720-a1
Signed-off-by: Darren Huang <darren.huang@advantech.com.tw>
Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw>
Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw>
Signed-off-by: Tim Liang <tim.liang@advantech.com.tw>
Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
Marek Vasut [Tue, 25 Jan 2022 02:49:22 +0000 (03:49 +0100)]
arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B
The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020
documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the
pinmux tables.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Oliver Stäbler [Tue, 25 Jan 2022 02:48:54 +0000 (03:48 +0100)]
arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
Fix address of the pad control register
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
to be a typo but it leads to an exception when pinctrl is applied due to
wrong memory address access.
Signed-off-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Fixes:
c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
Fixes:
748f908cc882 ("arm64: add basic DTS for i.MX8MQ")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Picked from Linux 5cfad4f45806f ("arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0")
Marek Vasut [Tue, 25 Jan 2022 02:48:06 +0000 (03:48 +0100)]
ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options
Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs
in case they should be operated faster, e.g. to improve boot time.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>