Sander de Smalen [Wed, 15 Mar 2023 09:21:48 +0000 (09:21 +0000)]
[AArch64][SVE] Fix the indexed addressing mode when FI = 0.
This is an alternative fix to D145497, which also addresses
https://github.com/llvm/llvm-project/issues/60918
In D124457 which added the original code for this, @efriedma pointed
out that it wasn't safe to assume that FI #0 would be allocated at offset
0, but that part of the patch went in without any changes.
The downside of this solution is that any access to an object on the
stack that has been allocated at SP + 0, still gets moved to a separate
register first, which degrades performance.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D146056
Carlos Alberto Enciso [Wed, 15 Mar 2023 13:30:24 +0000 (13:30 +0000)]
[llvm-debuginfo-analyzer] README
llvm-debuginfo-analyzer is a command line tool that processes debug
info contained in a binary file and produces a debug information
format agnostic “Logical View”, which is a high-level semantic
representation of the debug info, independent of the low-level
format.
https://discourse.llvm.org/t/llvm-dev-rfc-llvm-dva-debug-information-visual-analyzer/62570
This patch:
Contains notes collected during the development, review and test.
It describes limitations, know issues and future work.
Reviewed By: Orlando
Differential Revision: https://reviews.llvm.org/D144857
Simon Pilgrim [Wed, 15 Mar 2023 13:22:16 +0000 (13:22 +0000)]
[DAG] TargetLowering::ShrinkDemandedOp - rename Demanded arg to DemandedBits. NFC
Make it clear this is referring to DemandedBits not DemandedElts.
Igor Kushnir [Wed, 15 Mar 2023 13:21:41 +0000 (09:21 -0400)]
[libclang] Add index option to store preambles in memory
This commit allows libclang API users to opt into storing PCH in memory
instead of temporary files. The option can be set only during CXIndex
construction to avoid multithreading issues and confusion or bugs if
some preambles are stored in temporary files and others - in memory.
The added API works as expected in KDevelop:
https://invent.kde.org/kdevelop/kdevelop/-/merge_requests/283
Differential Revision: https://reviews.llvm.org/D145974
Matthias Springer [Wed, 15 Mar 2023 10:49:55 +0000 (11:49 +0100)]
[mlir][Transforms] OperationFolder: Remove redundant `create` API
These functions are available on the `OpBuilder` API.
Differential Revision: https://reviews.llvm.org/D146126
Nicolas Vasilache [Tue, 14 Mar 2023 21:37:58 +0000 (14:37 -0700)]
[mlir][Transform] NFC - Refactor forall mapping to threads and blocks into one thing
Differential Revision: https://reviews.llvm.org/D146095
Simon Pilgrim [Wed, 15 Mar 2023 11:36:00 +0000 (11:36 +0000)]
[DAG] mergeStore - peek through truncates when finding dead store(trunc(load())) patterns
Extend the existing store(load()) removal code to account for intermediate truncates that some targets won't remove with canCombineTruncStore - we only care about the load/store MemoryVT.
Fixes regression from D146121
Jonas Paulsson [Wed, 8 Feb 2023 18:37:47 +0000 (19:37 +0100)]
[Clang] Give warning for an underaligned 128-bit __sync library call.
On SystemZ, int128 values are generally aligned to only 8 bytes per the ABI
while 128 bit atomic ISA instructions exist with a full 16 byte alignment
requirement.
__sync builtins are emitted as atomicrmw instructions which always require
the natural alignment (16 bytes in this case), and they always get it
regardless of the alignment of the value being addressed.
This patch improves this situation by giving a warning if the alignment is
not known to be sufficient. This check is done in CodeGen instead of in Sema
as this is currently the only place where the alignment can be computed. This
could/should be moved into Sema in case the alignment computation could be
made there eventually.
Reviewed By: efriedma, jyknight, uweigand
Differential Revision: https://reviews.llvm.org/D143813
Shao-Ce SUN [Wed, 15 Mar 2023 05:06:10 +0000 (13:06 +0800)]
[Flang][RISCV] Emit target features for RISC-V
Fix the issue of .o file generated by `Flang`
with `Flags` info is 0x0 under RISC-V.
Reviewed By: awarzynski, kiranchandramohan
Differential Revision: https://reviews.llvm.org/D145883
Tom Stellard [Wed, 15 Mar 2023 11:19:01 +0000 (04:19 -0700)]
lit: Fix formatting in README.rst
This was preventing lit from being uploaded to pypi.
Reviewed By: mgorny
Differential Revision: https://reviews.llvm.org/D143419
Matt Arsenault [Mon, 6 Feb 2023 15:49:50 +0000 (11:49 -0400)]
InstCombine: Handle folding fcmp of 0 into llvm.is.fpclass
This needs to consider the denormal mode.
Matt Arsenault [Wed, 15 Feb 2023 09:27:34 +0000 (05:27 -0400)]
Reapply "InstCombine: Fold is.fpclass(x, fcZero) to fcmp oeq 0"
This reverts commit
458ad6900e6635e4640229d40e6f713147e52de7.
Archibald Elliott [Wed, 15 Mar 2023 10:38:11 +0000 (10:38 +0000)]
[AArch64] Assembly Support for FEAT_GCS/FEAT_CHK
This implements support for two new 2022 A-profile extensions:
- FEAT_CHK - Check Feature Status Extension
- FEAT_GCS - Guarded Control Stacks
FEAT_CHK is mandatory from armv8.0-a, but is in the hint space so
there's no clang command-line flag for it, and we only print the hint as
`chkfeat x16` at v8.9a and above, to be compatible when using a
non-integrated assembler that might not yet know about the extension.
FEAT_GCS is optional from armv9.4-a onwards. It is enabled using `+gcs`
in a clang `-march=` or `-mcpu=` option string, or using a
`.arch_extension gcs` assembly directive.
This patch includes changes by Ties Stuij, Tomas Matheson, and Keith
Walker.
Differential Revision: https://reviews.llvm.org/D145563
Alexey Lapshin [Mon, 27 Feb 2023 16:59:30 +0000 (17:59 +0100)]
[DWARFLinker][DWARFv5] Support debug_loclists.
This patch adds support of DWARFv5 .debug_loclists table.
As DWARFLinker resolves relocations, it is able to always
use DW_FORM_addr instead of DW_FORM_addrx. DW_FORM_addrx
helps to minimize number of relocations, it is also used for
split DWARF. Both of these cases are not relevant for the
DWARFLinker. Thus, this patch converts all DW_FORM_addrx
forms into the DW_FORM_addr. And, as the result, it converts
location lists of DW_FORM_loclistx form into the DW_FORM_sec_offset.
For the --update case all DW_FORM_addrx, DW_FORM_loclistx
are preserved as is.
Depends On D145499
Differential Revision: https://reviews.llvm.org/D145680
Kadir Cetinkaya [Wed, 15 Mar 2023 08:12:58 +0000 (09:12 +0100)]
[clangd] Respect WantDiags when emitting diags from possibly stale preambles
Differential Revision: https://reviews.llvm.org/D146116
David Spickett [Wed, 15 Mar 2023 09:56:39 +0000 (09:56 +0000)]
Reland "[lldb] Refactor CrashReason"
This reverts commit
71c4d186f1cf247f1aa45f4fd1b38f350b68d123.
The reinterpret casts were not needed.
JP Lehr [Wed, 15 Mar 2023 09:58:01 +0000 (05:58 -0400)]
[OpenMP][libomptarget][AMDGPU] Update print launch info
Clean up for the AMD-specific kernel launch info in the NextGen Plugins.
- Fixes a mistake introduced with the initial commit that added printing
of an AMD-only property.
- Removes another AMD-only property (not clear on upstream status)
- Adds some more comment to what info is printed.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D145924
Simon Pilgrim [Wed, 15 Mar 2023 09:56:22 +0000 (09:56 +0000)]
[DAG] Fold multiple insert_vector_elt of zero values into an AND mask
This also allows us to make use of the existing isVectorClearMaskLegal shuffle canonicalization
Differential Revision: https://reviews.llvm.org/D145939
David Spickett [Wed, 15 Mar 2023 09:54:47 +0000 (09:54 +0000)]
Revert "[lldb] Refactor CrashReason"
This reverts commit
af38530ee29c285f3827e33a41edf27c9c3a6767 due
to a build failure on 32 bit.
David Spickett [Thu, 9 Mar 2023 14:32:52 +0000 (14:32 +0000)]
[lldb] Refactor CrashReason
So that there is only one function that NativeThreads call,
which takes a siginfo. Everything else is an internal detail.
Reviewed By: labath, JDevlieghere
Differential Revision: https://reviews.llvm.org/D146043
Valentin Clement [Wed, 15 Mar 2023 09:37:56 +0000 (10:37 +0100)]
Revert "[flang] Load fir.ref<fir.class<T>> instead of creating a wrong box"
This reverts commit
fbca61c46612a6377b7d7cf5b56573df3c6759e2.
This is causing some issue. Revert for now.
Kito Cheng [Wed, 15 Mar 2023 09:23:42 +0000 (17:23 +0800)]
[libunwind][RISC-V] Rewrite testcase with C as possible.
Fix #60472
The testcase is writen in all inline asm but it seems not well
maintained for the CFI directive, of cause we can fix that, but this
patch also contain another issue is it use s0 and s1 without
store/restore.
This patch proposed another way to testing that, use inline asm to
generate dummy def and use, so compiler will generate store/restore for
the vector register, and then generate the CFI directives.
Also check __riscv_vector as the testcase guard, because the testcase
will read vlenb which is only available when V or zve* extensions is
present.
Reviewed By: MaskRay, asb, #libunwind
Differential Revision: https://reviews.llvm.org/D145225
Kito Cheng [Wed, 15 Mar 2023 09:21:25 +0000 (17:21 +0800)]
[RISCV] Pass vector argument by stack correctly.
We've a argument lowering logic to prevent floating-point value pass
passed with bit-conversion, but that rule should not applied to vector
arguments.
---
How to pass argument to `foo`:
```
tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer)
```
`foo` take 13 arguments, first 8 argument pass in GPR, and next 2 LMUL 8 vector
arguments passed in v8-v23, and now we run out of argument register for GPR and
vector register, so we must pass last LMUL 8 vector argument by stack.
Which means we should reserve `vlenb * 8` byte for stack for the last
vector argument.
Reviewed By: craig.topper, asb
Differential Revision: https://reviews.llvm.org/D145938
Kito Cheng [Wed, 15 Mar 2023 09:20:13 +0000 (17:20 +0800)]
[RISCV] Precommit test to show wrong way to pass scalable FP vector on stack
Test case to demo scaleable vector on stack will cause stack corruption.
Detail explan what happened:
```
tail call void @foo(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer,
<vscale x 16 x float> zeroinitializer)
```
`foo` take 13 arguments, first 8 argument pass in GPR, and next 2 LMUL 8 vector
arguments passed in v8-v23, and now we run out of argument register for GPR and
vector register, so we must pass last LMUL 8 vector argument by stack.
However LLVM only reserve 8 byte on stack for the LMUL 8 vector
argument, it will cause stack corruption when we try to store that into
stack.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D145934
Alexandros Lamprineas [Wed, 22 Feb 2023 21:53:44 +0000 (21:53 +0000)]
[FuncSpec] Minor refactoring in statistics and debug messages.
* Remove redundant variable `NbFunctionsSpecialized` as it is no longer
used by the cost model.
* Rename statistic `NumFuncSpecialized` to `NumSpecsCreated` as a better
description (the old name confusingly implied number of functions we have
created clones for).
* Same for variable `SpecializedFuncs`. Renamed to `Specializations`.
* Move debug message in the destructor (avoids repetition when MaxIters > 1).
Differential Revision: https://reviews.llvm.org/D145375
chenglin.bi [Wed, 15 Mar 2023 08:56:45 +0000 (16:56 +0800)]
[InstCombine] Remove one-use limit when it can simplify to a const in the pattern foldICmpUsingBoolRange
This patch follow up
dd31a3b3a5, when the pattern return a constant we needn't limit it to one-use.
chenglin.bi [Wed, 15 Mar 2023 08:28:25 +0000 (16:28 +0800)]
[InstCombine] Precommit tests for one-use check in icmp-range; NFC
Ben Shi [Thu, 9 Mar 2023 08:08:22 +0000 (16:08 +0800)]
[clang] Add AVR specific inline assembly escaped characters
Fixes https://github.com/llvm/llvm-project/issues/60204
Reviewed By: jacquesguan
Differential Revision: https://reviews.llvm.org/D145659
Jakub Chlanda [Fri, 3 Mar 2023 13:39:02 +0000 (14:39 +0100)]
[NVPTX] Expose LDU builtins
Also check if native half types are supported to give more descriptive
error message, without it clang only reports incorrect intrinsic return
type.
Differential Revision: https://reviews.llvm.org/D145238
pvanhout [Tue, 14 Mar 2023 07:46:05 +0000 (08:46 +0100)]
[AMDGPU] Use UniformityAnalysis in AtomicOptimizer
Adds & uses a new `isDivergentUse` API in UA.
UniformityAnalysis now requires CycleInfo as well as the new temporal divergence API can query it.
-----
Original patch that adds `isDivergentUse` by @sameerds
The user of a temporally divergent value is marked as divergent in the
uniformity analysis. But the same user may also have been marked divergent for
other reasons, thus losing this information about temporal divergence. But some
clients need to specificly check for temporal divergence. This change restores
such an API, that already existed in DivergenceAnalysis.
Reviewed By: sameerds, foad
Differential Revision: https://reviews.llvm.org/D146018
pvanhout [Fri, 24 Feb 2023 13:44:56 +0000 (14:44 +0100)]
[AMDGPU] Select v_sat_pk_u8_i16
The backend knew about `v_sat_pk_u8_i16` but never made use of it.
This patch adds selection patterns (DAG/GISel) for that instruction.
I think it'll be very rarely used, but at least it's possible to use it.
Solves #58266 (https://github.com/llvm/llvm-project/issues/58266)
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D144729
Matthias Springer [Wed, 15 Mar 2023 08:20:36 +0000 (09:20 +0100)]
[mlir][affine][analysis][NFC] Simplify FlatAffineConstraints API
* Remove `reset` function. Use copy assignment directly (instead of within `reset`).
* Fix potential `nullptr` dereference in `getFlattenedAffineExprs`.
* Make constraint set optional in `checkMemrefAccessDependence`.
Differential Revision: https://reviews.llvm.org/D145935
Kadir Cetinkaya [Tue, 14 Mar 2023 10:13:00 +0000 (11:13 +0100)]
[clangd] Patch main file macros in preamble
Depends on D146026
Fixes https://github.com/clangd/clangd/issues/1537.
Differential Revision: https://reviews.llvm.org/D146028
Kadir Cetinkaya [Tue, 14 Mar 2023 09:45:12 +0000 (10:45 +0100)]
[clangd] Patch PragmaMarks in preamble section of the file
Differential Revision: https://reviews.llvm.org/D146026
Max Kazantsev [Wed, 15 Mar 2023 07:21:11 +0000 (14:21 +0700)]
[NFC] Add some debug printouts to CaptureTracking
AdityaK [Wed, 15 Mar 2023 06:34:56 +0000 (23:34 -0700)]
[RISCV] Reserve X18 by default for Android
Reserve X18 even when -fsanitize=shadow-call-stack is not enabled.
Based on: https://reviews.llvm.org/D143355
Reviewed by: asb, samitolvanen, phosek, MaskRay
Differential Revision: https://reviews.llvm.org/D145999
Qiu Chaofan [Wed, 15 Mar 2023 06:21:52 +0000 (14:21 +0800)]
[Clang] Check feature requirement from inlined callee
Currently clang emits error when both always_inline and target
attributes are on callee, but caller doesn't have some feature.
This patch makes clang emit error when caller cannot meet target feature
requirements from an always-inlined callee.
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D143479
Kazu Hirata [Wed, 15 Mar 2023 06:09:18 +0000 (23:09 -0700)]
[polly] Use DenseMap::contains (NFC)
Matt Arsenault [Wed, 15 Mar 2023 05:53:19 +0000 (01:53 -0400)]
clang: Fix header tests for nofpclass
Kazu Hirata [Wed, 15 Mar 2023 05:20:33 +0000 (22:20 -0700)]
[flang] Use Use *{Set,Map}::contains (NFC)
Matt Arsenault [Tue, 28 Feb 2023 11:47:23 +0000 (07:47 -0400)]
clang: Handle MatrixType in hasFloatingRepresentation
Allows applying nofpclass to matrix arguments.
Matt Arsenault [Mon, 27 Feb 2023 23:56:00 +0000 (19:56 -0400)]
clang: Emit nofpclass(nan inf) for -ffinite-math-only
Set this on any source level floating-point type argument,
return value, call return or outgoing parameter which is lowered
to a valid IR type for the attribute. Currently this isn't
applied to emitted intrinsics since those don't go through
ABI code.
Matt Arsenault [Thu, 2 Mar 2023 12:22:07 +0000 (08:22 -0400)]
Attributor: Add baseline tests for nofpclass
Matt Arsenault [Tue, 28 Feb 2023 12:05:23 +0000 (08:05 -0400)]
clang: Add baseline test for nofpclass emission
Matt Arsenault [Wed, 1 Feb 2023 12:56:58 +0000 (08:56 -0400)]
CodeGen: Add some additional is_fpclass lowering tests
Cover more cases in preparation for making greater use
of fcmp based lowerings. Also add more tests for the inverted
cases. Test iszero | isnan test masks. We should probably just
generate every combination of test masks.
Kazu Hirata [Wed, 15 Mar 2023 04:48:49 +0000 (21:48 -0700)]
[mlir] Use Use *{Set,Map}::contains (NFC)
Kazu Hirata [Wed, 15 Mar 2023 04:41:40 +0000 (21:41 -0700)]
[lldb] Use *{Set,Map}::contains (NFC)
Kazu Hirata [Wed, 15 Mar 2023 04:30:29 +0000 (21:30 -0700)]
[clang-tools-extra] Use *{Set,Map}::contains (NFC)
Jie Fu [Wed, 15 Mar 2023 04:07:25 +0000 (12:07 +0800)]
[mlir] Fix two build warnings (NFC)
/data/llvm-project/mlir/lib/Dialect/Tensor/Utils/Utils.cpp:62:11: error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare]
if (dim >= shape.size())
~~~ ^ ~~~~~~~~~~~~
1 error generated.
/data/llvm-project/mlir/lib/Dialect/Tensor/IR/TensorTilingInterfaceImpl.cpp:484:8: error: unused variable 'appendIndex' [-Werror,-Wunused-variable]
auto appendIndex = [&](Value val, SmallVector<Value> &dynIndices,
^
1 error generated.
Mahesh Ravishankar [Wed, 15 Mar 2023 03:18:49 +0000 (03:18 +0000)]
[mlir][Tensor] Use folded evaluators in tiling implementation of `tensor.pad`.
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D145135
Jeff Bailey [Tue, 14 Mar 2023 14:53:03 +0000 (14:53 +0000)]
[libc] Add instructions for linux headers
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D146049
jinge90 [Wed, 15 Mar 2023 03:09:25 +0000 (11:09 +0800)]
Add __builtin_set_flt_rounds
This builtin will be converted to llvm.set.rounding intrinsic
in IR level and should be work with "#pragma STDC FENV_ACCESS ON"
since it changes default FP environment. Users can change rounding
mode via this builtin without introducing libc dependency.
Reviewed by: andrew.w.kaylor, rjmccall, sepavloff, aaron.ballman
Differential Revision: https://reviews.llvm.org/D145765
Signed-off-by: jinge90 <ge.jin@intel.com>
Jacob Lambert [Wed, 15 Mar 2023 02:40:33 +0000 (19:40 -0700)]
[clang-offload-bundler] Fix error with regex in bundler test
Fix recently introduced error and further generalize
pattern matching for accepted HOST string
Arthur Eubanks [Mon, 13 Mar 2023 17:03:09 +0000 (10:03 -0700)]
[Pipeline] Remove early InstCombine in ThinLTO post link sample profile pipeline
With opaque pointers, all function pointer types are the same, meaning there should be no bitcasts.
Internal benchmarks with SampleFDO look neutral.
This was added in D36333.
Reviewed By: tejohnson, davidxl
Differential Revision: https://reviews.llvm.org/D146099
Kazu Hirata [Wed, 15 Mar 2023 02:17:18 +0000 (19:17 -0700)]
[clang] Use *{Set,Map}::contains (NFC)
Jacob Lambert [Wed, 15 Mar 2023 02:05:59 +0000 (19:05 -0700)]
[clang-offload-bundler] Fix test failures and document typo
The recent bundler patch (e48ae0d) introduced a few errors
in two clang/Driver tests, and in the bundler documentation
Kazu Hirata [Wed, 15 Mar 2023 01:56:06 +0000 (18:56 -0700)]
[llvm] Use *{Set,Map}::contains (NFC)
Douglas Yung [Wed, 15 Mar 2023 01:33:55 +0000 (18:33 -0700)]
Mark test modified in e48ae0d as XFAIL for PS4/PS5 until the author can investigate.
The test is failing on the PS4/PS5 bots:
https://lab.llvm.org/buildbot/#/builders/139/builds/37475
https://lab.llvm.org/buildbot/#/builders/216/builds/18354
Uday Bondhugula [Sat, 18 Feb 2023 09:16:55 +0000 (14:46 +0530)]
[MLIR] Update/fix memref region computation for affine.parallel ops
When the affine.parallel op was introduced, affine utilities weren't
extended to handle it. Extending these is straightforward and natural
given that addAffineParallelOpDomain has also been added.
Update/complete memref region compute to account for affine.parallel
ops. Handle failure cleanly.
Add and expose utilities missing for affine.parallel to be consistent
with affine.for.
All of these allow various affine passes to work with a combination of
affine.parallel and affine.for ops.
Differential Revision: https://reviews.llvm.org/D145669
Kazu Hirata [Wed, 15 Mar 2023 01:06:55 +0000 (18:06 -0700)]
[Target] Use *{Set,Map}::contains (NFC)
David Blaikie [Wed, 15 Mar 2023 00:50:11 +0000 (00:50 +0000)]
Fix split-dwarf-dwp-invalid test to be Windows-path-separator compatible
Amir Ayupov [Wed, 15 Mar 2023 00:29:23 +0000 (17:29 -0700)]
[BOLT][NFC] Move addRelocation{X86,AArch64} into MCPlusBuilder
The two methods don't belong in BinaryFunction methods.
Move the dispatch tables into target-specific MCPlusBuilder methods.
Reviewed By: rafauler
Differential Revision: https://reviews.llvm.org/D131813
Ben Shi [Tue, 14 Mar 2023 03:59:55 +0000 (11:59 +0800)]
[RISCV][NFC] Combine identical switch cases in TTI
Reviewed By: craig.topper, asb
Differential Revision: https://reviews.llvm.org/D146008
Amir Ayupov [Wed, 15 Mar 2023 00:26:21 +0000 (17:26 -0700)]
[BOLT][NFC] Simplify MCPlusBuilder::getRegSize
Pre-calculate the register size table in MCPlusBuilder constructor,
similar to `AliasMap`/`SmallerAliasMap` in `initAliases`.
Reviewed By: #bolt, rafauler
Differential Revision: https://reviews.llvm.org/D145828
Frank Dischner [Wed, 15 Mar 2023 00:20:54 +0000 (17:20 -0700)]
[compiler-rt][builtins] Support builtins for armv8m.base
This allows building the compiler builtins library for the Armv8-M
Baseline architecture. It can be built in the same way as other
baremetal targets using the appropriate '--target' flag
(e.g. --target=armv8m.base-eabi).
NOTE: As with the other Cortex-M targets, only the builtins library is
supported. There is no support for sanitizers, etc.
The armv8m.base architecture is a superset of armv6m, so adding it to
the cmake files using thumb1_SOURCES is almost enough for it to compile.
Minor changes are needed to divsi3 and udivsi3, because armv8m.base does
have support for div instructions but not mov with an immediate operand.
Reviewed By: MaskRay, peter.smith
Differential Revision: https://reviews.llvm.org/D143297
Amir Ayupov [Tue, 14 Mar 2023 22:40:57 +0000 (15:40 -0700)]
[BOLT][NFC] Provide default impl for MIB methods that are only overridden on X86
Simplifies D145687
Reviewed By: #bolt, rafauler
Differential Revision: https://reviews.llvm.org/D145972
Frank Tetzel [Tue, 14 Mar 2023 23:25:37 +0000 (16:25 -0700)]
[lli] Register profiling support for ORC in lli
Adds perf event listeners when RTDyldObjectLinkingLayer is used in -jit-kind=orc
mode.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D126214
Michael Maitland [Wed, 15 Feb 2023 18:40:41 +0000 (10:40 -0800)]
[VPlan] VPWidenIntOrFpInductionRecipe inherits from VPHeaderPHIRecipe
Differential Revision: https://reviews.llvm.org/D144125
Lei Zhang [Tue, 14 Mar 2023 23:45:42 +0000 (23:45 +0000)]
[mlir][spirv] Fix UnifyAliasedResourcePass for 64-bit index
Reviewed By: kuhar
Differential Revision: https://reviews.llvm.org/D145079
Tom Stellard [Tue, 14 Mar 2023 23:51:21 +0000 (16:51 -0700)]
JITLink: Add missing EHFrame NULL terminator on aarch64/ELF
This fixes test failures on AArch64 with libgcc-13:
Clang :: Interpreter/global-dtor.cpp
Clang-Unit :: Interpreter/./ClangReplInterpreterTests/2/4
Reviewed By: lhames, v.g.vassilev
Differential Revision: https://reviews.llvm.org/D146067
Yeting Kuo [Mon, 6 Mar 2023 10:13:48 +0000 (18:13 +0800)]
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
The patch handles fixed type strict-fp by new RISCVISD::STRICT_ prefixed
isd nodes.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D145900
Shafik Yaghmour [Tue, 14 Mar 2023 23:27:55 +0000 (16:27 -0700)]
[Clang] Fix ClassifyImplicitMemberAccess to handle cases where the access in an unevaluated context is not within a CXXRecordDecl or CXXMethodDecl
ClassifyImplicitMemberAccess assumes that if we are not in a static context then
the DeclContext must be a CXXRecordDecl or a CXXMethodDecl. In the case of the
unevaluated context this may not be true.
This will lead to a crash because contextClass will remain a nullptr.
Fixes: https://github.com/llvm/llvm-project/issues/37792
Fixes: https://github.com/llvm/llvm-project/issues/48405
Differential Revision: https://reviews.llvm.org/D142490
NAKAMURA Takumi [Sat, 11 Feb 2023 18:42:09 +0000 (03:42 +0900)]
Let IntrinsicEmitter free from CodeGenTarget.h
For now, I have introduced `llvm::tmp::getValueType(Rec)` as a copy from
`CodeGenTarget.cpp`. This will be removed in the near future, when
IntrinsicEmitter will not depend on MVT.
Differential Revision: https://reviews.llvm.org/D143844
NAKAMURA Takumi [Sun, 12 Feb 2023 03:04:06 +0000 (12:04 +0900)]
llvm-tblgen: Split out CodeGenIntrinsics.cpp from CodeGenTarget.cpp
Differential Revision: https://reviews.llvm.org/D143844
NAKAMURA Takumi [Tue, 14 Mar 2023 23:06:57 +0000 (08:06 +0900)]
clang/test/Driver/clang-offload-bundler-standardize.c REQUIRES asserts. (fixup D145770)
Jorge Gorbe Moya [Tue, 14 Mar 2023 22:49:25 +0000 (15:49 -0700)]
[bazel][libc] Re-add dependency on errno to strtol_test_helper.
https://reviews.llvm.org/D146014 removed the dependency on errno from
several targets and added it to the `libc_test` macro. However,
strtol_test_helper is not a `libc_test` but a `cc_library` so it's
missing a dependency.
Fangrui Song [Tue, 14 Mar 2023 22:50:03 +0000 (15:50 -0700)]
[test] Improve MC/AArch64/elf-reloc-plt32.s to check defined symbol
Jakub Kuderski [Tue, 14 Mar 2023 22:47:33 +0000 (18:47 -0400)]
[mlir][spirv] Fix scf.yield pattern conversion
Only rewrite `scf.yield` when the parent op is supported by
scf-to-spirv.
Fixes: #61380, #61107, #61148
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D146080
Jakub Kuderski [Tue, 14 Mar 2023 22:35:24 +0000 (18:35 -0400)]
[mlir][spirv][NFC] Clean up scf-to-spirv pass
This is a clean up before fixing issues identified in this pass by
https://github.com/llvm/llvm-project/issues/61380 and similar issues.
- Move patterns definitions closer to declarations.
- Simplify pattern definitions.
- Drop hand-written pass constructor in favor of an auto-generated on.
- Fix typos in pass description.
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D146077
David Blaikie [Tue, 14 Mar 2023 22:43:53 +0000 (22:43 +0000)]
Amir Ayupov [Tue, 14 Mar 2023 22:36:40 +0000 (15:36 -0700)]
[BOLT][NFC] Use llvm::is_contained
Apply the replacement throughout BOLT.
Reviewed By: #bolt, rafauler
Differential Revision: https://reviews.llvm.org/D145464
Amir Ayupov [Tue, 14 Mar 2023 22:34:08 +0000 (15:34 -0700)]
[BOLT][NFC] Remove BB::getBranchInfo accepting MCSymbol ptr
Reviewed By: #bolt, rafauler
Differential Revision: https://reviews.llvm.org/D144924
Fangrui Song [Tue, 14 Mar 2023 22:17:38 +0000 (15:17 -0700)]
[RISCV][MC] Adjust conditions to emit R_RISCV_ADD*/R_RISCV_SUB* pairs
D132262 tried to simplify `IsMetadataOrEHFrameSection` originally introduced in
D127549 but caused a regression as `.quad` directives in
```
.section .note,"a",@note; note:
.quad extern-note # extern is undefined
.section .rodata,"a",@progbits; rodata:
.quad extern-rodata # extern is undefined
.section .nonalloc,"",@progbits; nw:
.quad extern-nw
```
are incorrectly rejected: these differences may be link-time constants and
are allowed in GNU assembler and LLVM MC's non-RISC-V ports.
Relax the conditions to allow these cases. For A-B, A may be defined later, but
this requiresFixups call has to eagerly make a decision. For now, emit ADD/SUB
unless A is `.L*`. This euristic handles many temporary label differences for
.debug_* and .apple_types sections. Ideally we should delay the decision of
PC-relative vs ADD/SUB until A is defined.
Reviewed By: compnerd
Differential Revision: https://reviews.llvm.org/D145474
Fangrui Song [Tue, 14 Mar 2023 22:16:58 +0000 (15:16 -0700)]
[RISCV] A@plt-B+C: emit R_RISCV_PLT32 even if A is defined
Follow-up to D143226
Currently we incorrectly emit R_RISCV_ADD32/R_RISCV_SUB32.
Emit R_RISCV_PLT32 instead. The new behavior matches x86-64 and AArch64.
Arthur Eubanks [Tue, 14 Mar 2023 16:40:48 +0000 (09:40 -0700)]
[SimplifyLibCalls] Return Value from optimizeSinCosPi when making change
Or else InstCombine can incorrectly report that no change has been made.
This optimization doesn't really fit into InstCombine since it optimizes multiple instructions at once; there's likely a more comprehensive fix.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D146064
bixia1 [Thu, 9 Mar 2023 17:38:09 +0000 (09:38 -0800)]
[mlir][sparse] Improve sort operation by generating inlined code to compare values.
Previously, we generate function calls to compare values for sorting. It turns
out that the compiler doesn't inline those function calls. We now directly
generate inlined code. Also, modify the code for comparing values to use less
number of branches.
This improves all sort implementation in general. For arabic-2005.mtx CSR, the
improvement is around 25%.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D145442
Kiran Chandramohan [Tue, 14 Mar 2023 21:51:02 +0000 (21:51 +0000)]
[MLIR] : Add integer mul in scf to openmp conversion
Add conversion for integer multiplication in scf reductions in the
SCF to OpenMP dialect conversion.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D145948
Kiran Chandramohan [Tue, 14 Mar 2023 19:08:34 +0000 (19:08 +0000)]
[Flang][OpenMP] Add support for OpenMP max reduction
This patch adds support for reduction of max-intrinsic for scalar
types. Max is lowered as a compare-select in the default lowering
flow for Flang. This pattern is matched and replaced with the
OpenMP dialect reduction operation.
Note: This is a temporary flow. The plan is to move to a flow where
the OpenMP reduction operation is inserted during lowering.
Reviewed By: do
Differential Revision: https://reviews.llvm.org/D145083
David Green [Tue, 14 Mar 2023 21:25:18 +0000 (21:25 +0000)]
[AArch64] Add FP16 broadcast and transpose costs
The FP16 broadcast and transpose can always use the same instructions as are
used for i16 vectors, with or without +fullfp16. This fills in some extra costs
to make sure we get them right.
Differential Revision: https://reviews.llvm.org/D146035
Julian Lettner [Thu, 9 Mar 2023 19:32:17 +0000 (11:32 -0800)]
Remove -lower-global-dtors-via-cxa-atexit flag
Remove the `-lower-global-dtors-via-cxa-atexit` escape hatch introduced
in D121736 [1], which switched the default lowering of global
destructors on MachO to use `__cxa_atexit()` to avoid emitting
deprecated `__mod_term_func` sections.
I added this flag as an escape hatch in case the switch causes any
problems. We didn't discover any problems so now we can remove it.
[1] https://reviews.llvm.org/D121736
rdar://
90277838
Differential Revision: https://reviews.llvm.org/D145715
Jacob Lambert [Fri, 10 Mar 2023 08:47:50 +0000 (00:47 -0800)]
[clang-offload-bundler] Standardize TargetID field for bundler
The bundler accepts both of the following for the --target option:
hip-amdgcn-amd-amdhsa-gfx900 (no env field)
hip-amdgcn-amd-amdhsa--gfx900 (blank env field)
The environment field is defined as optional for Triples
in Triple.h. However, in this patch we update the bundler to
internally standardize to include the env field. While users
aren't required to specify an env field when listing targets on
the commandline, bundles generated by the offload-bundler will
include the ABI field.
This standardization simplifies things for APIs that deal with
bundles generated by the clang-offload-bundler tool.
Differential Revision: https://reviews.llvm.org/D145770
Philip Reames [Tue, 14 Mar 2023 21:05:00 +0000 (14:05 -0700)]
[BasicBlockUtils] Expose an internal utility in API [nfc]
Shrinking a patch about to be posted for review.
Valery N Dmitriev [Thu, 23 Feb 2023 00:35:38 +0000 (16:35 -0800)]
[SLP] Outline GEP chain cost modeling into new TTI interface - NFCI.
Cost modeling for GEPs should actually be target dependent but is currently
done inside SLP target-independent way.
Sinking it into TTI enables target dependent implementation.
This patch adds new TTI interface and implementation of the basic functionality
trying to retain existing cost modeling.
Differential Revision: https://reviews.llvm.org/D144770
Slava Zakharin [Tue, 14 Mar 2023 20:58:58 +0000 (13:58 -0700)]
[flang] Fixed linaro-flang-aarch64-sharedlibs after D145992.
Daniel Thornburgh [Tue, 14 Mar 2023 20:44:07 +0000 (13:44 -0700)]
Revert "[LLVM][OHOS] Clang toolchain and targets"
This change had tests that break whenever LLVM_ENABLE_LINKER_BUILD_ID is
set, as is the case in the Fuchsia target.
This reverts commits:
f81317a54586dbcef0c14cf512a0770e8ecaab3d
72474afa27570a0a1307f3260f0187b703aa6d84
Valentin Clement [Tue, 14 Mar 2023 20:44:41 +0000 (21:44 +0100)]
[flang] Load fir.ref<fir.class<T>> instead of creating a wrong box
When a subroutine has an entry statement, the non-used argument
will be a fir.alloca and result in a fir.ref<fir.class<T>> for
polymorphic entities. In createBox, just load the box instead of
creating a wrong box.
Reviewed By: PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D146079
Arthur Eubanks [Mon, 13 Mar 2023 16:53:50 +0000 (09:53 -0700)]
[Passes] Remove some legacy passes
NewGVN
GVNHoist
GVNSink
MemCpyOpt
Float2Int
These were only used for the optimization pipeline, of which the legacy version was removed.
Philip Reames [Tue, 14 Mar 2023 20:18:05 +0000 (13:18 -0700)]
[MSAN] Minor refactor to reduce future diff [nfc]
Joseph Huber [Tue, 14 Mar 2023 20:11:30 +0000 (15:11 -0500)]
[libc] Remove leftover debug prints
Kazu Hirata [Tue, 14 Mar 2023 20:13:56 +0000 (13:13 -0700)]
[InlineOrder] Plugin Inline Order
This allows developing and distributing inlining heuristics
outside of tree. And together with the inline advisor plugins
allows for fine grained control of the inliner.
The PluginInlineOrderAnalysis class serves as the entry point
for dynamic advisors. Plugins must register instances of this
class to provide their own InlineOrder.
I'm checking in this patch on behalf of ibricchi
<ibricchi@student.ethz.ch>.
Differential Revision: https://reviews.llvm.org/D140637