review.tizen.org Git - platform/kernel/linux-starfive.git/log

Merge tag 'qcom-drivers-for-6.2-2' of https://git./linux/kernel/git/qcom/linux into soc/drivers

More Qualcomm driver updates for 6.2

Socinfo is extended with knowledge about MSM8956, MSM8976, SM6115,
SM4250, SM8150, SA8155 and SM8550.

Support for RSC v3, as found in SM8550 is added to the RPMH RSC driver.

Support for SM8550 and SM4250 ARC regulators are added to the RPM(h)
power-domain drivers. SM8550 support is added to the LLCC driver.
The AOSS QMP binding is declared compatible for SM8550.

BWMON and LLCC now selects REGMAP_MMIO to ensure dependencies are built
properly.

* tag 'qcom-drivers-for-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table
  dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants
  soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table
  dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155
  dt-bindings: soc: qcom: apr: document generic qcom,apr compatible
  soc: qcom: Select REMAP_MMIO for ICC_BWMON driver
  soc: qcom: Select REMAP_MMIO for LLCC driver
  soc: qcom: rpmpd: Add SM4250 support
  dt-bindings: power: rpmpd: Add SM4250 support
  dt-bindings: soc: qcom: aoss: Add compatible for SM8550
  soc: qcom: llcc: Add configuration data for SM8550
  dt-bindings: arm: msm: Add LLCC compatible for SM8550
  soc: qcom: llcc: Add v4.1 HW version support
  soc: qcom: socinfo: Add SM8550 ID
  soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response
  soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets
  soc: qcom: rpmhpd: Add SM8550 power domains
  dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding
  soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table
  dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976

Link: https://lore.kernel.org/r/20221207154134.3233779-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table

Add SoC ID table entries for the SM6115 / SM4250 and variants.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221201141619.2462705-5-bhupesh.sharma@linaro.org

dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants

Add SoC IDs for Qualcomm SM6115 / SM4250 and variants.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221201141619.2462705-4-bhupesh.sharma@linaro.org

soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table

Add SoC ID table entries for the SM8150 and SA8155 SoCs.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221201141619.2462705-3-bhupesh.sharma@linaro.org

dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155

Add SoC IDs for Qualcomm SM8150 and SA8155 SoCs.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221201141619.2462705-2-bhupesh.sharma@linaro.org

dt-bindings: soc: qcom: apr: document generic qcom,apr compatible

Document the qcom,apr compatible, used by Qualcomm Asynchronous Packet
Router driver.  There are no upstream DTSes using this compatible -
instead we have ones with APRv2 (qcom,apr-v2).  The driver does not make
distinction between both compatibles, which raises the question whether
the compatible is really needed.  Document it (as compatible with v2)
for completeness.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221201133637.46146-1-krzysztof.kozlowski@linaro.org

soc: qcom: Select REMAP_MMIO for ICC_BWMON driver

ICC_BWMON driver uses REGMAP_MMIO for accessing the hardware registers.
So select the dependency in Kconfig. Without this, there will be errors
while building the driver with COMPILE_TEST only:

ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/icc-bwmon.ko] undefined!
make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1
make: *** [Makefile:1944: modpost] Error 2

Cc: <stable@vger.kernel.org> # 6.0
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Fixes: b9c2ae6cac40 ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221129072022.41962-1-manivannan.sadhasivam@linaro.org

soc: qcom: Select REMAP_MMIO for LLCC driver

LLCC driver uses REGMAP_MMIO for accessing the hardware registers. So
select the dependency in Kconfig. Without this, there will be errors
while building the driver with COMPILE_TEST only:

ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/llcc-qcom.ko] undefined!
make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1
make: *** [Makefile:1944: modpost] Error 2

Cc: <stable@vger.kernel.org> # 4.19
Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver")
Reported-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221129071201.30024-2-manivannan.sadhasivam@linaro.org

soc: qcom: rpmpd: Add SM4250 support

SM4250 has the same RPM power domains as SM6115. Add SM4250
support by reusing SM6115 power domains.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221127112204.1486337-3-bhupesh.sharma@linaro.org

dt-bindings: power: rpmpd: Add SM4250 support

Add compatible and constants for the power domains exposed by the
SM4250 RPM.

Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221127112204.1486337-2-bhupesh.sharma@linaro.org

dt-bindings: soc: qcom: aoss: Add compatible for SM8550

Document the compatible for SM8550.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116113128.2655441-1-abel.vesa@linaro.org

soc: qcom: llcc: Add configuration data for SM8550

Add LLCC configuration data for SM8550 SoC.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116113005.2653284-4-abel.vesa@linaro.org

dt-bindings: arm: msm: Add LLCC compatible for SM8550

Add LLCC compatible for SM8550 SoC.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116113005.2653284-3-abel.vesa@linaro.org

soc: qcom: llcc: Add v4.1 HW version support

The LLCC found in SM8550 supports more slice configuration knobs and HW
block version has been bumped up to 4.1. Add support for the new version
and make sure the new config values are programed on probe.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116113005.2653284-2-abel.vesa@linaro.org

soc: qcom: socinfo: Add SM8550 ID

Add the ID for the Qualcomm SM8550 SoC.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116112438.2643607-1-abel.vesa@linaro.org

soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response

The RSC interrupt is issued only after the request is complete. For
fire-n-forget requests, the irq-done interrupt is sent after issuing the
RPMH request and for response-required request, the interrupt is
triggered only after all the requests are complete.

These unnecessary checks in the interrupt handler issues AHB reads from
a critical path. Lets remove them and clean up error handling in
rpmh_request data structures.

Co-developed-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116112246.2640648-2-abel.vesa@linaro.org

soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets

The SM8550 RSC has a new set of register offsets due to its version bump.
So read the version from HW and use the proper register offsets based on
that.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116112246.2640648-1-abel.vesa@linaro.org

soc: qcom: rpmhpd: Add SM8550 power domains

Add the power domains exposed by RPMH in the Qualcomm SM8550 platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116111745.2633074-3-abel.vesa@linaro.org

dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding

Add compatible and constants for the power domains exposed by the RPMH
in the Qualcomm SM8550 platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221116111745.2633074-2-abel.vesa@linaro.org

soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table

Add SoC ID table entries for MSM8956 and MSM8976 chips.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-8-angelogioacchino.delregno@collabora.com

dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976

Document the identifier of MSM8956/76.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111120156.48040-7-angelogioacchino.delregno@collabora.com

soc: fsl: qe: request pins non-exclusively

Commit 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") changed
qe_pin_request() to request and hold GPIO corresponding to a given pin.
Unfortunately this does not work, as fhci-hcd requests these GPIOs
first, befor calling qe_pin_request() (see
drivers/usb/host/fhci-hcd.c::of_fhci_probe()).
To fix it change qe_pin_request() to request GPIOs non-exclusively, and
free them once the code determines GPIO controller and offset for each
GPIO/pin.

Also reaching deep into gpiolib implementation is not the best idea. We
should either export gpio_chip_hwgpio() or keep converting to the global
gpio numbers space until we fix the driver to implement proper pin
control.

Fixes: 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/Y400YXnWBdz1e/L5@google.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

ARM: mmp: fix timer_read delay

timer_read() was using an empty 100-iteration loop to wait for the
TMR_CVWR register to capture the latest timer counter value. The delay
wasn't long enough. This resulted in CPU idle time being extremely
underreported on PXA168 with CONFIG_NO_HZ_IDLE=y.

Switch to the approach used in the vendor kernel, which implements the
capture delay by reading TMR_CVWR a few times instead.

Fixes: 49cbe78637eb ("[ARM] pxa: add base support for Marvell's PXA168 processor line")
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20221204005117.53452-3-doug@schmorgal.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

pxa: Remove dev_err() after platform_get_irq()

There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.

Signed-off-by: zhang songyi <zhang.songyi@zte.com.cn>
Reviewed-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lore.kernel.org/r/202212021042043546303@zte.com.cn
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'arm-soc/for-6.2/drivers' of https://github.com/Broadcom/stblinux into soc/drivers

This pull request contains Broadcom SoCs driver changes for 6.2, please
pull the following:

- Yuan uses dev_err_probe() in the Raspberry Pi firmware provider to
  simplify the error handling code

- Rafal adds support for initialiazing the BCM47xx NVMEM/NVRAM firmware
  provider out of memory-mapped flash devices.

* tag 'arm-soc/for-6.2/drivers' of https://github.com/Broadcom/stblinux:
  firmware/nvram: bcm47xx: support init from IO memory
  firmware: raspberrypi: Use dev_err_probe() to simplify code

Link: https://lore.kernel.org/r/20221129191755.542584-3-f.fainelli@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux into soc/drivers

Apple SoC RTKit/SART updates for 6.2.

Just two minor correctness nits reported by the kernel test robot.

* tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux:
soc: apple: rtkit: Stop casting function pointer signatures
soc: apple: sart: Stop casting function pointer signatures

Link: https://lore.kernel.org/r/57f84134-8645-35f6-2427-ee683800c413@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

soc: apple: rtkit: Stop casting function pointer signatures

Fixes: 9bd1d9a0d8bb ("soc: apple: Add RTKit IPC library")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>

soc: apple: sart: Stop casting function pointer signatures

Fixes: b170143ae111 ("soc: apple: Add SART driver")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Hector Martin <marcan@marcan.st>

tegra: mark BPMP driver as little-endian only

The BPMP firmware driver never worked on big-endian kernels, and
cannot easily be made portable. Add a dependency to make this clear
in case anyone ever wants to try a big-endian kernel on this hardware.

Link: https://lore.kernel.org/linux-arm-kernel/Y34FCQ3xTmcjqKRT@orome/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'ti-driver-soc-for-v6.2-v2' of git://git./linux/kernel/git/ti/linux into soc/drivers

TI SoC driver updates for v6.2 v2

* Minor bugfixes for knav_qmss_queue, smartreflex drivers
* API optimizations including using devm, bitmap apis to
  ti-sci, soc-info drivers
* k3-ringacc can now be built as modules for certain
  distros that mandate such usage.
* k3-socinfo can now detect AM62A SoCs.

* tag 'ti-driver-soc-for-v6.2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  soc: ti: k3-socinfo: Add AM62Ax JTAG ID
  soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe
  soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe
  firmware: ti_sci: Use devm_bitmap_zalloc when applicable
  soc: ti: k3-ringacc: Allow the driver to be built as module
  firmware: ti_sci: Fix polled mode during system suspend
  firmware: ti_sci: Use the non-atomic bitmap API when applicable
  firmware: ti_sci: Use the bitmap API to allocate bitmaps
  drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as static

Link: https://lore.kernel.org/r/20221122223856.fwackjg7fbd5jcz7@wannabe
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'qcom-drivers-for-6.2' of https://git./linux/kernel/git/qcom/linux into soc/drivers

Qualcomm driver updates for 6.2

The qcom,msm-id and qcom,board-id DeviceTree properties are documented,
to allow them to be used in configurations or devices requiring these
and the socinfo driver is updated to reuse the introduced identifiers.

The rpmh-rsc driver is extended to register for PM runtime notifications
from the CPU clusters, in order to submit sleep and wake votes the last
core in a cluster is being powered down.

A mechanism for keeping rpmhpd resources voted until sync_state is
introduced, this ensures that power-domains required during boot are
kept enabled. The rpmhpd power-domains for SDM670 are also added.

Support for the new QDU1000/QRU1000 platform is introduced in the rpmhpd
and socinfo drivers.

The APR driver gains missing error handling. QMI message descriptors in
the PDR driver are made const.

Support for the RPM found in SM6375 is added. The SPM driver gains
support for MSM8939 and MSM8976 platforms.

The stats and command-db drvers are marked as not having PM support.

* tag 'qcom-drivers-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits)
  dt-bindings: firmware: scm: add sdm670 compatible
  soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
  soc: qcom: rpmh-rsc: Save base address of drv
  PM: domains: Store the next hrtimer wakeup in genpd
  soc: qcom: rpmh-rsc: Attach RSC to cluster PM domain
  dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rsc
  dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976
  soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index
  soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id table
  dt-bindings: arm: qcom,ids: Add SoC IDs for QDU1000/QRU1000
  soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domains
  dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd binding
  dt-bindings: qcom: smp2p: Add WPSS node names to pattern property
  soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM
  dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2
  soc: qcom: llcc: make irq truly optional
  soc: qcom: spm: Add MSM8939 SPM register data
  dt-bindings: soc: qcom: spm: Add MSM8939 CPU compatible
  dt-bindings: soc: qcom: aoss: Add sc8280xp compatible
  dt-bindings: firmware: document Qualcomm SM6375 SCM
  ...

Link: https://lore.kernel.org/r/20221122202748.1854487-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

soc: ti: k3-socinfo: Add AM62Ax JTAG ID

Add JTAG ID entry to help identify AM62Ax SoC in kernel.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221119152447.241166-1-vigneshr@ti.com

Merge tag 'v6.1-next-soc' of https://git./linux/kernel/git/matthias.bgg/linux into soc/drivers

mmsys:
- add support for MT8186
- add correct compatible solution for vdosys[0,1] on MT8195

pmic wrapper:
- add support for MT8365

* tag 'v6.1-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  soc: mediatek: Add deprecated compatible to mmsys
  soc: mediatek: pwrap: add mt8365 SoC support
  soc: mediatek: pwrap: add support for sys & tmr clocks
  dt-bindings: soc: mediatek: pwrap: add MT8365 SoC bindings
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0"
  dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
  soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func

Link: https://lore.kernel.org/r/cc756001-a942-90b0-b79d-62c1fc189828@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.2-memory-v2' of git://git./linux/kernel/git/tegra/linux into soc/drivers

memory: tegra: Changes for v6.2-rc1

Some cleanups replace open-coded debugfs attributes and memory client
IDs are added for the DLA IP found on Tegra234 SoCs.

* tag 'tegra-for-6.2-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  memory: tegra: Add DLA clients for Tegra234
  memory: tegra186-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
  memory: tegra210-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
  memory: tegra30-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
  memory: tegra20-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code
  dt-bindings: tegra: Update headers for Tegra234
  dt-bindings: Add headers for NVDEC on Tegra234

Link: https://lore.kernel.org/r/20221121171239.2041835-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.2-clk-v2' of git://git./linux/kernel/git/tegra/linux into soc/drivers

clk: tegra: Changes for v6.2-rc1

Implements new ABI flags for certain clocks for which the parent rate
or clock state cannot be changed.

* tag 'tegra-for-6.2-clk-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Support BPMP-FW ABI deny flags

Link: https://lore.kernel.org/r/20221121171239.2041835-3-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.2-firmware-v2' of git://git./linux/kernel/git/tegra/linux into soc/drivers

firmware: tegra: Changes for v6.2-rc1

This adds new BPMP ABI so that newer features can be enabled.
Furthermore, the BPMP driver is updated to use iosys-map helpers to
allow working with shared memory regions that are located in system
memory.

Apart from that, several minor cleanups are included.

* tag 'tegra-for-6.2-firmware-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  firmware: tegra: Remove surplus dev_err() when using platform_get_irq_byname()
  firmware: tegra: Update BPMP ABI
  firmware: tegra: bpmp: Do not support big-endian
  firmware: tegra: bpmp: Use iosys-map helpers
  firmware: tegra: bpmp: Prefer u32 over uint32_t

Link: https://lore.kernel.org/r/20221121171239.2041835-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.2-soc-v2' of git://git./linux/kernel/git/tegra/linux into soc/drivers

soc/tegra: Changes for v6.2-rc1

In addition to a number of improvements and cleanups this contains a
fix for the FUSE access on newer chips, adds Tegra234 I/O pad support
and fixes various issues with wake events.

The SoC sysfs revision attribute is updated to include the platform
information so drivers can check for silicon vs. pre-silicon, among
other things.

* tag 'tegra-for-6.2-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: cbb: Remove redundant dev_err call
  soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_err
  firmware: tegra: include IVC header file only once
  soc/tegra: cbb: Check firewall before enabling error reporting
  soc/tegra: cbb: Add checks for potential out of bound errors
  soc/tegra: cbb: Update slave maps for Tegra234
  soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194
  soc/tegra: fuse: Use platform info with SoC revision
  soc/tegra: pmc: Process wake events during resume
  soc/tegra: pmc: Fix dual edge triggered wakes
  soc/tegra: pmc: Add I/O pad table for Tegra234
  soc/tegra: fuse: Add nvmem keepout list
  soc/tegra: fuse: Use SoC specific nvmem cells
  soc/tegra: pmc: Select IRQ_DOMAIN_HIERARCHY

Link: https://lore.kernel.org/r/20221121171239.2041835-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'riscv-soc-for-v6.2-mw0' of https://git./linux/kernel/git/conor/linux into soc/drivers

RISC-V SoC drivers for v6.2

SiFive:
- add probe error handling to the ccache driver

* tag 'riscv-soc-for-v6.2-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()
  soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
  soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()

Link: https://lore.kernel.org/r/Y3u0Oydiv2Wauda2@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

soc: mediatek: Add deprecated compatible to mmsys

For backward compatibility we add the deprecated compatible.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221111082912.14557-1-matthias.bgg@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

soc: mediatek: pwrap: add mt8365 SoC support

Add PMIC Wrap support for MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221031093401.22916-4-fchiby@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

soc: mediatek: pwrap: add support for sys & tmr clocks

MT8365 requires an extra 2 clocks to be enabled to behave correctly.
Add support these 2 clocks, they are made optional since they seem to
be present only on MT8365.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221031093401.22916-3-fchiby@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

dt-bindings: soc: mediatek: pwrap: add MT8365 SoC bindings

Add pwrap binding documentation for

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fadwa CHIBY <fchiby@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221031093401.22916-2-fchiby@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

1. Add mt8195 driver data with compatible "mediatek-mt8195-vdosys0".
2. Add mt8195 routing table settings of vdosys0.

Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220927152704.12018-4-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Revert "soc: mediatek: add mtk-mmsys support for mt8195 vdosys0"

This reverts commit b804923b7ccb9c9629703364e927b48cd02a9254.

Due to the compatible changing of mt8195 from "mediatek,mt8195-mmsys"
to "mediatek,mt8195-vdosys0", we have to revert this patch and send a
new patch with the new compatible.

Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Link: https://lore.kernel.org/r/20220927152704.12018-3-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

dt-bindings: arm: mediatek: mmsys: change compatible for MT8195

For previous MediaTek SoCs, such as MT8173, there are 2 display HW
pipelines binding to 1 mmsys with the same power domain, the same
clock driver and the same mediatek-drm driver.

For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to
2 different power domains, different clock drivers and different
mediatek-drm drivers.

Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR,
CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality)
and they makes VDOSYS0 supports PQ function while they are not
including in VDOSYS1.

Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related
component). It makes VDOSYS1 supports the HDR function while it's not
including in VDOSYS0.

To summarize0:
Only VDOSYS0 can support PQ adjustment.
Only VDOSYS1 can support HDR adjustment.

Therefore, we need to separate these two different mmsys hardwares to
2 different compatibles for MT8195.

Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220927152704.12018-2-jason-jh.lin@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Merge tag 'memory-controller-drv-6.2-2' of https://git./linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.2, part two

1. ARM PL353: document PL354 in bindings.
2. TI/OMAP GPMC: allow setting wait-pin polarity.

* tag 'memory-controller-drv-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: omap-gpmc: fix coverity issue "Control flow issues"
  dt-bindings: memory-controllers: ti,gpmc: add wait-pin polarity
  memory: omap-gpmc: wait pin additions
  MAINTAINERS: arm,pl353-smc: correct dt-binding path
  dt-bindings: memory-controllers: arm,pl353-smc: Extend to support 'arm,pl354' SMC

Link: https://lore.kernel.org/r/20221116093509.19657-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'imx-drivers-6.2' of git://git./linux/kernel/git/shawnguo/linux into soc/drivers

i.MX drivers change for 6.2:

- Improve imx8m-blk-ctrl driver to allow deferred probe in case that
  'bus' genpd is not yet ready.
- Add missing USB_1_PHY PD for i.MX scu-pd firmware driver.
- Add GENPD_FLAG_ACTIVE_WAKEUP flag for i.MX8MM/N in GPCv2 driver, so
  that the power domain remains on if USB remote wakeup is enabled.

* tag 'imx-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: gpcv2: add GENPD_FLAG_ACTIVE_WAKEUP flag for usb of imx8mm/n
  firmware: imx: scu-pd: add missed USB_1_PHY pd
  soc: imx: imx8m-blk-ctrl: Defer probe if 'bus' genpd is not yet ready

Link: https://lore.kernel.org/r/20221119125733.32719-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'renesas-drivers-for-v6.2-tag2' of git://git./linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.2 (take two)

- Add support for identifying the SoC revision on RZ/V2M.

* tag 'renesas-drivers-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Identify RZ/V2M SoC

Link: https://lore.kernel.org/r/cover.1668788925.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'optee-for-6.2' of https://git.linaro.org/people/jens.wiklander/linux-tee into soc/drivers

Add missing __init/__exit annotations to OP-TEE driver

* tag 'optee-for-6.2' of https://git.linaro.org/people/jens.wiklander/linux-tee:
optee: Add __init/__exit annotations to module init/exit funcs

Link: https://lore.kernel.org/r/Y3d4CHWl3Ofx5OrX@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

memory: tegra: Add DLA clients for Tegra234

Add the memory clients on Tegra234 which are needed for initialising the
SMMU for the Deep Learning Accelerator (DLA).

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

memory: tegra186-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No
functional change.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

memory: tegra210-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No
functional change.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

memory: tegra30-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No
functional change.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

memory: tegra20-emc: Use DEFINE_SHOW_ATTRIBUTE to simplify code

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No
functional change.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Merge branch for-6.2/dt-bindings into for-6.2/memory

dt-bindings: tegra: Update headers for Tegra234

Update the device-tree clock, memory, power and reset headers for
Tegra234 by adding the definitions for all the various devices.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

clk: tegra: Support BPMP-FW ABI deny flags

Support BPMP_CLK_STATE_CHANGE_DENIED by not populating state changing
operations when the flag is set.

Support BPMP_CLK_RATE_PARENT_CHANGE_DENIED by not populating rate or
parent changing operations when the flag is set.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

firmware: tegra: Remove surplus dev_err() when using platform_get_irq_byname()

There is no need to call the dev_err() function directly to print a
custom message when handling an error from either the platform_get_irq()
or platform_get_irq_byname() functions as both are going to display an
appropriate error message in case of a failure.

./drivers/firmware/tegra/bpmp-tegra210.c:204:2-9: line 204 is redundant
because platform_get_irq() already prints an error
./drivers/firmware/tegra/bpmp-tegra210.c:216:2-9: line 216 is redundant
because platform_get_irq() already prints an error

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2579
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Merge branch 'for-6.2/firmware' into for-6.2/clk

firmware: tegra: Update BPMP ABI

Update the BPMP ABI to align with the the latest version.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: cbb: Remove redundant dev_err call

devm_ioremap_resource() prints error message in itself. Remove the
dev_err call to avoid redundant error message.

Signed-off-by: Shang XiaoJing <shangxiaojing@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: cbb: Use DEFINE_SHOW_ATTRIBUTE to simplify tegra_cbb_err

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the code. No
functional change.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

firmware: tegra: include IVC header file only once

Add the necessary definition to prevent compilation
errors from the ivc.h file being included multiple times.
This does not currently cause any compilation issues,
but fix this anyway.

Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc: renesas: Identify RZ/V2M SoC

Add support for identifying the RZ/V2M (R9A09G011) SoC.
Note that the SoC does not have a identification register.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[biju: removed config changes ]
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20221116102140.852889-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe

The pm_runtime_enable will increase power disable depth. Thus
a pairing decrement is needed on the error handling path to
keep it balanced according to context.

Fixes: 984aa6dbf4ca ("OMAP3: PM: Adding smartreflex driver support.")
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221108080322.52268-3-zhangqilong3@huawei.com

soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe

The pm_runtime_enable will increase power disable depth. Thus
a pairing decrement is needed on the error handling path to
keep it balanced according to context.

Fixes: 41f93af900a2 ("soc: ti: add Keystone Navigator QMSS driver")
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20221108080322.52268-2-zhangqilong3@huawei.com

dt-bindings: soc: add loongson-2 chipid

Add the Loongson-2 SoC chipid binding with DT schema format using
json-schema.

Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221111054201.18528-2-zhuyinbo@loongson.cn'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

soc: loongson: add GUTS driver for loongson-2 platforms

The global utilities block controls PCIE device enabling, alternate
function selection for multiplexed signals, consistency of HDA, USB
and PCIE, configuration of memory controller, rtc controller, lio
controller, and clock control.

This patch adds a driver to manage and access global utilities block
for LoongArch architecture Loongson-2 SoCs. Initially only reading SVR
and registering soc device are supported. Other guts accesses, such
as reading firmware configuration by default, should eventually be
added into this driver as well.

Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'renesas-drivers-for-v6.2-tag1' of git://git./linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v6.2

  - Let SOC_RENESAS select GPIOLIB and PINCTRL, so this does not have to
    be handled in two (soon three: arm/arm64/riscv), places.

* tag 'renesas-drivers-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: Kconfig: Explicitly select GPIOLIB and PINCTRL config under SOC_RENESAS

Link: https://lore.kernel.org/r/cover.1667558747.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

dt-bindings: firmware: scm: add sdm670 compatible

The Snapdragon 670 uses SCM as for PSCI power management. Document the
appropriate compatible string for it.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221111001818.124901-4-mailingradian@gmail.com

soc/tegra: cbb: Check firewall before enabling error reporting

To enable error reporting for a fabric to CCPLEX, we need to write its
register for enabling error interrupt to CCPLEX during boot and later
clear the error status register after error occurs. If a fabric's
registers are protected and not accessible from CCPLEX, then accessing
the registers will cause CBB firewall error.

Add support to check whether write access from CCPLEX to the registers
of a fabric is not blocked by it's firewall before enabling error
reporting to CCPLEX for that fabric.

Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0")
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: cbb: Add checks for potential out of bound errors

Added checks to avoid potential out of bounds errors which can happen if
the 'slave map' and 'CBB errors' arrays are not correct or latest where
some entries are missing.

Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0")
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: cbb: Update slave maps for Tegra234

Updating the slave map for fabrics and using the same maps for DCE, RCE
and SCE as they all are a replica in Tegra234.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: cbb: Use correct master_id mask for CBB NOC in Tegra194

In Tegra194 SoC, master_id bit range is different between cluster NOC
and CBB NOC. Currently same bit range is used which results in wrong
master_id value. Due to this, illegal accesses from the CCPLEX master
do not result in a crash as expected. Fix this by using the correct
range for the CBB NOC.

Finally, it is only necessary to extract the master_id when the
erd_mask_inband_err flag is set because when this is not set, a crash
is always triggered.

Fixes: b71344221466 ("soc/tegra: cbb: Add CBB 1.0 driver for Tegra194")
Fixes: fc2f151d2314 ("soc/tegra: cbb: Add driver for Tegra234 CBB 2.0")
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: fuse: Use platform info with SoC revision

Tegra pre-silicon platforms do not have chip revisions. This makes the
revision SoC attribute meaningless on these platforms.

Instead, populate the revision SoC attribute with a combination of the
platform name and the chip revision for silicon platforms, and simply
with the platform name on pre-silicon platforms.

Signed-off-by: Kartik <kkartik@nvidia.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

memory: omap-gpmc: fix coverity issue "Control flow issues"

Assign a big positive integer instead of an negative integer to an
u32 variable. Also remove the check for ">= 0" which doesn't make sense
for unsigned integers.

Reported-by: coverity-bot <keescook+coverity-bot@chromium.org>
Addresses-Coverity-ID: 1527139 ("Control flow issues")
Fixes: 89aed3cd5cb9 ("memory: omap-gpmc: wait pin additions")
Signed-off-by: Benedikt Niedermayr <benedikt.niedermayr@siemens.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20221109102454.174320-1-benedikt.niedermayr@siemens.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup

The next wakeup timer value needs to be set in always on domain timer
as the arch timer interrupt can not wakeup the SoC if after the deepest
CPUidle states the SoC also enters deepest low power state.

To wakeup the SoC in such scenarios the earliest wakeup time is set in
CONTROL_TCS and the firmware takes care of setting up its own timer in
always on domain with next wakeup time. The timer wakes up the RSC and
sets resources back to wake state.

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org

soc: qcom: rpmh-rsc: Save base address of drv

Add changes to save drv's base address for rsc. This is
used to read drv's configuration such as solver mode is
supported or to write into CONTROL_TCS registers.

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-6-ulf.hansson@linaro.org

PM: domains: Store the next hrtimer wakeup in genpd

The arch timer cannot wake up the Qualcomm Technologies, Inc. (QTI) SoCs
from the deeper CPUidle states. To be able to wakeup from these deeper
states, another always-on timer needs to be programmed through the so
called CONTROL_TCS.

As the RSC is part of CPU subsystem and the corresponding APSS RSC device
is attached to the cluster PM domain (through genpd), it holds the
responsibility to program the always-on timer, before entering any of these
deeper CPUidle states.

However, programming the timer requires information about the next hrtimer
wakeup for the cluster PM domain, which is currently only known by genpd.
Therefore, let's share this data through a new genpd helper function,
dev_pm_genpd_get_next_hrtimer().

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>
[Ulf: Reworked the code and updated the commit message]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-5-ulf.hansson@linaro.org

soc: qcom: rpmh-rsc: Attach RSC to cluster PM domain

RSC is part the CPU subsystem and powers off the CPU domains when all
the CPUs and no RPMH transactions are pending from any of the drivers.
The RSC needs to flush the 'sleep' and 'wake' votes that are critical
for saving power when all the CPUs are in idle.

Let's make RSC part of the CPU PM domains, by attaching it to the
cluster power domain. Registering for PM domain notifications, RSC
driver can be notified that the last CPU is powering down. When the last
CPU is powering down the domain, let's flush the 'sleep' and 'wake'
votes that are stored in the data buffers into the hardware and also
write next wakeup in CONTROL_TCS.

Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-3-ulf.hansson@linaro.org

dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rsc

The change documents power-domains property for RSC device.
This optional property points to corresponding PM domain node.

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221018152837.619426-2-ulf.hansson@linaro.org

soc/tegra: pmc: Process wake events during resume

During system resume, translate tier2 SC7 wake sources back into IRQs
and do generic_handle_irq() to invoke the interrupt handlers for edge
triggered wake events such as SW-wake.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: pmc: Fix dual edge triggered wakes

When a wake event is defined to be triggered on both positive and
negative edge of the input wake signal, it is crucial to know the
current state of the signal when going into suspend. The intended way to
obtain the current state of the wake signals is to read the
WAKE_AOWAKE_SW_STATUS register, which should contains the raw state of
the wake signals.

However, this register is edge triggered, an edge will not be generated
for signals that are already asserted prior to the assertion of
WAKE_LATCH_SW.

To workaround this, change the polarity of the wake level from '0' to
'1' while latching the signals, as this will generate an edge for
signals that are set to '1'.

Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: pmc: Add I/O pad table for Tegra234

Add I/O pad table for Tegra234 to allow configuring DPD mode and
switching the pins to 1.8V or 3.3V as needed.

On Tegra234, DPD registers are reorganized such that there is a DPD_REQ
register and a DPD_STATUS register per pad group. Update the PMC driver
accordingly.

While at it, use the generated tables from tegra-pinmux-scripts to make
the formatting of these tables more consistent.

Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
[treding@nvidia.com: generate tables from tegra-pinmux-scripts]
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()

The device_node pointer returned by of_find_matching_node() with
refcount incremented, when finish using it, the refcount need be
decreased.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()

Add missing free_irq() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()

Add missing iounmap() before return error from sifive_ccache_init().

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

firmware/nvram: bcm47xx: support init from IO memory

Provide NVMEM content to the NVRAM driver from a simple
memory resource. This is necessary to use NVRAM in a memory-
mapped flash device. Patch taken from OpenWrts development
tree.

This patch makes it possible to use memory-mapped NVRAM
on the D-Link DWL-8610AP and the D-Link DIR-890L.

Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@vger.kernel.org
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
[Added an export for modules potentially using the init symbol]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20221103082529.359084-1-linus.walleij@linaro.org
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

soc: mediatek: Add all settings to mtk_mmsys_ddp_dpi_fmt_config func

The difference between MT8186 and other ICs is that when modifying the
output format, we need to modify the mmsys_base+0x400 register to take
effect. So when setting the dpi output format, we need to call
mtk_mmsys_ddp_dpi_fmt_config to set it to MT8186 synchronously.

Commit a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi
output for MT8186") lacked some of the possible output formats and also
had a wrong bitmask.

Add the missing output formats and fix the bitmask.

While at it, also update mtk_mmsys_ddp_dpi_fmt_config() to use generic
formats, so that it is slightly easier to extend for other platforms.

Fixes: a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for MT8186")
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976

Like MSM8916 and some others, MSM8976 uses qcom,smd-channels and not
qcom,glink-channels.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104172122.252761-5-angelogioacchino.delregno@collabora.com

soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index

As idr_alloc() and of_property_read_string_index() can return negative
numbers, it should be better to check the return value and deal with
the exception.
Therefore, it should be better to use goto statement to stop and return
error.

Fixes: 6adba21eb434 ("soc: qcom: Add APR bus driver")
Signed-off-by: Jiasheng Jiang <jiasheng@iscas.ac.cn>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107014403.3606-1-jiasheng@iscas.ac.cn

soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id table

Add SoC ID table entries for the QDU1000 and QRU1000 platforms and
their variants.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221026190549.4005703-6-quic_molvera@quicinc.com

dt-bindings: arm: qcom,ids: Add SoC IDs for QDU1000/QRU1000

Add SoC IDs for Qualcomm QDU1000 and QRU1000 platforms and their
variants.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221026190549.4005703-5-quic_molvera@quicinc.com

soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domains

Add the power domains exposed by RPMH in the Qualcomm QDU1000
and QRU1000 platforms.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221026190549.4005703-4-quic_molvera@quicinc.com

dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd binding

Add compatible and constants for the power domains exposed by the RPMH
in the Qualcomm QDU1000 and QRU1000 platforms.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221026190549.4005703-3-quic_molvera@quicinc.com

dt-bindings: qcom: smp2p: Add WPSS node names to pattern property

WLAN firmware uses SMP2P protocol in order to talk to the application
processor (AP) in certain cases like WoW (Wake on Wireless). WLAN
firmware runs on the WPSS Q6 processor (Wireless Processor SubSystem).
Therefore it is required to have sub nodes pertaining to the WPSS Q6
processor and the application processor in the SMP2P node.

Add WPSS Q6 (Wireless Processor SubSystem) node names to the pattern
property required for WPSS Q6 processor to communicate to the
application processor and vice versa over SMP2P protocol.

Signed-off-by: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221017125346.3691-2-quic_mpubbise@quicinc.com

soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
and APQ variants and while at it also add the configuration for the
MSM8976's little (a53) and big (a72) clusters cache power management.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Marijn: reorder struct definitions to follow high-to-low order]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104133452.131227-3-angelogioacchino.delregno@collabora.com

dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2

Add SPM AVS Wrapper 2 compatibles for MSM8976's L2 cache.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104133452.131227-2-angelogioacchino.delregno@collabora.com

soc: qcom: llcc: make irq truly optional

The function platform_get_irq prints an error message into the kernel
log when the irq isn't found.

Since the interrupt is actually optional and not provided by some SoCs,
use platform_get_irq_optional which does not print an error message.

Fixes: c081f3060fab ("soc: qcom: Add support to register LLCC EDAC driver")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221104153041.412020-1-luca.weiss@fairphone.com