Pierre-Eric Pelloux-Prayer [Mon, 12 Apr 2021 06:03:41 +0000 (08:03 +0200)]
radeonsi: re-create the aux context in si_create_context
If a GPU reset occurs, all contexts need to be recreated.
So instead of re-creating the aux context during the flush
of a normal context, we build a new one if we detect that
it needs to be updated.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
Pierre-Eric Pelloux-Prayer [Fri, 9 Apr 2021 16:15:23 +0000 (18:15 +0200)]
radeonsi: only recreate the aux_context when soft recovery failed
When a GPU hang is detected in the kernel, it can uses 2 different
mechanism to recovery: a soft recovery or a hard reset.
Soft recovery doesn't lose the vram content so contexts are still
valid. In this case we don't need to recreate the aux context.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
Pierre-Eric Pelloux-Prayer [Fri, 9 Apr 2021 16:13:56 +0000 (18:13 +0200)]
radeonsi: do not recreate the aux context from the aux context
This will cause a deadlock since si_get_reset_status is called
from flush, which is called with aux_context_lock taken.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
Pierre-Eric Pelloux-Prayer [Fri, 9 Apr 2021 16:12:21 +0000 (18:12 +0200)]
radeonsi: use SI_CONTEXT_FLAG_AUX when recreating the aux context
Fixes:
e6a0f243ea1 ("radeonsi: update pipe_screen::num_contexts")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
Pierre-Eric Pelloux-Prayer [Fri, 9 Apr 2021 16:08:44 +0000 (18:08 +0200)]
radeonsi: submit cs to failed context instead of skipping them
Skipping the submission would trigger asserts in debug builds
or cause memory corruption.
Instead the cs is submitted as ususual but the kernel won't submit
it to the hardware (and will return ECANCELED) if the context
is really lost (= not soft-recovered).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2491
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
Pierre-Eric Pelloux-Prayer [Fri, 9 Apr 2021 16:04:56 +0000 (18:04 +0200)]
amdgpu,radeon: add needs_reset param to ctx_query_reset_status
The kernel can do different types of recovery (soft recovery, GPU reset).
Since they both increase gpu_reset_counter, this will cause all contexts
to report AMDGPU_CTX_QUERY2_FLAGS_RESET, which is a bit misleading: if
a single context was soft-recovered, the others are fine and we don't need
special processing.
This commit uses the AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST to distinguish
between the 2 kind of reset and later commits will use this information.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10179>
Pierre-Eric Pelloux-Prayer [Mon, 12 Apr 2021 09:05:47 +0000 (11:05 +0200)]
driconf: add workarounds for Teardown
Based on the comments from https://gitlab.freedesktop.org/mesa/mesa/-/issues/3714.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10172>
Pierre-Eric Pelloux-Prayer [Mon, 12 Apr 2021 08:56:27 +0000 (10:56 +0200)]
gallium/u_threaded: skip refcounting only once
If info->take_index_buffer_ownership is true we can skip
refcounting but only for the first iteration of the loop.
The next iterations have to use tc_set_resource_reference.
Fixes:
363c1ef0c0e ("gallium/u_threaded: split draws that don't fit in a batch")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10171>
Marek Olšák [Thu, 11 Feb 2021 22:59:02 +0000 (17:59 -0500)]
nir: handle mediump varyings in varying compaction helpers
Group mediump varyings and don't put 16-bit and 32-bit components
in the same vec4.
... and reply to the comment there.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10224>
Marek Olšák [Fri, 4 Sep 2020 17:48:30 +0000 (13:48 -0400)]
radeonsi: enable FP16 for mediump on gfx9+ if radeonsi_fp16=true
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
Marek Olšák [Mon, 29 Mar 2021 11:54:11 +0000 (07:54 -0400)]
radeonsi: kill 16-bit VS outputs if PS doesn't use them or doing Z-only draw
The kill_outputs logic uses our internal IO indices. Just add indices for
16-bit varyings. We don't have enough free indices to use, but we can reuse
the indices that GLES doesn't have. Those are all the legacy desktop GL
varyings.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
Marek Olšák [Thu, 11 Feb 2021 08:24:57 +0000 (03:24 -0500)]
radeonsi: optimize and legalize 16-bit samplers
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
Marek Olšák [Sun, 14 Feb 2021 11:48:43 +0000 (06:48 -0500)]
radeonsi: implement 16-bit VS inputs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
Marek Olšák [Wed, 10 Feb 2021 16:08:25 +0000 (11:08 -0500)]
radeonsi: implement 16-bit VS->PS varyings
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
Marek Olšák [Wed, 10 Feb 2021 03:06:09 +0000 (22:06 -0500)]
ac/llvm: implement 16-bit packed VS outputs and FS inputs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
Adam Jackson [Tue, 14 Nov 2017 20:13:04 +0000 (15:13 -0500)]
glx: Lift sending the MakeCurrent request to top-level code
Somewhat terrifyingly, we never sent this for direct contexts, which
means the server never knew the context/drawable bindings. To handle
this sanely, pull the request code up out of the indirect backend, and
rewrite the context switch path to call it as appropriate. This
attempts to preserve the existing behavior of not calling unbind() on
the context if its refcount would not drop to zero.
Of course, you can't just do this indiscriminately, because this is GLX
and extant X servers have bugs and everything is terrible. To wit:
- For 1.20.x prior to 1.20.6, you can bind a direct context once, but
the second time you try to modify the context's binding you will get
GLXBadContextTag. This includes unbinding the context. And "deleting"
the context will leak memory, because it will still appear to be
current.
- For 1.19 and earlier, glXMakeCurrent(dpy, None, ctx) should be legal
for GL 3.0+ contexts, but the server will throw BadMatch.
To guard against this, we only send the request for indirect contexts
unless the server is known good, and only mention one context at a time
in such a request; if switching between contexts, we first unbind the
old, and then bind the new. Note that the second VendorRelease() version
is to catch XFree86 4.x and Xorg [67].x, which almost certainly have the
above bugs. Other servers might report different version numbers here,
but we can't do direct rendering against them, so this should be safe.
Fixes: mesa/mesa#4418
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Adam Jackson [Mon, 12 Apr 2021 15:33:17 +0000 (11:33 -0400)]
glx: Be more robust against null fbconfigs
These can happen along the internal paths for no-config contexts, and we
shouldn't crash.
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Adam Jackson [Fri, 19 Mar 2021 17:39:01 +0000 (13:39 -0400)]
glx: Move {Bind,Release}TexImage from context to screen vtable
All the other operations on drawables live there, be consistent.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Adam Jackson [Thu, 25 Mar 2021 22:13:46 +0000 (18:13 -0400)]
glx: Don't pointlesly add -D_REENTRANT to libGL's cflags
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Adam Jackson [Wed, 24 Mar 2021 16:15:03 +0000 (12:15 -0400)]
glx: Remove some #if 0'd DRI config attribute fetch
We've never read any of this out. The transparency stuff we've never
implemented and the shift/mask stuff doesn't vary independently enough
to need to match on.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Adam Jackson [Thu, 25 Mar 2021 17:51:51 +0000 (13:51 -0400)]
glx: Clean up fbconfig attribute handling
Move the macros defining the expected number of attributes into the same
file as their consumer, remove a pointless maximum, and allocate more
space for attribs on the stack to avoid malloc in the common case.
glxext.c knows about 46 config attribs, 46 - 18 = 28, round up to 32 to
future proof a bit.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Adam Jackson [Thu, 25 Mar 2021 17:41:41 +0000 (13:41 -0400)]
glx: Default sRGBCapable in the same place as the other config attribs
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9992>
Mike Blumenkrantz [Tue, 13 Apr 2021 22:21:28 +0000 (18:21 -0400)]
aux/trace: use ralloc_free for ralloc()ed state pointers
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10221>
Iván Briano [Fri, 9 Apr 2021 21:42:53 +0000 (14:42 -0700)]
intel, anv: propagate robustness setting to nir_opt_load_store_vectorize
Closes #4309
Fixes dEQP-VK-robustness.robustness2.*.readonly.*
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10147>
Jason Ekstrand [Tue, 6 Apr 2021 22:54:07 +0000 (15:54 -0700)]
intel: fix querying mip levels on null surfaces on SKL and prior
When a surface of type SURFTYPE_NULL is accessed by resinfo, the MIPCount
returned is undefined instead of 0.
Closes #4309
Fixes dEQP-VK.robustness.robustness2.*.sampled_image.*.null_descriptor.*
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10147>
Ella-0 [Wed, 27 Jan 2021 14:16:08 +0000 (14:16 +0000)]
glsl: build without bison
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8739>
Alyssa Rosenzweig [Sat, 10 Apr 2021 02:14:14 +0000 (07:44 +0530)]
docs: Add some notes on building for macOS
I intend this page to grow as I explore more about Mesa/Darwin.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10152>
Daniel Schürmann [Mon, 22 Feb 2021 13:58:37 +0000 (14:58 +0100)]
aco/cssa: don't create parallelcopies for constants and exec
if we are able to spill these directly.
Totals from 4913 (3.60% of 136546) affected shaders (Raven):
SpillSGPRs: 16021 -> 15451 (-3.56%); split: -3.87%, +0.31%
CodeSize:
58102020 ->
57371464 (-1.26%); split: -1.26%, +0.00%
Instrs:
11411454 ->
11230105 (-1.59%); split: -1.59%, +0.00%
Latency:
555706331 ->
550058635 (-1.02%); split: -1.07%, +0.05%
InvThroughput:
273023354 ->
271854469 (-0.43%); split: -0.44%, +0.01%
SClause: 385168 -> 385371 (+0.05%); split: -0.01%, +0.06%
Copies: 1342084 -> 1175762 (-12.39%); split: -12.40%, +0.01%
Branches: 392619 -> 378662 (-3.55%); split: -3.56%, +0.00%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Thu, 18 Feb 2021 20:07:08 +0000 (21:07 +0100)]
aco/cssa: rewrite lower_to_cssa pass
The previous pass was based on misconceptions and
rounded up with bug fixes. The new pass is entirely
rewritten and basically just one-to-one from the paper:
"Revisiting Out-of-SSA Translation for Correctness, CodeQuality, and Efficiency"
by B. Boissinot et al.
It also incorporates the value-equality testing.
The regressions are mainly due to creating parallelcopies for
exec phis at loop headers (mitigated in the next commit).
Totals from 4933 (3.61% of 136546) affected shaders (Raven):
SpillSGPRs: 16249 -> 16527 (+1.71%); split: -0.28%, +1.99%
SpillVGPRs: 1771 -> 1595 (-9.94%)
CodeSize:
57544436 ->
58280304 (+1.28%); split: -0.00%, +1.28%
Scratch: 176128 -> 179200 (+1.74%)
Instrs:
11265783 ->
11445884 (+1.60%); split: -0.00%, +1.60%
Latency:
552596156 ->
555880540 (+0.59%); split: -0.53%, +1.13%
InvThroughput:
271431862 ->
273097423 (+0.61%); split: -0.18%, +0.79%
VClause: 160240 -> 160241 (+0.00%); split: -0.02%, +0.02%
SClause: 386863 -> 386685 (-0.05%); split: -0.07%, +0.02%
Copies: 1180801 -> 1345633 (+13.96%); split: -0.02%, +13.98%
Branches: 379129 -> 393052 (+3.67%); split: -0.01%, +3.69%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Thu, 4 Mar 2021 15:46:54 +0000 (16:46 +0100)]
aco: add new reindex_ssa() pass
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Thu, 4 Mar 2021 15:31:22 +0000 (16:31 +0100)]
aco: fix kill flags on phi operands
Fossil-db changes are likely due to how the CSSA pass works.
Totals from 1782 (1.31% of 136546) affected shaders (Raven):
CodeSize:
25333292 ->
25294020 (-0.16%); split: -0.16%, +0.00%
Instrs: 4916059 -> 4908218 (-0.16%); split: -0.16%, +0.00%
Latency:
282860167 ->
282707176 (-0.05%); split: -0.08%, +0.03%
InvThroughput:
136487564 ->
136394958 (-0.07%); split: -0.12%, +0.05%
VClause: 74791 -> 74795 (+0.01%)
Copies: 542115 -> 534280 (-1.45%); split: -1.48%, +0.04%
Branches: 168977 -> 168966 (-0.01%); split: -0.01%, +0.01%
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Mon, 22 Feb 2021 13:55:45 +0000 (14:55 +0100)]
aco: lower p_spill with constants correctly
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Fri, 26 Mar 2021 13:12:43 +0000 (13:12 +0000)]
aco/spill: use correct next_use_distances at loop header
To decide which variables to spill, we must use the distances at the
beginning of the loop-header, and not the distances at the end of the
loop-preheader. The difference are that the former includes phis which are
viable to be spilled as opposed to the phi operands which would be reloaded
by add_coupling_code(), ending up in potentially too high register pressure
before the loop.
Totals from 206 (0.15% of 136546) affected shaders (Raven):
SpillSGPRs: 5154 -> 5000 (-2.99%)
CodeSize: 3654072 -> 3647184 (-0.19%); split: -0.19%, +0.00%
Instrs: 701482 -> 700526 (-0.14%); split: -0.14%, +0.00%
Latency:
40988780 ->
40872506 (-0.28%); split: -0.29%, +0.00%
InvThroughput:
20364560 ->
20306006 (-0.29%)
SClause: 20192 -> 20198 (+0.03%)
Copies: 77732 -> 77688 (-0.06%); split: -0.08%, +0.03%
Branches: 24204 -> 24050 (-0.64%)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Mon, 22 Feb 2021 17:02:24 +0000 (18:02 +0100)]
aco/spill: refactor live-in registerDemand calculation
This also fixes some hypothetical issue for loops without phis
and for loops with higher register pressure at the end of the
loop preheader.
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Mon, 22 Feb 2021 14:58:46 +0000 (15:58 +0100)]
aco/spill: refactor some more spill decision taking
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Mon, 22 Feb 2021 13:57:28 +0000 (14:57 +0100)]
aco/spill: don't count phis as variable access
This increases the chance of evicting phis
if these have longer next-use distances.
Totals from 6 (0.00% of 146267) affected shaders (Navi10):
CodeSize: 476992 -> 464388 (-2.64%)
Instrs: 81785 -> 79952 (-2.24%)
VClause: 2380 -> 2374 (-0.25%)
Copies: 26836 -> 25131 (-6.35%)
Branches: 2494 -> 2492 (-0.08%)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Mon, 22 Feb 2021 13:06:05 +0000 (14:06 +0100)]
aco/spill: spill phi constants and exec directly to VGPR
This lets us avoid some CSSA copies.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Mon, 22 Feb 2021 10:00:22 +0000 (11:00 +0100)]
aco/spill: reload spilled exec masks directly to exec
This handles the case of
exec = p_linear_phi %a, %b
where %a or %b might have been spilled.
By directly reloading these variables into the exec mask register,
we can avoid additional CSSA parallelcopies.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Daniel Schürmann [Wed, 17 Feb 2021 17:29:48 +0000 (18:29 +0100)]
aco/spill: refactor spill decision taking
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9196>
Boris Brezillon [Tue, 13 Apr 2021 10:54:44 +0000 (12:54 +0200)]
panfrost: Pass a tile enable map to avoid reloading untouched tiles
We only do that when there are more than one damage rectangle and the
number of tiles to reload is significantly lower than the total number
of tiles covered by the damage extent, otherwise the overhead of the
TEM read might defeat the optimization that we might get from using one.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Tue, 13 Apr 2021 10:51:48 +0000 (12:51 +0200)]
panfrost: Kill the old tile-buffer preload logic
Now that the gallium driver uses the pan_preload() helpers we can get
rid of the code in pan_blit.c and all its dependencies.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:59:25 +0000 (09:59 +0200)]
panfrost: Use the generic preload and FB helpers in the gallium driver
We also rework the code to have the FB descriptor shared by the tiler
and fragment jobs, instead of allocating a separate FB descriptor for
tiler jobs.
The new implementation seems to fix a few dEQP failures on T720.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Tue, 13 Apr 2021 10:24:17 +0000 (12:24 +0200)]
panfrost: Fix partial update
The KHR_partial_update spec says:
"
If EGL_EXT_buffer_age is supported, the contents of the buffer inside
the damage region may also be relied upon to contain the same content
as the last time they were defined for the current back buffer.
"
but we currently assume that everything inside the damage region will
be overwritten by new data and that the previous content doesn't need
to be reloaded.
Let's get rid of the damage rect inversion logic for now and reload
everything inside the damage extent. We will optimize things further
down the line, using pre-frame DCDs on Bifrost, and a tile enable map
on Midgard.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Tue, 13 Apr 2021 10:16:41 +0000 (12:16 +0200)]
panfrost: Create a blitter library to replace the existing preload helpers
pan_blitter.c is meant to replace the pan_blit.c which currently
provides helpers to preload the tile buffer. Some changes
are worth mentioning:
- we use pre-frame DCDs on Bifrost (Midgard still uses a tiler job
to preload the tile buffer)
- the blit shaders are now stored in a hash table and created lazily
- we now cache blend shader binaries and blit RSDs too
This library will soon be extended to cover regular blits.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 14:00:26 +0000 (16:00 +0200)]
panfrost: Always pass a non-NULL screen to set_damage_region()
We will soon have a different handling for Bifrost, and we need to know
which GPU we're targeting to choose the right path.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:39:10 +0000 (15:39 +0200)]
panfrost: Extend pan_fb_info to allow passing pre/post frame DCDs
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:38:12 +0000 (15:38 +0200)]
panfrost: Extend pan_fb_info to allow passing a tile enable map
We will use this tile enable map to implement KHR_partial_update and
replace the current solution where the preload process is done by
inverting damage regions, merging the resulting inverted regions and
issuing preloading draws for those rectangles.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:31:16 +0000 (15:31 +0200)]
panfrost: Decode pre/post frame DCDs
Bifrost FB descritptors can be attached 3 DCDs describing pre/post frame
operations (pre frames DCDs can be used to preload the tile buffers).
Decode them when mode != NEVER.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:27:53 +0000 (15:27 +0200)]
panfrost: s/pandecode_vertex_tiler_postfix_pre/pandecode_dcd/
We will soon use this function to decode pre/post frame DCDs which are
not part of a job descriptor.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:23:11 +0000 (15:23 +0200)]
panfrost: Add the early ZS pre frame mode
We will use that one when preloading ZS buffers.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:22:12 +0000 (15:22 +0200)]
panfrost: Add align info to the draw and draw padding definitions
Needed if we want to allocate pre/post frame draw descriptors.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 7 Apr 2021 13:34:22 +0000 (15:34 +0200)]
panfrost: Add an helper to emit fragment jobs
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:56:19 +0000 (09:56 +0200)]
panfrost: Add various helpers to simplify FB desc emission
Now that image and image views are gallium-agnostic and contain enough
information, we can provide generic helpers to emit FB descriptors and
their dependencies, thread storage and tiler descriptors.
This helpers will be re-used in the Vulkan driver.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 2 Apr 2021 13:06:52 +0000 (15:06 +0200)]
pan/midg: Use the sampler index passed to the texture instruction
Sampler index and texture index can differ.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:52:29 +0000 (09:52 +0200)]
panfrost: Pass a const device to panfrost_sample_positions()
This function doesn't modify the dev object, we can constify this
argument.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:50:41 +0000 (09:50 +0200)]
panfrost: Provide a helper to retrieve image surface pointers
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Wed, 31 Mar 2021 07:49:00 +0000 (09:49 +0200)]
panfrost: Provide a helper to calculate the polygon list size
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 15:24:47 +0000 (16:24 +0100)]
panfrost: Pass an image view to panfrost_new_texture()
pan_image_view contains everything we need to emit a texture
descriptor. Pass this object instead of the dozen of arguments
we have now.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 10:14:28 +0000 (11:14 +0100)]
panfrost: Patch the gallium driver to use pan_image_layout_init()
Now that we have a generic implementation, we can use it and get rid
of panfrost_setup_layout().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 10:13:05 +0000 (11:13 +0100)]
panfrost: Add a pan_image_layout_init() helper
We will need it for Vulkan.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 17:50:20 +0000 (18:50 +0100)]
panfrost: Move special Z32_S8X24 case out of panfrost_setup_layout()
We are about to move the panfrost_setup_layout() logic out of the
gallium driver, and the Z32_S8X24 split is not mandatory (some GPU
support this format natively). Let's move this special case out of
panfrost_setup_layout() and patch the format of the first plane
instead.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 17:35:52 +0000 (18:35 +0100)]
panfrost: Move out-of-band CRC info to pan_image
We already have the data BO stored there, let's move the out-of-band
CRC BO too. We also add a CRC mode to pan_image_layout so we can easily
know where the CRC resides.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 17:12:12 +0000 (18:12 +0100)]
panfrost: Add an offset field so we can attach a sub-buffer to an image
Needed for Vulkan.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 16:33:47 +0000 (17:33 +0100)]
panfrost: Split pan_image in two
Move the image view bit out of pan_image and create a separate
pan_image_view struct. Once this is done we can embed a pan_image
object in panfrost_resource which will be referenced by the image
view that we pass to panfrost_load_{midgard,bifrost}().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 15:31:19 +0000 (16:31 +0100)]
panfrost: Add extra info to the pan_image_layout struct
This means duplicating some of the bits we already have in the
pipe_resource object embedded in panfrost_resource, but if will also
allow us to move some code out of the gallium driver without requiring
copy those fields every time we call a generic helper.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Fri, 26 Mar 2021 18:12:39 +0000 (19:12 +0100)]
panfrost: Stop passing a depth > 1 when creating 2D textures
The depth field is ignored if dim != 3D, but it's a bit confusing.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 15:28:03 +0000 (16:28 +0100)]
panfrost: Add a format field to pan_image_layout
We will need this information at the layout level if we want to move
some of the code out of the gallium driver and share it with the
Vulkan driver. Let's get rid of panfrost_resource.internal_format which
basically encodes the same thing.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 14:17:08 +0000 (15:17 +0100)]
panfrost: Move image states out of pan_image_layout
The layout is supposed to encode image miplevels/surfaces layout, not
the state data stored in the buffers. It doesn't matter for a gallium
driver, since resources are expected to hold both a layout and a state,
but Vulkan is a bit different. In Vulkan, the image state is explicitly
passed by the user when starting a render pass (vkCmdBeginRenderPass()),
and might evolve depending on the operation done in this render pass.
This state is not effective until the command buffer is queued and
executed. For these reasons, keeping the image state attached to the
VkImage object is not an option, but we'd still like to re-use the
layout and state objects, and all common helpers acting on those objects.
Let's move the state bits out of the layout to make that possible.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Boris Brezillon [Thu, 25 Mar 2021 13:19:37 +0000 (14:19 +0100)]
panfrost: s/panfrost_slice/pan_image_slice_layout/
We are about to move slice states out of the panfrost_slice object,
but before we do that, let's rename the existing struct to reflect what
this object refers to.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10033>
Connor Abbott [Mon, 7 Dec 2020 13:54:25 +0000 (14:54 +0100)]
vtn: Handle ZeroExtend/SignExtend image operands
These decorations allow you to override the signedness of image
instructions. This means that we have to override the type we get from
the sampled image.
Apparently both Intel and AMD get the type from the descriptor rather
than the instruction, but this appears to not be the case with Adreno,
which is why this wasn't noticed until now. So this probably won't fix
any preexisting bugs, but it's required to fix
dEQP-VK.image.extend_operands_spirv1p4.* when exposing VK_KHR_spirv_1_4
on turnip.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7968>
Lucas Stach [Tue, 13 Apr 2021 14:42:57 +0000 (16:42 +0200)]
Revert remaining half of "gallium/dri2: Pass the resource that corresponds to the plane"
As documented in
6ec7e0d40664 (gallium: document convention for get_handle
calls on multi-planar resources) it's the drivers responsibility to walk
the chain of resources for multi-planar resources. The get_handle interface
should always be called with the base resource by the frontend.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10212>
Juan A. Suarez Romero [Tue, 13 Apr 2021 08:00:14 +0000 (10:00 +0200)]
v3dv: fix assertion
Ensure subpass_idx has a valid value; we use "-1" as invalid one.
Fixes CID#1468096 "Macro compares unsigned to 0 (NO_EFFECT)"
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10203>
Juan A. Suarez Romero [Thu, 8 Apr 2021 16:27:10 +0000 (18:27 +0200)]
v3d: use GS_BIN inputs as VS_BIN outputs
When creating the Vextex Shader bin, only store outputs that will be
read later as inputs by the Geometry Shader bin.
This fixes
KHR-GLES31.core.geometry_shader.rendering.rendering.lines_input_triangle_strip_output_line_loop_drawcall
(exposed by previous commit).
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10129>
Juan A. Suarez Romero [Thu, 8 Apr 2021 16:20:08 +0000 (18:20 +0200)]
broadcom/compiler: use VPM offsets in GS load_per_vertex input
Vertex Shader has a store_out lowering pass that converts gallium driver
locations in offsets inside the VPM.
One of the consequences is that these offsets are consecutives; that is,
if the VS stores VARYING_SLOT_VAR0.xyz and VARYING_SLOT_VAR1.xyzw, there
isn't a hole in the VPM offsets for the un-stored VARYING_SLOT_VAR0.w.
Thus we need to change how the VPM offset is computed in the Geometry
Shader when loading the inputs.
This bug is exposed by !9050.
v2 (Iago):
- Include explanatory comment.
- Use assert.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10129>
Bas Nieuwenhuizen [Tue, 13 Apr 2021 09:21:36 +0000 (11:21 +0200)]
radv: Re-enable retiling.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10037>
Juan A. Suarez Romero [Tue, 6 Apr 2021 11:24:42 +0000 (13:24 +0200)]
ci/broadcom: use SNMP to turn on/off devices
So far we were using a telnet-based script to communicate with the PoE
Switch to turn on/off the network ports the DUTs are connected.
But this script does not seem very reliable because from time to time the
switch fails to execute the steps in the script.
As the PoE Switch we use is a smart one with support for SNMP protocol,
it would be easier to use it to handle it, which allows to turn on/off
the ports without going through the nasty telnet steps
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9954>
Samuel Pitoiset [Mon, 12 Apr 2021 16:00:51 +0000 (18:00 +0200)]
radv: fix needed dynamic state for VRS
If the pipeline struct isn't found, the state might still be dynamic.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10193>
Erik Faye-Lund [Mon, 29 Mar 2021 10:45:41 +0000 (12:45 +0200)]
compiler/glsl: do not cast struct to string
When formatting the error here, we're currently casting an
ast_type_qualifier as a string.
But we don't need to use a string here at all, because we know from
context exactly what qualifier we're talking about, because the
if-statements explicitly check for the uniform-qualifier.
So let's just hard-code the format-string to reference the right
qualifier instead of the string-shenanigans. The latter cannot do the
right thing.
Fixes:
2d03f48a65a ("glsl: Add parsing for GLSL uniform blocks.")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9911>
Erik Faye-Lund [Mon, 29 Mar 2021 10:36:28 +0000 (12:36 +0200)]
compiler/glsl: drop rogue argument to _mesa_glsl_error
This arugment is not present int the format-string, so we shouldn't pass
it to _mesa_glsl_error either.
Noticed by Coverity.
Fixes:
02dc74fbd72 ("glsl: parse invocations layout qualifier for ARB_gpu_shader5")
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9911>
Marek Olšák [Mon, 8 Feb 2021 11:06:24 +0000 (06:06 -0500)]
st/mesa: fix nir_lower_io if it's done right after IO vectorization
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 14:32:25 +0000 (09:32 -0500)]
gallium: add PIPE_SHADER_CAP_FP16_CONST_BUFFERS for FP16 uniforms
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 14:44:04 +0000 (09:44 -0500)]
glsl: lower mediump uniforms to FP16 based on an option
Everything else is done - just allow it.
v2: update lower_precision_test.py
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Sun, 14 Feb 2021 12:21:31 +0000 (07:21 -0500)]
mesa: implement glGetActiveUniform for FP16 uniforms
We must return the types before lowering to 16 bits.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Sun, 14 Feb 2021 12:02:13 +0000 (07:02 -0500)]
mesa: implement glGetUniform for FP16 uniforms
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 13:44:31 +0000 (08:44 -0500)]
mesa: implement glUniform for packed FP16 uniforms
Let's just say that this passes dEQP.
If you think the _mesa_float_to_half conversions are costly, you can
enable FP16 uniforms only if the CPU supports F16C, which is fast.
Drivers will control whether this is used, not common code.
ARM will need something that is equivalent to F16C.
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Fri, 12 Feb 2021 13:14:07 +0000 (08:14 -0500)]
glsl: pack 16-bit uniforms in the NIR linker
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Alyssa Rosenzweig [Mon, 3 Aug 2020 19:21:16 +0000 (15:21 -0400)]
nir: Add varying precision linking helper (v2)
It is useful for the precisions of varyings to match across shader
stages at link-time to enable precision lowering optimizations, which
would otherwise require costly draw-time fixups.
The goal is to enable `producer->precision == consumer->precision` to be
an invariant drivers may rely on for linked shaders.
v2: keep transform feedback outputs at mediump - mareko
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> (v1)
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Mon, 8 Feb 2021 02:10:08 +0000 (21:10 -0500)]
nir: add many passes that lower and optimize 16-bit input/outputs and samplers
Added:
* a pass that renumbers bases of IO intrinsics
* a pass that converts mediump IO to 16 bits, optionally using the new
packed varying slots
* a pass that sets (forces) mediump in IO intrinsics (for testing)
* a pass that remaps VARYING_SLOT_VAR[0..15]_16BIT to VARYING_SLOT_VAR[0..31]
(if some shader stages don't want packed varyings)
* a pass that folds type conversions around texture opcodes into those
opcodes (e.g. tex(f2f32(coord), ..) is changed into tex accepting f16)
* a pass that changes (legalizes) sampler src and dst types based on specified
hw constraints (e.g. derivatives must be the same type as coordinates)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Tue, 9 Feb 2021 15:58:51 +0000 (10:58 -0500)]
nir: add new VARYING_SLOTs and shader info for packed 16-bit varyings
This allows mediump inputs and outputs to be trivially lowered into packed
16-bit varyings where 1 slot is occupied by 2 16-bit vec4s, without any
packing instructions in NIR and without any conflicts with 32-bit varyings.
The only thing that is changed is IO semantics in intrinsics to get packed
16-bit varyings.
This simplifies supporting 16-bit types for drivers that have 32-bit slots
everywhere except the fragment shader where they can do 16-bit interpolation
on either the low or high half of each slot.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Tue, 9 Feb 2021 16:08:11 +0000 (11:08 -0500)]
nir: add src and dest types to all IO loads and stores for mediump
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Marek Olšák [Mon, 8 Feb 2021 00:57:09 +0000 (19:57 -0500)]
compiler: move TEXTURE_COORD/VERTEX_GENERIC_ATTRIB limits into shader_enums.h
because they are used there.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9050>
Jesse Natalie [Mon, 12 Apr 2021 02:15:35 +0000 (19:15 -0700)]
nir_opt_deref: ptr_as_array(deref_cast<T*>(x))[0] isn't the same as x[0] if the cast has alignment
This breaks CLOn12's handling of CL CTS test_basic vector_creation for char3 (at least).
Removing this cast causes us to try to load from a deref with no alignment info.
Fixes:
99bb2a4d ("nir/opt_deref: Don't remove casts with alignment information")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
Jesse Natalie [Mon, 12 Apr 2021 02:13:44 +0000 (19:13 -0700)]
vtn: Support scoped control barriers for OpenCL too
The current handling for SPIR-V memory semantics is very specific to
the wording in the SPIR-V spec, which breaks its handling of OpenCL
(compared to what we had working downstream before merging upstream).
Update/relax the logic here to support CL's barrier(CLK_GLOBAL_MEM_FENCE);
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10165>
Marek Olšák [Mon, 5 Apr 2021 00:19:55 +0000 (20:19 -0400)]
radeonsi: unify internal compute with SSBOs in si_launch_grid_internal_ssbos
just deduplicate the code
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 23:37:01 +0000 (19:37 -0400)]
radeonsi: move binding the internal compute shader into si_launch_grid_internal
instead of doing it in each function
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 21:01:01 +0000 (17:01 -0400)]
radeonsi: enable DCC for MSAA 4x and 8x on gfx9
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Sun, 4 Apr 2021 20:58:29 +0000 (16:58 -0400)]
radeonsi: implement DCC MSAA 4x/8x fast clear using DCC equations on gfx9
MSAA 4x and 8x should only clear the first 2 samples because other samples
are uncompressed. The compute shader only clears that subset of DCC.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Fri, 19 Mar 2021 20:14:23 +0000 (16:14 -0400)]
radeonsi: fix and enable full DCC with MSAA 2x on gfx9
This enables fast clear with any clear color (not just 0/1) for bpp >= 32.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Mon, 22 Mar 2021 23:43:53 +0000 (19:43 -0400)]
ac,radeonsi: rewrite DCC retiling without the DCC retile map
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.
The RADV code is disabled.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
Marek Olšák [Tue, 23 Mar 2021 01:21:30 +0000 (21:21 -0400)]
ac/surface: limit the number of swizzle modes that can have displayable DCC
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
projects / platform / upstream / mesa.git / log