Francis Ricci [Mon, 25 Sep 2017 21:51:04 +0000 (21:51 +0000)]
Add missing include to sanitizer procmaps
llvm-svn: 314162
Eli Friedman [Mon, 25 Sep 2017 21:37:52 +0000 (21:37 +0000)]
[ARM] Add tests for vcvt followed by store.
llvm-svn: 314161
Eli Friedman [Mon, 25 Sep 2017 21:34:29 +0000 (21:34 +0000)]
[ARM] Regenerate vcvt test checks.
llvm-svn: 314160
Sanjay Patel [Mon, 25 Sep 2017 21:31:08 +0000 (21:31 +0000)]
[x86] make assertions less strict in avx512f test file
Missed a line in r314158.
llvm-svn: 314159
Sanjay Patel [Mon, 25 Sep 2017 21:27:37 +0000 (21:27 +0000)]
[x86] make assertions less strict in avx512f test file
I'm not sure why yet, but there may be differences depending on the host?
llvm-svn: 314158
Francis Ricci [Mon, 25 Sep 2017 21:26:34 +0000 (21:26 +0000)]
Fix style in sanitizer_procmaps.h
llvm-svn: 314157
Gheorghe-Teodor Bercea [Mon, 25 Sep 2017 21:25:38 +0000 (21:25 +0000)]
[OpenMP] Bugfix: output file name drops the absolute path where full path is needed.
Summary: When composing the output file name, the path to the file is being dropped. The full path is required.
Reviewers: Hahnfeld, ABataev, caomhin, carlo.bertolli, hfinkel, tra
Reviewed By: tra
Subscribers: hfinkel, tra, cfe-commits
Differential Revision: https://reviews.llvm.org/D37912
llvm-svn: 314156
Jason Molenda [Mon, 25 Sep 2017 21:23:37 +0000 (21:23 +0000)]
Remove the details of the libstdc++ implementation that were
in TestDataFormatterSkipSummary.py - I'm building this test
with the default c++ library.
Skip TestMTCSimple.py when running for i386.
llvm-svn: 314155
Gheorghe-Teodor Bercea [Mon, 25 Sep 2017 21:22:49 +0000 (21:22 +0000)]
Revert commit with wrong message.
llvm-svn: 314154
Craig Topper [Mon, 25 Sep 2017 21:15:00 +0000 (21:15 +0000)]
[InstCombine] Move an optimization from foldICmpAndConstConst to foldICmpUsingKnownBits
All this optimization cares about is knowing how many low bits of LHS is known to be zero and whether that means that the result is 0 or greater than the RHS constant. It doesn't matter where the zeros in the low bits came from. So we don't need to specifically look for an AND. Instead we can use known bits.
Differential Revision: https://reviews.llvm.org/D38195
llvm-svn: 314153
Craig Topper [Mon, 25 Sep 2017 21:14:59 +0000 (21:14 +0000)]
[X86] Don't select anyext GR32->GR64 to SUBREG_TO_REG. Use INSERT_SUBREG instead.
As far as I know SUBREG_TO_REG is stating that the upper bits are 0. But if we are just converting the GR32 with no checks, then we have no reason to say the upper bits are 0.
I don't really know how to test this today since I can't find anything that looks that closely at SUBREG_TO_REG. The test changes here seems to be some perturbance of register allocation.
Differential Revision: https://reviews.llvm.org/D38001
llvm-svn: 314152
Craig Topper [Mon, 25 Sep 2017 21:14:55 +0000 (21:14 +0000)]
[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.
llvm-svn: 314151
Gheorghe-Teodor Bercea [Mon, 25 Sep 2017 21:07:16 +0000 (21:07 +0000)]
[OpenMP] Don't throw cudalib not found error if only front-end is required.
Summary: If we only use the compiler front-end, do not throw an error about the cuda device library not being found. This allows the front-end to be run on systems where no Cuda installation is found.
Reviewers: Hahnfeld, ABataev, carlo.bertolli, caomhin, tra
Reviewed By: tra
Subscribers: hfinkel, tra, cfe-commits
Differential Revision: https://reviews.llvm.org/D37914
llvm-svn: 314150
Francis Ricci [Mon, 25 Sep 2017 20:48:51 +0000 (20:48 +0000)]
[sanitizer_common] Don't provide sanitizer_procmaps API functions where not defined
Summary:
Platforms that don't implement procmaps (primarily fuchsia and windows) still expose
the procmaps API when including sanitizer_procmaps.h, despite not implementing the functions
provided by that header. Ensure that the API is only exposed on platforms that implement it.
Reviewers: vitalybuka, alekseyshl, kubamracek
Subscribers: llvm-commits, krytarowski
Differential Revision: https://reviews.llvm.org/D38187
llvm-svn: 314149
Jake Ehrlich [Mon, 25 Sep 2017 20:37:28 +0000 (20:37 +0000)]
[llvm-objcopy] Refactor code to include initialize method
This change refactors some of the code to allow for some code
deduplication in later diffs as well as just to make adding a new
section type more self contained to the class itself. The idea for this
was first mentioned by James in D 37915 and will be used in that change
as recommended.
This change follows changes for dynamic sections but precedes support
for dynamic relocations.
Differential Revision: https://reviews.llvm.org/D38008
llvm-svn: 314148
Sanjay Patel [Mon, 25 Sep 2017 20:30:53 +0000 (20:30 +0000)]
[InstCombine] remove extract-of-select vector transform (2nd try)
The 1st attempt at this:
https://reviews.llvm.org/rL314117
was reverted at:
https://reviews.llvm.org/rL314118
because of bot fails for clang tests that were checking optimized IR. That should be fixed with:
https://reviews.llvm.org/rL314144
...so try again.
Original commit message:
The transform to convert an extract-of-a-select-of-vectors was added at:
https://reviews.llvm.org/rL194013
And a question about the validity of this transform was raised in the review:
https://reviews.llvm.org/D1539:
...but not answered AFAICT>
Most of the motivating cases in that patch are now handled by other combines. These are the tests that were added with
the original commit, but they are not regressing even after we remove the transform in this patch.
The diffs we see after removing this transform cause us to avoid increasing the instruction count, so we don't want to do
those transforms as canonicalizations.
The motivation for not turning a vector-select-of-vectors into a scalar operation is shown in PR33301:
https://bugs.llvm.org/show_bug.cgi?id=33301
...in those cases, we'll get vector ops with this patch rather than the vector/scalar mix that we currently see.
Differential Revision: https://reviews.llvm.org/D38006
llvm-svn: 314147
Tobias Grosser [Mon, 25 Sep 2017 20:27:15 +0000 (20:27 +0000)]
[ScopInfo] Allow invariant loads in branch conditions
In case the value used in a branch condition is a load instruction, assume this
load to be invariant.
llvm-svn: 314146
Wei Mi [Mon, 25 Sep 2017 19:57:59 +0000 (19:57 +0000)]
Reinstall the patch "Use EmitPointerWithAlignment to get alignment information of the pointer used in atomic expr" after fixing PR31620.
This is to fix PR34347. EmitAtomicExpr now only uses alignment information from
Type, instead of Decl, so when the declaration of an atomic variable is marked
to have the alignment equal as its size, EmitAtomicExpr doesn't know about it and
will generate libcall instead of atomic op. The patch uses EmitPointerWithAlignment
to get the precise alignment information.
Differential Revision: https://reviews.llvm.org/D37310
llvm-svn: 314145
Sanjay Patel [Mon, 25 Sep 2017 19:56:57 +0000 (19:56 +0000)]
[x86] remove RUNs that were checking fully optimized IR
Clang regression tests that depend on the optimizer can break
when there are changes to LLVM...as in:
https://reviews.llvm.org/rL314117
llvm-svn: 314144
Benjamin Kramer [Mon, 25 Sep 2017 19:42:20 +0000 (19:42 +0000)]
[Hexagon] Avoid unused variable warnings in Release builds.
No functionality change intended.
llvm-svn: 314143
Justin Lebar [Mon, 25 Sep 2017 19:41:56 +0000 (19:41 +0000)]
Revert "[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.", rL314135.
Causing assertion failures on macos:
> Assertion failed: (Num < NumOperands && "Invalid child # of SDNode!"),
> function getOperand, file
> /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm/include/llvm/CodeGen/SelectionDAGNodes.h,
> line 835.
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42739/testReport/LLVM/CodeGen_NVPTX/surf_read_cuda_ll/
llvm-svn: 314142
Alexander Shaposhnikov [Mon, 25 Sep 2017 19:32:33 +0000 (19:32 +0000)]
[analyzer] Fix crash on modeling of pointer arithmetic
This patch fixes analyzer's crash on the newly added test case
(see also https://bugs.llvm.org/show_bug.cgi?id=34374).
Pointers subtraction appears to be modeled incorrectly
in the following example:
char* p;
auto n = p - reinterpret_cast<char*>((unsigned long)1);
In this case the analyzer (built without this patch)
tries to create a symbolic value for the difference
treating reinterpret_cast<char*>((unsigned long)1)
as an integer, that is not correct.
Differential revision: https://reviews.llvm.org/D38214
Test plan: make check-all
llvm-svn: 314141
Konstantin Belochapka [Mon, 25 Sep 2017 19:26:48 +0000 (19:26 +0000)]
[X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86-asm-syntax=intel (PR34617).
Fix for incorrect code generation when x86-asm-syntax=intel.
Differential Revision: https://reviews.llvm.org/D37945
llvm-svn: 314140
Craig Topper [Mon, 25 Sep 2017 19:26:08 +0000 (19:26 +0000)]
[SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors
This teach simplifyDemandedBits to handle constant splat vector shifts.
This required changing some uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount.
I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here.
I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change.
Differential Revision: https://reviews.llvm.org/D37665
llvm-svn: 314139
Martin Storsjo [Mon, 25 Sep 2017 19:24:45 +0000 (19:24 +0000)]
[MinGW] Don't link -lmsvcrt if a different msvcrt version is to be linked
Differential Revision: https://reviews.llvm.org/D37530
llvm-svn: 314138
Alexey Bataev [Mon, 25 Sep 2017 19:12:59 +0000 (19:12 +0000)]
[SLP] Add a test for PR32086, NFC.
llvm-svn: 314137
Krzysztof Parzyszek [Mon, 25 Sep 2017 19:12:55 +0000 (19:12 +0000)]
[Hexagon] Better determination of register classes in bit tracker
Add two callbacks to MachineEvaluator, so that specific implementations
can specify more details about register classes:
- composeWithSubRegIndex(RC,Idx), to provide the register class for a
register from RC used in conjunction with a subregister index Idx.
- getPhysRegBitWidth(Reg), to provide the size in bits of the given
physical register.
llvm-svn: 314136
Artem Belevich [Mon, 25 Sep 2017 18:53:57 +0000 (18:53 +0000)]
[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
Differential Revision: https://reviews.llvm.org/D38191
llvm-svn: 314135
Krzysztof Parzyszek [Mon, 25 Sep 2017 18:49:42 +0000 (18:49 +0000)]
[Hexagon] Make getHexagonSubRegIndex take reference instead of pointer
llvm-svn: 314134
Craig Topper [Mon, 25 Sep 2017 18:43:13 +0000 (18:43 +0000)]
[AVX-512] Replace large number of explicit patterns that check for insert_subvector with zero after masked compares with fewer patterns with predicate
This replaces the large number of patterns that handle every possible case of zeroing after a masked compare with a few simpler patterns that use a predicate to check for a masked compare producer.
This is similar to what we do for detecting free GR32->GR64 zero extends and free xmm->ymm/zmm zero extends.
This shrinks the isel table from ~590k to ~531k. This is a roughly 10% reduction in size.
Differential Revision: https://reviews.llvm.org/D38217
llvm-svn: 314133
Jason Molenda [Mon, 25 Sep 2017 18:19:39 +0000 (18:19 +0000)]
Initial patchset to get the testsuite running against armv7 and arm64 iOS devices.
Normal customer devices won't be able to run these tests, we're hoping to get
a public facing bot set up at some point. Both devices pass the testsuite without
any errors or failures.
I have seen some instability with the armv7 test runs, I may submit additional patches
to address this. arm64 looks good.
I'll be watching the bots for the rest of today; if any problems are introduced by
this patch I'll revert it - if anyone sees a problem with their bot that I don't
see, please do the same. I know it's a rather large patch.
One change I had to make specifically for iOS devices was that debugserver can't
create files. There were several tests that launch the inferior process redirecting
its output to a file, then they retrieve the file. They were not trying to test
file redirection in these tests, so I rewrote those to write their output to a file
directly.
llvm-svn: 314132
Hongbin Zheng [Mon, 25 Sep 2017 18:10:36 +0000 (18:10 +0000)]
[SimplifyIndvar] Minor change to refine r314125, NFC
llvm-svn: 314130
Artem Belevich [Mon, 25 Sep 2017 17:55:26 +0000 (17:55 +0000)]
[CUDA] Fix names of __nvvm_vote* intrinsics.
Also fixed a syntax error in activemask().
Differential Revision: https://reviews.llvm.org/D38188
llvm-svn: 314129
Arnold Schwaighofer [Mon, 25 Sep 2017 17:51:33 +0000 (17:51 +0000)]
ARM: One more fix for swifterror CSR set
We use a differently ordered CSR set if the frame pointer is pushed. Add a
matching ..._SwiftError version.
llvm-svn: 314128
Eugene Zemtsov [Mon, 25 Sep 2017 17:41:16 +0000 (17:41 +0000)]
Use socketpair on all Unix platforms
Using TCP sockets is insecure against local attackers, and possibly
against remote attackers too (some vulnerabilities may allow tricking a
browser to make a request to localhost). Use socketpair (which is immune
to such attacks) on all Unix platforms.
Patch by Demi Marie Obenour < demiobenour@gmail.com >
Differential Revision: https://reviews.llvm.org/D33213
llvm-svn: 314127
Rui Ueyama [Mon, 25 Sep 2017 17:40:21 +0000 (17:40 +0000)]
Use UINT64_MAX instead of implicitly-type-converted -1.
llvm-svn: 314126
Hongbin Zheng [Mon, 25 Sep 2017 17:39:40 +0000 (17:39 +0000)]
[SimplifyIndvar] Replace the srem used by IV if we can prove both of its operands are non-negative
Since now SCEV can handle 'urem', an 'urem' is a better canonical form than an 'srem' because it has well-defined behavior
This is a follow up of D34598
Differential Revision: https://reviews.llvm.org/D38072
llvm-svn: 314125
Yi Kong [Mon, 25 Sep 2017 17:36:54 +0000 (17:36 +0000)]
[Sema] Null check in BuildDeclarationNameExpr
Qualtype may point to null if we cannot infer its type yet.
Fixes PR33843
Differential Revision: https://reviews.llvm.org/D38158
llvm-svn: 314124
Benjamin Kramer [Mon, 25 Sep 2017 17:35:38 +0000 (17:35 +0000)]
[ARM] Fix -Wdangling-else warning.
A ternary is clearer here. No functionality change.
llvm-svn: 314123
Chris Bieneman [Mon, 25 Sep 2017 17:31:40 +0000 (17:31 +0000)]
Revert "Initial patchset to get the testsuite running against armv7 and arm64 iOS devices. Normal customer devices won't be able to run these devices, we're hoping to get a public facing bot set up at some point. Both devices pass the testsuite without any errors or failures."
This patch has been causing LLDB test failures on ObjC tests. A test log
may still be available here:
http://lab.llvm.org:8080/green/view/LLDB/job/lldb/1650/
This reverts commit r314038.
llvm-svn: 314122
Arnold Schwaighofer [Mon, 25 Sep 2017 17:19:50 +0000 (17:19 +0000)]
ARM: Use the proper swifterror CSR list on platforms other than darwin
Noticed by inspection
llvm-svn: 314121
Rui Ueyama [Mon, 25 Sep 2017 17:19:17 +0000 (17:19 +0000)]
Use a temporary varaible to improve readability. NFC.
llvm-svn: 314120
Benjamin Kramer [Mon, 25 Sep 2017 17:16:47 +0000 (17:16 +0000)]
[clangd] Fix missing "message" key when responding with unsupported method
The language server protocol dictates that a ResponseError should have a
[message string][1] describing the error. This adds a simple message to the
error and a simple test.
[1]: https://github.com/Microsoft/language-server-protocol/blob/master/protocol.md#response-message
Patch by Raoul Wols!
Differential Revision: https://reviews.llvm.org/D38225
llvm-svn: 314119
Sanjay Patel [Mon, 25 Sep 2017 17:00:04 +0000 (17:00 +0000)]
revert r314117 because there are bogus clang tests that depend on the optimizer
llvm-svn: 314118
Sanjay Patel [Mon, 25 Sep 2017 16:41:34 +0000 (16:41 +0000)]
[InstCombine] remove extract-of-select vector transform
The transform to convert an extract-of-a-select-of-vectors was added at:
rL194013
And a question about the validity of this transform was raised in the review:
https://reviews.llvm.org/D1539:
...but not answered AFAICT>
Most of the motivating cases in that patch are now handled by other combines. These are the tests that were added with
the original commit, but they are not regressing even after we remove the transform in this patch.
The diffs we see after removing this transform cause us to avoid increasing the instruction count, so we don't want to do
those transforms as canonicalizations.
The motivation for not turning a vector-select-of-vectors into a scalar operation is shown in PR33301:
https://bugs.llvm.org/show_bug.cgi?id=33301
...in those cases, we'll get vector ops with this patch rather than the vector/scalar mix that we currently see.
Differential Revision: https://reviews.llvm.org/D38006
llvm-svn: 314117
Tobias Grosser [Mon, 25 Sep 2017 16:37:15 +0000 (16:37 +0000)]
[ScopInfo] Allow uniform branch conditions
If all but one branch come from an error condition and the incoming value from
this branch is a constant, we can model this branch.
llvm-svn: 314116
Michael Liao [Mon, 25 Sep 2017 16:21:21 +0000 (16:21 +0000)]
Remove trailing whitespaces.
llvm-svn: 314115
Reid Kleckner [Mon, 25 Sep 2017 16:14:53 +0000 (16:14 +0000)]
[DebugInfo] Sort the SDDbgValue list before assuming it is in IR order
Summary:
This code iterates the 'Orders' vector in parallel with the DbgValue
list, emitting all DBG_VALUEs that occurred between the last IR order
insertion point and the next insertion point. This assumes the
SDDbgValue list is sorted in IR order, which it usually is. However, it
is not sorted when a node with a debug value is replaced with another
one. When this happens, TransferDbgValues is called, and the new value
is added to the end of the list.
The problem can be solved by stably sorting the list by IR order.
Reviewers: aprantl, Ka-Ka
Reviewed By: aprantl
Subscribers: MatzeB, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D38197
llvm-svn: 314114
Reid Kleckner [Mon, 25 Sep 2017 16:14:39 +0000 (16:14 +0000)]
Use {} instead of make_pair and an iterator for the insertion point, NFC
llvm-svn: 314113
Jan Vesely [Mon, 25 Sep 2017 16:07:34 +0000 (16:07 +0000)]
Rework atomic ops to use clang builtins rather than llvm asm
reviewer: Aaron Watry
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 314112
Jan Vesely [Mon, 25 Sep 2017 16:04:37 +0000 (16:04 +0000)]
prepare_builtins: Fix compile breakage with older LLVM
Fixes r314050
reviewer: Tom Stellard
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 314111
Kostya Kortchinsky [Mon, 25 Sep 2017 15:12:08 +0000 (15:12 +0000)]
[scudo] Scudo thread specific data refactor, part 2
Summary:
Following D38139, we now consolidate the TSD definition, merging the shared
TSD definition with the exclusive TSD definition. We introduce a boolean set
at initializaton denoting the need for the TSD to be unlocked or not. This
adds some unused members to the exclusive TSD, but increases consistency and
reduces the definitions fragmentation.
We remove the fallback mechanism from `scudo_allocator.cpp` and add a fallback
TSD in the non-shared version. Since the shared version doesn't require one,
this makes overall more sense.
There are a couple of additional cosmetic changes: removing the header guards
from the remaining `.inc` files, added error string to a `CHECK`.
Question to reviewers: I thought about friending `getTSDAndLock` in `ScudoTSD`
so that the `FallbackTSD` could `Mutex.Lock()` directly instead of `lock()`
which involved zeroing out the `Precedence`, which is unused otherwise. Is it
worth doing?
Reviewers: alekseyshl, dvyukov, kcc
Reviewed By: dvyukov
Subscribers: srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D38183
llvm-svn: 314110
Michael Zuckerman [Mon, 25 Sep 2017 14:50:38 +0000 (14:50 +0000)]
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF8 stride 4):
This patch expands the support of lowerInterleavedStore to 8x8i stride 4.
LLVM creates suboptimal shuffle code-gen for AVX2.
In overall, this patch is a specific fix for the pattern (Strid=4 VF=8) and we plan to include more patterns in the future.
The patch goal is to optimize the following sequence:
At the end of the computation, we have xmm2, xmm0, xmm12 and xmm3 holding
each 8 chars:
c0, c1, , c7
m0, m1, , m7
y0, y1, , y7
k0, k1, ., k7
And these need to be transposed/interleaved and stored like so:
c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....
Reviewers
DavidKreitzer
Farhana
zvi
igorb
guyblank
RKSimon
Ayal
Differential Revision: https://reviews.llvm.org/D36058
Change-Id: I3cc5c2ca5d6318901c192a4428493b99ef424c32
llvm-svn: 314109
Evgeny Mankov [Mon, 25 Sep 2017 14:42:15 +0000 (14:42 +0000)]
[ELF][fix] Using statically linked lld leads to segmentation fault on linking ELF
[Synopsys]
Using function elf::link(...) leads to segmentation fault on its second call. First call finishes correctly.
[Solution]
Clear the rest of globals.
Reviewed by: George Rimar and Rui Ueyama
Differential Revision: http://reviews.llvm.org/D38131
llvm-svn: 314108
Sylvestre Ledru [Mon, 25 Sep 2017 14:08:35 +0000 (14:08 +0000)]
Fix clangd when built with LLVM_LINK_LLVM_DYLIB=ON
Reviewers: malaperle, malaperle-ericsson, bkramer
Reviewed By: bkramer
Subscribers: bkramer, mgorny, ilya-biryukov, cfe-commits
Differential Revision: https://reviews.llvm.org/D38228
llvm-svn: 314107
Nemanja Ivanovic [Mon, 25 Sep 2017 14:05:46 +0000 (14:05 +0000)]
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.
llvm-svn: 314106
Chad Rosier [Mon, 25 Sep 2017 14:05:00 +0000 (14:05 +0000)]
[AArch64] Add basic support for Qualcomm's Saphira CPU.
llvm-svn: 314105
Michael Zuckerman [Mon, 25 Sep 2017 13:49:32 +0000 (13:49 +0000)]
[Clang] Adding missing feature to goldmont
Change-Id: I6c22478d16b8e02ce60dae2f8c80d43bc5ab3a9c
llvm-svn: 314104
Michael Zuckerman [Mon, 25 Sep 2017 13:45:31 +0000 (13:45 +0000)]
Adding missing feature to goldmont.
Change-Id: I1ddc619169fae6a56308deef8dae5db3da702cf4
llvm-svn: 314103
Jina Nahias [Mon, 25 Sep 2017 13:38:08 +0000 (13:38 +0000)]
fixing a bug in mask[z]_set1 intrinsic
Differential Revision: https://reviews.llvm.org/D38231
Change-Id: I80bbff9cbe93e4be54d8a761ef9723edf3f57c57
llvm-svn: 314102
Alexey Bataev [Mon, 25 Sep 2017 13:34:59 +0000 (13:34 +0000)]
[SLP] Support for horizontal min/max reduction.
Summary:
SLP vectorizer supports horizontal reductions for Add/FAdd binary operations. Patch adds support for horizontal min/max reductions.
Function getReductionCost() is split to getArithmeticReductionCost() for binary operation reductions and getMinMaxReductionCost() for min/max reductions.
Patch fixes PR26956.
Reviewers: spatel, mkuper, hfinkel, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D27846
llvm-svn: 314101
Simon Dardis [Mon, 25 Sep 2017 13:25:34 +0000 (13:25 +0000)]
[mips][compiler-rt] Disable sem_init_glibc.cc for MIPS64.
This test can't pass on MIPS64 due to the lack of versioned interceptors
for asan and company. The interceptors bind to the earlier version of
sem_init rather than the latest version. For MIPS64el this causes an
accidental pass while MIPS64 big endian fails due reading back a
different 32bit word to what sem_init wrote when the test is corrected
to use 64bit atomics.
llvm-svn: 314100
George Rimar [Mon, 25 Sep 2017 09:46:33 +0000 (09:46 +0000)]
[ELF] - Simplify removeUnusedSyntheticSections a bit.
Previously`InX::Got` and InX::MipsGot synthetic sections
were not removed if ElfSym::GlobalOffsetTable was defined.
ElfSym::GlobalOffsetTable is a symbol for _GLOBAL_OFFSET_TABLE_.
Patch moves ElfSym::GlobalOffsetTable check out from removeUnusedSyntheticSections.
Also note that there was no point to check ElfSym::GlobalOffsetTable for MIPS case
because InX::MipsGot::empty() always returns false for non-relocatable case, and in case
of relocatable output we do not create special symbols anyways.
Differential revision: https://reviews.llvm.org/D37623
llvm-svn: 314099
George Rimar [Mon, 25 Sep 2017 09:41:32 +0000 (09:41 +0000)]
[ELF] - Report orphan sections if -verbose given.
When -verbose is specified, patch outputs names of each input orphan section
assigned to output.
Differential revision: https://reviews.llvm.org/D37517
llvm-svn: 314098
George Rimar [Mon, 25 Sep 2017 09:31:43 +0000 (09:31 +0000)]
[ELF] - LTO: do not optimize away symbols accessed from linkerscript.
Previously when BC file had global variable that was accessed from script,
it was optimized away or inlined by IPO.
In this patch I add symbols at left side of assignment expression as LinkerRedefined,
what prevents optimization for them.
Differential revision: https://reviews.llvm.org/D37059
llvm-svn: 314097
Clement Courbet [Mon, 25 Sep 2017 06:35:16 +0000 (06:35 +0000)]
[CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> TargetTransformInfo::enableMemCmpExpansion.
Summary:
Right now there are two functions with the same name, one does the work
and the other one returns true if expansion is needed. Rename
TargetTransformInfo::expandMemCmp to make it more consistent with other
members of TargetTransformInfo.
Remove the unused Instruction* parameter.
Differential Revision: https://reviews.llvm.org/D38165
llvm-svn: 314096
Rui Ueyama [Mon, 25 Sep 2017 05:30:39 +0000 (05:30 +0000)]
Do not sort CU vectors.
We used to sort and uniquify CU vectors, but looks like CU vectors in
.gdb_index sections created by gold are not guaranteed to be sorted.
llvm-svn: 314095
Rui Ueyama [Mon, 25 Sep 2017 04:55:27 +0000 (04:55 +0000)]
Speeds up CU vector creation.
We used to use std::set to uniquify CU vector elements, but as we know,
std::set is pretty slow. Fortunately we didn't actually have to use a
std::set here. This patch replaces it with std::vector.
With this patch, lld's -gdb-index overhead when linking a clang debug
build is now about 1 second (8.65 seconds without -gdb-index vs 9.60
seconds with -gdb-index). Since gold takes more than 6 seconds to create
a .gdb_index for the same output, our number isn't that bad.
llvm-svn: 314094
Rui Ueyama [Mon, 25 Sep 2017 03:40:45 +0000 (03:40 +0000)]
Fix off-by-one error.
llvm-svn: 314093
Rui Ueyama [Mon, 25 Sep 2017 02:29:51 +0000 (02:29 +0000)]
Do not use StringTableBuilder to build symbol table for .gdb_index.
Previously, we had two levels of hash table lookup. The first hash
lookup uses CachedHashStringRefs as keys and returns offsets in string
table. Then, we did the second hash table lookup to obtain GdbSymbol
pointers. But we can directly map strings to GDbSymbols.
One test file is updated in this patch because we no longer have a '\0'
byte at the start of the string pool, which was automatically inserted
by StringTableBuilder.
This patch speeds up Clang debug build (with -gdb-index) link time by
0.3 seconds.
llvm-svn: 314092
Rui Ueyama [Mon, 25 Sep 2017 01:42:57 +0000 (01:42 +0000)]
Compute string hashes early and cache them.
This change alone speeds up linking of Clang debug build with -gdb-index
by 1.2 seconds, from 12.5 seconds to 11.3 seconds. (Without -gdb-index,
lld takes 8.5 seconds to link the same input files.)
llvm-svn: 314090
Rui Ueyama [Mon, 25 Sep 2017 00:57:30 +0000 (00:57 +0000)]
Rename copy -> copyFrom.
This patch is to improve code readability.
llvm-svn: 314089
Rui Ueyama [Mon, 25 Sep 2017 00:57:18 +0000 (00:57 +0000)]
Move Config->SymbolRenaming to SymbolTable.
In order to keep track of symbol renaming, we used to have
Config->SymbolRenaming, and whether a symbol is in the map or not
affects its symbol attribute (i.e. "LinkeRedefined" bit).
This patch adds "CanInline" bit to Symbol to aggreagate symbol
information in one place and removed the member from Config since
no one except SymbolTable now uses the table.
llvm-svn: 314088
Rui Ueyama [Sun, 24 Sep 2017 23:12:36 +0000 (23:12 +0000)]
Remove unused member variable.
llvm-svn: 314087
Rui Ueyama [Sun, 24 Sep 2017 21:45:35 +0000 (21:45 +0000)]
Refactor GdbIndexSection. NFC.
This patch rewrites a part of GdbIndexSection to address the following
issues in the previous implementation:
- Previously, some struct declarations were in GdbIndex.h while they
were not used in GdbIndex.cpp. Such structs are moved to
SyntheticSection.h.
- The actual implementation were split into GdbIndexSection and GdbHash
section, but that separation didn't make much sense. They are now
unified as GdbIndexSection.
In addition to the above changes, this patch splits functions, rename
variables and remove redundant functions/variables to generally improve
code quality.
llvm-svn: 314084
Craig Topper [Sun, 24 Sep 2017 19:30:55 +0000 (19:30 +0000)]
[X86] Make IFMA instructions during isel so we can fold broadcast loads.
This required changing the ISD opcode for these instructions to have the commutable operands first and the addend last. This way tablegen can autogenerate the additional patterns for us.
llvm-svn: 314083
Craig Topper [Sun, 24 Sep 2017 19:30:54 +0000 (19:30 +0000)]
[X86] Add tests to show missed opportunities to fold broadcast loads into IFMA instructions when the load is on operand1 of the instrinsic.
We need to enable commuting during isel to catch this since the load folding tables can't handle broadcasts.
llvm-svn: 314082
Roman Gareev [Sun, 24 Sep 2017 19:00:25 +0000 (19:00 +0000)]
[Polly] Information about generalized matrix multiplication
Reviewed-by: Tobias Grosser <tobias@grosser.es>
Differential Revision: https://reviews.llvm.org/D38218
llvm-svn: 314081
Craig Topper [Sun, 24 Sep 2017 17:28:14 +0000 (17:28 +0000)]
[X86] Add IFMA instructions to the load folding tables and make them commutable for the multiply operands.
llvm-svn: 314080
Simon Pilgrim [Sun, 24 Sep 2017 15:17:46 +0000 (15:17 +0000)]
Fix implicit-fallthrough warning by adding missing break
llvm-svn: 314079
Simon Pilgrim [Sun, 24 Sep 2017 14:00:52 +0000 (14:00 +0000)]
Fix signed/unsigned warning
llvm-svn: 314078
Simon Pilgrim [Sun, 24 Sep 2017 13:45:49 +0000 (13:45 +0000)]
[X86][SSE] Add more tests for shuffle combining with extracted vector elements (PR22415)
llvm-svn: 314077
Simon Pilgrim [Sun, 24 Sep 2017 13:42:31 +0000 (13:42 +0000)]
[X86][SSE] Add support for extending bool vectors bitcasted from scalars
This patch acts as a reverse to combineBitcastvxi1 - bitcasting a scalar integer to a boolean vector and extending it 'in place' to the requested legal type.
Currently this doesn't handle AVX512 at all - but the current mask register approach is lacking for some cases.
Differential Revision: https://reviews.llvm.org/D35320
llvm-svn: 314076
Tobias Grosser [Sun, 24 Sep 2017 09:25:30 +0000 (09:25 +0000)]
[ScopDetect/Info] Look through PHIs that follow an error block
In case a PHI node follows an error block we can assume that the incoming value
can only come from the node that is not an error block. As a result, conditions
that seemed non-affine before are now in fact affine.
This is a recommit of r312663 after fixing
test/Isl/CodeGen/phi_after_error_block_outside_of_scop.ll
llvm-svn: 314075
Nemanja Ivanovic [Sun, 24 Sep 2017 05:48:11 +0000 (05:48 +0000)]
[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.
llvm-svn: 314073
Craig Topper [Sun, 24 Sep 2017 05:24:52 +0000 (05:24 +0000)]
[AVX-512] Add pattern for selecting masked version of v8i32/v8f32 compare instructions when VLX isn't available.
We use a v16i32/v16f32 compare instead and truncate the result. We already did this for the unmasked version, but were missing the version with 'and'.
llvm-svn: 314072
Craig Topper [Sun, 24 Sep 2017 05:24:51 +0000 (05:24 +0000)]
[X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.
Not sure if anything really cares, but this seems like the right thing to do.
llvm-svn: 314071
Dylan McKay [Sun, 24 Sep 2017 01:07:26 +0000 (01:07 +0000)]
[AVR] Implement getCmpLibcallReturnType().
This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code.
By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit.
Patch By Thomas Backman.
llvm-svn: 314070
Davide Italiano [Sun, 24 Sep 2017 01:06:35 +0000 (01:06 +0000)]
[Verifier] Stop accepting broken DIGlobalVariable(s).
The code wasn't yelling at the user when there's a reference
from a DIGlobalVariableExpression. Thanks to Adrian for the
reduced testcase. Fixes PR34672.
llvm-svn: 314069
Simon Pilgrim [Sat, 23 Sep 2017 19:18:29 +0000 (19:18 +0000)]
[X86] Regenerate i64 to v2f32 bitcast test
llvm-svn: 314068
Richard Smith [Sat, 23 Sep 2017 18:27:11 +0000 (18:27 +0000)]
Don't warn about runtime behavior problems in variable initializers that we
know are going to be constant-evaluated.
Any relevant diagnostics should be produced by constant expression evaluation.
llvm-svn: 314067
Benjamin Kramer [Sat, 23 Sep 2017 16:08:48 +0000 (16:08 +0000)]
Silence unused variable warning in Release builds.
llvm-svn: 314066
Tobias Grosser [Sat, 23 Sep 2017 15:32:07 +0000 (15:32 +0000)]
[IslExprBuilder] Do not generate RTC with more than 64 bit
Such RTCs may introduce integer wrapping intrinsics with more than 64 bit,
which are translated to library calls on AOSP that are not part of the
runtime and will consequently cause linker errors.
Thanks to Eli Friedman for reporting this issue and reducing the test case.
llvm-svn: 314065
Sanjay Patel [Sat, 23 Sep 2017 14:32:07 +0000 (14:32 +0000)]
[x86] reduce 64-bit mask constant to 32-bits by right shifting
This is a follow-up from D38181 (r314023). We have to put 64-bit
constants into a register using a separate instruction, so we
should try harder to avoid that.
From what I see, we're not likely to encounter this pattern in the
DAG because the upstream setcc combines from this don't (usually?)
produce this pattern. If we fix that, then this will become more
relevant. Since the cost of handling this case is just loosening
the predicate of the existing fold, we might as well do it now.
llvm-svn: 314064
Sanjay Patel [Sat, 23 Sep 2017 14:24:07 +0000 (14:24 +0000)]
[x86] add an add+shift test for follow-up suggestion from D38181; NFC
llvm-svn: 314063
Nemanja Ivanovic [Sat, 23 Sep 2017 12:53:03 +0000 (12:53 +0000)]
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.
llvm-svn: 314062
Reka Kovacs [Sat, 23 Sep 2017 12:13:32 +0000 (12:13 +0000)]
[docs] Fix typos in Clang's User's Manual.
llvm-svn: 314061
Nemanja Ivanovic [Sat, 23 Sep 2017 09:50:12 +0000 (09:50 +0000)]
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.
llvm-svn: 314060
Craig Topper [Sat, 23 Sep 2017 05:34:07 +0000 (05:34 +0000)]
[X86] Move the getInsertVINSERTImmediate and getExtractVEXTRACTImmediate helper functions over to X86ISelDAGToDAG.cpp
Redefine them to call getI8Imm and return that directly.
llvm-svn: 314059
Craig Topper [Sat, 23 Sep 2017 05:34:06 +0000 (05:34 +0000)]
[X86] Remove is the isVINSERT*Index/isVEXTRACT*Index predicates from isel.
The only insert_subvector/extract_subvector nodes that make it to isel are guaranteed to match.
llvm-svn: 314058