Chris Dewhurst [Tue, 6 Sep 2016 14:41:09 +0000 (14:41 +0000)]
[Sparc][Leon] Corrected supported atomics size for processors supporting Leon CASA instruction back to 32 bits.
This was erroneously checked-in for 64 bits while trying to find if there was a way to get 64 bit atomicity in Leon processors. There is not and this change should not have been checked-in. There is no unit test for this as the existing unit tests test for behaviour to 32 bits, which was the original intention of the code.
llvm-svn: 280710
Rafael Espindola [Tue, 6 Sep 2016 13:57:15 +0000 (13:57 +0000)]
Mark R_GOTREL_FROM_END as a relative expression.
Fixes pr30282.
llvm-svn: 280709
George Rimar [Tue, 6 Sep 2016 13:51:57 +0000 (13:51 +0000)]
[ELF] - Linkerscript: implemented FILL command as alias for =fillexpr
Patch implements FILL just as alias for =fillexpr.
This allows to make implementation much shorted and simpler than D24186.
Differential revision: https://reviews.llvm.org/D24227
llvm-svn: 280708
Dimitar Vlahovski [Tue, 6 Sep 2016 12:48:10 +0000 (12:48 +0000)]
Fixing an MSVC error from rL280692
MSVC emits an error when one uses a const variable in a lambda without
capturing it.
gcc and clang don't emit an error in this scenario.
llvm-svn: 280707
Simon Dardis [Tue, 6 Sep 2016 12:36:24 +0000 (12:36 +0000)]
[mips] Tighten FastISel restrictions
LLVM PR/29052 highlighted that FastISel for MIPS attempted to lower
arguments assuming that it was using the paired 32bit registers to
perform operations for f64. This mode of operation is not supported
for MIPSR6.
This patch resolves the reported issue by adding additional checks
for unsupported floating point unit configuration.
Thanks to mike.k for reporting this issue!
Reviewers: seanbruno, vkalintiris
Differential Review: https://reviews.llvm.org/D23795
llvm-svn: 280706
Krzysztof Parzyszek [Tue, 6 Sep 2016 12:30:00 +0000 (12:30 +0000)]
[PPC] Claim stack frame before storing into it, if no red zone is present
Unlike PPC64, PPC32/SVRV4 does not have red zone. In the absence of it
there is no guarantee that this part of the stack will not be modified
by any interrupt. To avoid this, make sure to claim the stack frame first
before storing into it.
This fixes https://llvm.org/bugs/show_bug.cgi?id=26519.
Differential Revision: https://reviews.llvm.org/D24093
llvm-svn: 280705
Pavel Labath [Tue, 6 Sep 2016 11:08:02 +0000 (11:08 +0000)]
Second round of fixups for r280692
Android targets don't have std::to_string and std::stoul. Use llvm::to_string and strtoul
instead.
llvm-svn: 280704
Dimitar Vlahovski [Tue, 6 Sep 2016 11:00:37 +0000 (11:00 +0000)]
Revert "Intel(R) Memory Protection Extensions (Intel(R) MPX) support."
This reverts commit rL280668 because the register tests fail on i386
Linux.
I investigated a little bit what causes the failure - there are missing
registers when running 'register read -a'.
This is the output I got at the bottom:
"""
...
Memory Protection Extensions:
bnd0 = {0x0000000000000000 0x0000000000000000}
bnd1 = {0x0000000000000000 0x0000000000000000}
bnd2 = {0x0000000000000000 0x0000000000000000}
bnd3 = {0x0000000000000000 0x0000000000000000}
unknown:
2 registers were unavailable.
"""
Also looking at the packets exchanged between the client and server:
"""
...
history[308] tid=0x7338 < 19> send packet: $qRegisterInfo4a#d7
history[309] tid=0x7338 < 130> read packet:
$name:bnd0;bitsize:128;offset:1032;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:101;dwarf:101;#48
history[310] tid=0x7338 < 19> send packet: $qRegisterInfo4b#d8
history[311] tid=0x7338 < 130> read packet:
$name:bnd1;bitsize:128;offset:1048;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:102;dwarf:102;#52
history[312] tid=0x7338 < 19> send packet: $qRegisterInfo4c#d9
history[313] tid=0x7338 < 130> read packet:
$name:bnd2;bitsize:128;offset:1064;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:103;dwarf:103;#53
history[314] tid=0x7338 < 19> send packet: $qRegisterInfo4d#da
history[315] tid=0x7338 < 130> read packet:
$name:bnd3;bitsize:128;offset:1080;encoding:vector;format:vector-uint64;set:Memory
Protection Extensions;ehframe:104;dwarf:104;#54
history[316] tid=0x7338 < 19> send packet: $qRegisterInfo4e#db
history[317] tid=0x7338 < 76> read packet:
$name:bndcfgu;bitsize:64;offset:1096;encoding:vector;format:vector-uint8;#99
history[318] tid=0x7338 < 19> send packet: $qRegisterInfo4f#dc
history[319] tid=0x7338 < 78> read packet:
$name:bndstatus;bitsize:64;offset:1104;encoding:vector;format:vector-uint8;#8e
...
"""
The bndcfgu and bndstatus registers don't have the 'Memory Protections
Extension' set. I looked at the code and it seems that that is set
correctly.
So I'm not sure what's the problem or where does it come from.
Also there is a second failure related to something like this in the
tests:
"""
registerSet.GetName().lower()
"""
For some reason the registerSet.GetName() returns None.
llvm-svn: 280703
Pierre Gousseau [Tue, 6 Sep 2016 10:48:27 +0000 (10:48 +0000)]
[clang-cl] Check that we are in clang cl mode before enabling support for the CL environment variable.
Checking for the type of the command line tokenizer should not be the criteria to enable support for the CL environment variable, this change checks that we are in clang-cl mode instead.
Differential Revision: https://reviews.llvm.org/D23503
llvm-svn: 280702
Leny Kholodov [Tue, 6 Sep 2016 10:48:04 +0000 (10:48 +0000)]
DebugInfo: use llvm::DINode::DIFlags type for debug info flags
Use llvm::DINode::DIFlags type (strongly typed enum) for debug flags instead of unsigned int to avoid problems on platforms with sizeof(int) < 4: we already have flags with values > (1 << 16).
Patch by: Victor Leschuk <vleschuk@gmail.com>
Differential Revision: https://reviews.llvm.org/D23767
llvm-svn: 280701
Leny Kholodov [Tue, 6 Sep 2016 10:46:28 +0000 (10:46 +0000)]
DebugInfo: use strongly typed enum for debug info flags
Use ADT/BitmaskEnum for DINode::DIFlags for the following purposes:
Get rid of unsigned int for flags to avoid problems on platforms with sizeof(int) < 4
Flags are now strongly typed
Patch by: Victor Leschuk <vleschuk@gmail.com>
Differential Revision: https://reviews.llvm.org/D23766
llvm-svn: 280700
Alexey Bader [Tue, 6 Sep 2016 10:10:28 +0000 (10:10 +0000)]
[OpenCL] Remove access qualifiers on images in arg info metadata.
Summary:
Remove access qualifiers on images in arg info metadata:
* kernel_arg_type
* kernel_arg_base_type
Image access qualifiers are inseparable from type in clang implementation,
but OpenCL spec provides a special query to get access qualifier
via clGetKernelArgInfo with CL_KERNEL_ARG_ACCESS_QUALIFIER.
Besides that OpenCL conformance test_api get_kernel_arg_info expects
image types without access qualifier.
Patch by Evgeniy Tyurin.
Reviewers: bader, yaxunl, Anastasia
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D23915
llvm-svn: 280699
Silviu Baranga [Tue, 6 Sep 2016 10:10:21 +0000 (10:10 +0000)]
[RegisterScavenger] Remove aliasing registers of operands from the candidate set
Summary:
In addition to not including the register operand of the current
instruction also don't include any aliasing registers. We can't consider
these as candidates because using them will clobber the corresponding
register operand of the current instruction.
This change doesn't include a test case and it would probably be difficult
to produce a stable one since the bug depends on the results of register
allocation.
Reviewers: MatzeB, qcolombet, hfinkel
Subscribers: hfinkel, llvm-commits
Differential Revision: https://reviews.llvm.org/D24130
llvm-svn: 280698
Pavel Labath [Tue, 6 Sep 2016 10:04:22 +0000 (10:04 +0000)]
Fix build breakage in r280692
The commit introduced an array of const objects, which libstdc++ does not like. Make the object
non-const.
Also fix a compiler warning while I'm in there.
llvm-svn: 280697
Craig Topper [Tue, 6 Sep 2016 06:56:59 +0000 (06:56 +0000)]
[AVX-512] Fix masked VPERMI2PS isel when the index comes from a bitcast.
We need to bitcast the index operand to a floating point type so that it matches the result type. If not then the passthru part of the DAG will be a bitcast from the index's original type to the destination type. This makes it very difficult to match. The other option would be to add 5 sets of patterns for every other possible type.
llvm-svn: 280696
Craig Topper [Tue, 6 Sep 2016 05:45:27 +0000 (05:45 +0000)]
[AVX-512] Add a test case to show that we don't select masked vpermi2ps when the index operand comes from a bitcast.
It doesn't work because we're looking for a bitcast from the v4i32 index operand to v4f32 for the passthru part of the DAG. But since the index is bitcasted from v2i64 and bitcasts fold, we actually have a bitcast from v2i64 to v4f32 in the passthru part of the DAG.
Taken from optimized output from clang's test case.
llvm-svn: 280695
Craig Topper [Tue, 6 Sep 2016 05:45:24 +0000 (05:45 +0000)]
[X86] Remove unused encoding from IntrinsicType enum.
llvm-svn: 280694
Craig Topper [Tue, 6 Sep 2016 05:45:21 +0000 (05:45 +0000)]
[X86] Fix indentation. NFC
llvm-svn: 280693
Sean Callanan [Tue, 6 Sep 2016 04:48:36 +0000 (04:48 +0000)]
Added the "frame diagnose" command and use its output to make crash info better.
When a process stops due to a crash, we get the crashing instruction and the
crashing memory location (if there is one). From the user's perspective it is
often unclear what the reason for the crash is in a symbolic sense.
To address this, I have added new fuctionality to StackFrame to parse the
disassembly and reconstruct the sequence of dereferneces and offsets that were
applied to a known variable (or fuction retrn value) to obtain the invalid
pointer.
This makes use of enhancements in the disassembler, as well as new information
provided by the DWARF expression infrastructure, and is exposed through a
"frame diagnose" command. It is also used to provide symbolic information, when
available, in the event of a crash.
The algorithm is very rudimentary, and it needs a bunch of work, including
- better parsing for assembly, preferably with help from LLVM
- support for non-Apple platforms
- cleanup of the algorithm core, preferably to make it all work in terms of
Operands instead of register/offset pairs
- improvement of the GetExpressioPath() logic to make prettier expression
paths, and
- better handling of vtables.
I welcome all suggestios, improvements, and testcases.
llvm-svn: 280692
Justin Bogner [Tue, 6 Sep 2016 04:45:37 +0000 (04:45 +0000)]
Revert "bugpoint: Stop threading errors through APIs that never fail"
This isn't the right thing to do - it turns out a number of the APIs
that "never fail" just exit(1) if something bad happens. We can and
should thread Error through this instead.
That diff will make more sense with this reverted. Sorry for the
noise.
This reverts r280690
llvm-svn: 280691
Justin Bogner [Tue, 6 Sep 2016 04:04:13 +0000 (04:04 +0000)]
bugpoint: Stop threading errors through APIs that never fail
This simplifies ListReducer and most of its subclasses by removing the
std::string &Error that was threaded through all of them but almost
never used. If we end up needing error handling in more places here we
can reinstate it using llvm::Error instead of these unwieldy strings.
The 2 cases (out of 12) that actually can hit the error cases are a
little bit awkward now, but those will clean up as I refactor this API
further.
llvm-svn: 280690
Saleem Abdulrasool [Tue, 6 Sep 2016 04:00:12 +0000 (04:00 +0000)]
ARM: workaround bundled operation predication
This is a Windows ARM specific issue. If the code path in the if conversion
ends up using a relocation which will form a IMAGE_REL_ARM_MOV32T, we end up
with a bundle to ensure that the mov.w/mov.t pair is not split up. This is
normally fine, however, if the branch is also predicated, then we end up trying
to predicate the bundle.
For now, report a bundle as being unpredicatable. Although this is false, this
would trigger a failure case previously anyways, so this is no worse. That is,
there should not be any code which would previously have been if converted and
predicated which would not be now.
Under certain circumstances, it may be possible to "predicate the bundle". This
would require scanning all bundle instructions, and ensure that the bundle
contains only predicatable instructions, and converting the bundle into an IT
block sequence. If the bundle is larger than the maximal IT block length (4
instructions), it would require materializing multiple IT blocks from the single
bundle.
llvm-svn: 280689
Mehdi Amini [Tue, 6 Sep 2016 03:26:37 +0000 (03:26 +0000)]
Revert "DebugInfo: use strongly typed enum for debug info flags"
This reverts commit r280686, bots are broken.
llvm-svn: 280688
Mehdi Amini [Tue, 6 Sep 2016 03:23:45 +0000 (03:23 +0000)]
[LTO] Constify (NFC)
llvm-svn: 280687
Mehdi Amini [Tue, 6 Sep 2016 03:14:06 +0000 (03:14 +0000)]
DebugInfo: use strongly typed enum for debug info flags
Use ADT/BitmaskEnum for DINode::DIFlags for the following purposes:
* Get rid of unsigned int for flags to avoid problems on platforms with sizeof(int) < 4
* Flags are now strongly typed
Patch by: Victor Leschuk <vleschuk@gmail.com>
Differential Revision: https://reviews.llvm.org/D23766
llvm-svn: 280686
Mehdi Amini [Tue, 6 Sep 2016 03:03:15 +0000 (03:03 +0000)]
Fix DensetSet::insert_as() for MSVC2015 (NFC)
The latest MSVC update apparently resolve the call from the
const ref variant to itself, leading to an infinite
recursion. It is not clear to me why the r-value overload is
not selected. `ValueT` is a pointer type, and the functional-style
cast in the call `insert_as(ValueT(V), LookupKey);` should result
in a r-value ref. A bug in MSVC?
Differential Revision: https://reviews.llvm.org/D23956
llvm-svn: 280685
Craig Topper [Tue, 6 Sep 2016 00:31:10 +0000 (00:31 +0000)]
[AVX-512] Fix v8i64 shift by immediate lowering on 32-bit targets.
llvm-svn: 280684
Saleem Abdulrasool [Tue, 6 Sep 2016 00:28:43 +0000 (00:28 +0000)]
CodeGen: ensure that libcalls are always AAPCS CC
All of the builtins are designed to be invoked with ARM AAPCS CC even on ARM
AAPCS VFP CC hosts. Tweak the default initialisation to ARM AAPCS CC rather
than C CC for ARM/thumb targets.
The changes to the tests are necessary to ensure that the calling convention for
the lowered library calls are honoured. Furthermore, these adjustments cause
certain branch invocations to change to branch-and-link since the returned value
needs to be moved across registers (d0 -> r0, r1).
llvm-svn: 280683
Craig Topper [Mon, 5 Sep 2016 23:58:40 +0000 (23:58 +0000)]
[AVX-512] Teach fastisel load/store handling to use EVEX encoded instructions for 128/256-bit vectors and scalar single/double.
Still need to fix the register classes to allow the extended range of registers.
llvm-svn: 280682
Craig Topper [Mon, 5 Sep 2016 23:58:37 +0000 (23:58 +0000)]
[X86] Update fast-isel store test to have more 256 and 512-bit test cases. Add command lines for AVX and AVX512 feature sets.
llvm-svn: 280681
Craig Topper [Mon, 5 Sep 2016 23:58:32 +0000 (23:58 +0000)]
[X86] Update fast-isel vector load test to have more 256 and 512-bit test cases. Add a command line for SKX features too.
llvm-svn: 280680
Sanjay Patel [Mon, 5 Sep 2016 23:49:32 +0000 (23:49 +0000)]
fix FileCheck variables for test added with r280677
The script (utils/update_test_checks.py) seems to have problems
with variable names that start with the same string.
llvm-svn: 280679
Gor Nishanov [Mon, 5 Sep 2016 23:45:45 +0000 (23:45 +0000)]
[Coroutines] Part12: Handle alloca address-taken
Summary:
Move early uses of spilled variables after CoroBegin.
For example, if a parameter had address taken, we may end up with the code
like:
define @f(i32 %n) {
%n.addr = alloca i32
store %n, %n.addr
...
call @coro.begin
This patch fixes the problem by moving uses of spilled variables after CoroBegin.
Reviewers: majnemer
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D24234
llvm-svn: 280678
Sanjay Patel [Mon, 5 Sep 2016 23:38:22 +0000 (23:38 +0000)]
[InstCombine] don't assert that division-by-constant has been folded (PR30281)
This is effectively a revert of:
https://reviews.llvm.org/rL280115
And this should fix
https://llvm.org/bugs/show_bug.cgi?id=30281:
llvm-svn: 280677
Sanjay Patel [Mon, 5 Sep 2016 22:36:32 +0000 (22:36 +0000)]
[InstCombine] revert r280637 because it causes test failures on an ARM bot
http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/14952/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Aicmp.ll
llvm-svn: 280676
Todd Fiala [Mon, 5 Sep 2016 22:03:02 +0000 (22:03 +0000)]
remove dependence of TestGdbRemoteExitCode.py on parent directory source
As Pavel pointed out in a comment on llvm.org/pr30271, the VPATH I was
using here to eliminate duplication of a .cpp file had a side effect of
attempting to pull in a .o/.obj file from that same parent dir, where
other tests can be running in parallel. This is no good.
For now, I have removed the VPATH, which should address
llvm.org/pr30271. I have also removed the XFAIL.
llvm-svn: 280675
Ahmed Bougacha [Mon, 5 Sep 2016 20:53:14 +0000 (20:53 +0000)]
[lit] Downgrade error to warning on gtest crashes during discovery.
Lots of unittests started failing under asan after r280455. It seems
they've been failing for a long time, but lit silently ignored them.
Downgrade the error so we can figure out what is going on.
Filed http://llvm.org/PR30285.
llvm-svn: 280674
Craig Topper [Mon, 5 Sep 2016 20:34:50 +0000 (20:34 +0000)]
[AVX-512] Integrate mask register copying more completely into X86InstrInfo::copyPhysReg and simplify. No functional change intended.
The code is now written in terms of source and dest classes with feature checks inside each type of copy instead of having separate functions for each feature set.
llvm-svn: 280673
Ed Schouten [Mon, 5 Sep 2016 18:38:34 +0000 (18:38 +0000)]
Add support for targeting armv6-unknown-cloudabi-eabihf.
I'm in the progress of adding ARMv6 support to CloudABI. On the compiler
side, everything seems to work properly with this tiny change applied.
llvm-svn: 280672
Simon Pilgrim [Mon, 5 Sep 2016 18:11:17 +0000 (18:11 +0000)]
[X86][SSE] Add test cases for PR29078
'Failure to recognise i64 sitofp/uitofp conversions that can be performed as i32'
llvm-svn: 280671
Simon Pilgrim [Mon, 5 Sep 2016 18:04:38 +0000 (18:04 +0000)]
[X86][SSE] Add test cases for PR29079
'Failure to recognise uitofp conversions that can be performed as sitofp'
llvm-svn: 280670
Dimitry Andric [Mon, 5 Sep 2016 18:01:13 +0000 (18:01 +0000)]
Add missing _US_ACTION_MASK constant to unwind.h
Summary:
During building of recent compiler-rt sources on FreeBSD for arm, I
noticed that our unwind.h (which originates in libunwind) was missing
the `_US_ACTION_MASK` constant:
compiler-rt/lib/builtins/gcc_personality_v0.c:187:18: error: use of undeclared identifier '_US_ACTION_MASK'
if ((state & _US_ACTION_MASK) != _US_UNWIND_FRAME_STARTING)
^
It appears that both clang's internal unwind.h, and libgcc's unwind.h
define this constant as 3, so let's add this to libunwind's version too.
Reviewers: logan, kledzik, davide, emaste
Subscribers: joerg, davide, aemerson, emaste, llvm-commits
Differential Revision: https://reviews.llvm.org/D24222
llvm-svn: 280669
Valentina Giusti [Mon, 5 Sep 2016 17:43:10 +0000 (17:43 +0000)]
Intel(R) Memory Protection Extensions (Intel(R) MPX) support.
Summary:
The Intel(R) Memory Protection Extensions (Intel(R) MPX) associates pointers
to bounds, against which the software can check memory references to
prevent out of bound memory access.
This patch allows accessing the MPX registers:
* bnd0-3: 128-bit registers to hold the bound values,
* bndcfgu, bndstatus: 64-bit configuration registers,
This patch also adds read/write tests for the MPX registers in the register
command tests and adds a new subdirectory for MPX specific tests.
Signed-off-by: Valentina Giusti <valentina.giusti@intel.com>
Reviewers: labath, granata.enrico, lldb-commits, clayborg
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D24187
llvm-svn: 280668
whitequark [Mon, 5 Sep 2016 17:42:46 +0000 (17:42 +0000)]
CODE_OWNERS: bring my entry up to date
llvm-svn: 280667
Simon Atanasyan [Mon, 5 Sep 2016 15:42:43 +0000 (15:42 +0000)]
[ELF][MIPS] Support R_MIPS_TLS_DTPREL64 / R_MIPS_TLS_TPREL64 relocations calculation
llvm-svn: 280666
Simon Atanasyan [Mon, 5 Sep 2016 15:42:39 +0000 (15:42 +0000)]
[ELF][MIPS] Support R_MIPS_TLS_DTPREL32 / R_MIPS_TLS_TPREL32 relocations calculation
llvm-svn: 280665
Simon Atanasyan [Mon, 5 Sep 2016 15:42:29 +0000 (15:42 +0000)]
[ELF][MIPS] Do not create a hidden definition for __tls_get_addr on MIPS
On most architectures the linker is required to optimize away any
references to __tls_get_addr in case of static linking. As usual
a special case is MIPS - libc defines __tls_get_addr itself because
there are no TLS optimizations for this architecture.
llvm-svn: 280664
Pavel Labath [Mon, 5 Sep 2016 15:15:12 +0000 (15:15 +0000)]
Replace uses of MIUtilParse::CRegexParser with llvm::Regex
Summary:
Replace uses of the local MIUtilParse::CRegexParser class with the LLVM support class llvm::Regex. This reduces duplication of code, and makes it possible to remove the MIUtilParse::CRegexParser class that requires LLVM internal implementation headers.
Bug: https://llvm.org/bugs/show_bug.cgi?id=29138
Reviewers: dawn, abidh, ki.stfu
Subscribers: labath, ki.stfu, lldb-commits
Differential Revision: https://reviews.llvm.org/D23882
Author: Michał Górny <mgorny@gentoo.org>
llvm-svn: 280662
Simon Pilgrim [Mon, 5 Sep 2016 14:15:38 +0000 (14:15 +0000)]
[X86][SSE] Regenerate odd shuffle tests with common prefixes
llvm-svn: 280661
Oliver Stannard [Mon, 5 Sep 2016 13:49:26 +0000 (13:49 +0000)]
[SimplifyCFG] Add test for sinking inline asm in if/else
This test code previously caused a failure in the module verifier,
because SimplifyCFG created this invalid instruction, which tries to
take the address of inline asm:
%.sink = select i1 %1, i64 ()* asm "mov $0, #1", "=r", i64 ()* asm %"mov $0, #2", "=r"
This has been fixed recently, presumably by James Molloy's patches that
re-wrote and changed parts of SimplifyCFG, so this patch just adds a
regression test for it.
Differential Revision: https://reviews.llvm.org/D24231
llvm-svn: 280660
NAKAMURA Takumi [Mon, 5 Sep 2016 13:14:54 +0000 (13:14 +0000)]
clang/test/Modules/compiler_builtins_x86.c: Fix r280658.
llvm-svn: 280659
James Molloy [Mon, 5 Sep 2016 12:28:49 +0000 (12:28 +0000)]
Attempt to fix buildbots not targetting x86
r280613 introduced failures for all builds that don't target x86 by default. Add an explicit target to avoid a missing feature diagnostic.
llvm-svn: 280658
Dmitry Vyukov [Mon, 5 Sep 2016 12:22:56 +0000 (12:22 +0000)]
asan: allow __asan_{before,after}_dynamic_init without registered globals
When optimizing, GCC optimizes away aggressively unused static globals.
The __asan_before_dynamic_init/__asan_after_dynamic_init calls are placed
in static constructor earlier while the registration of the globals is done
later in the compilation process. If all the globals with
dynamic initialization are optimized away from some particular TU in between
those two, libasan can fail on an assertion that dynamic_init_globals is
empty.
While I'm going to commit a GCC change which will remove the
__asan_before_dynamic_init/__asan_after_dynamic_init in many cases when this
happens (basically if the optimizers can prove there are no memory
references in between the two calls), there are still testcases where such
pair of calls is left, e.g. for
struct S { S () { asm volatile ("" : : : "memory"); } };
static S c;
int
main ()
{
return 0;
}
with -O2 -fsanitize=address and ASAN_OPTIONS=check_initialization_order=true
this still fails the assertion. Trying to avoid this problem on the
compiler side would decrease code quality I'm afraid, whether it is making
sure for -fsanitize=address we keep around at least one dynamically
initialized global if the
__asan_before_dynamic_init/__asan_after_dynamic_init pair has been emitted,
or adding some artificial global which would be used as the condition for
those calls etc.
So, can the assertion be instead just removed, this really shouldn't slow
down the calls measurably (for __asan_before_dynamic_init it is even
cheaper) and the assertion doesn't check something worthwhile anyway (it is
sufficient if there is a single dynamically initialized global in any other
TU to make it happy).
Details in http://gcc.gnu.org/PR77396
Author: Jakub Jelinek
llvm-svn: 280657
Benjamin Kramer [Mon, 5 Sep 2016 12:06:47 +0000 (12:06 +0000)]
[WebAssembly] Unbreak the build.
Not sure why ADL isn't working here.
llvm-svn: 280656
Valery Pykhtin [Mon, 5 Sep 2016 11:22:51 +0000 (11:22 +0000)]
[AMDGPU] Refactor FLAT TD instructions
Differential revision: https://reviews.llvm.org/D24072
llvm-svn: 280655
Michael Kruse [Mon, 5 Sep 2016 10:54:16 +0000 (10:54 +0000)]
Add check-polly-tests build target.
The check-polly-tests target runs regression/unit tests but without checking
formatting. This is useful to not having to reload a file in an open editor
(which eg. clears the undo buffer, moves cursor/window position) when running
polly-update-format.
After this change, the following test targets exist:
- check-polly-unittests to run unittests only
- check-polly-tests to run unit and regression tests
- polly-check-format to check formatting using clang-format
- check-polly to run them all
As a side-effect, when running check-polly, polly-check-format and run in
parallel (instead of polly-check-format first).
Differential Revision: https://reviews.llvm.org/D24191
llvm-svn: 280654
Kirill Bobyrev [Mon, 5 Sep 2016 09:42:02 +0000 (09:42 +0000)]
[clang-rename] Add comment after namespace closing
llvm-svn: 280653
Pavel Labath [Mon, 5 Sep 2016 08:34:56 +0000 (08:34 +0000)]
Add default_packet_timeout key to the new TestGdbRemoteHostInfo test
android targets use this key, so the test should recognize it.
llvm-svn: 280652
James Molloy [Mon, 5 Sep 2016 08:29:15 +0000 (08:29 +0000)]
[Thumb1] Add relocations for fixups fixup_arm_thumb_{br,bcc}
These need to be mapped through to R_ARM_THM_JUMP{11,8} respectively.
Fixes PR30279.
llvm-svn: 280651
Igor Breger [Mon, 5 Sep 2016 08:26:51 +0000 (08:26 +0000)]
[AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Explicitly zero upper bits.
Differential Revision: http://reviews.llvm.org/D23983
llvm-svn: 280650
Craig Topper [Mon, 5 Sep 2016 07:14:21 +0000 (07:14 +0000)]
[X86] Make some static arrays of opcodes const and shrink to uint16_t. NFC
llvm-svn: 280649
Craig Topper [Mon, 5 Sep 2016 06:43:06 +0000 (06:43 +0000)]
[AVX-512] Simplify X86InstrInfo::copyPhysReg for 128/256-bit vectors with AVX512, but not VLX. We should use the VEX opcodes and trust the register allocator to not use the extended XMM/YMM register space.
Previously we were extending to copying the whole ZMM register. The register allocator shouldn't use XMM16-31 or YMM16-31 in this configuration as the instructions to spill them aren't available.
llvm-svn: 280648
Craig Topper [Mon, 5 Sep 2016 06:43:00 +0000 (06:43 +0000)]
[Target] Remove the AvailableRegClasses vector from TargetLoweringBase. It was a private member with no code reading from it.
llvm-svn: 280647
Gor Nishanov [Mon, 5 Sep 2016 04:44:30 +0000 (04:44 +0000)]
[Coroutines] Part11: Add final suspend handling.
Summary:
A frontend may designate a particular suspend to be final, by setting the second argument of the coro.suspend intrinsic to true. Such a suspend point has two properties:
* it is possible to check whether a suspended coroutine is at the final suspend point via coro.done intrinsic;
* a resumption of a coroutine stopped at the final suspend point leads to undefined behavior. The only possible action for a coroutine at a final suspend point is destroying it via coro.destroy intrinsic.
This patch adds final suspend handling logic to CoroEarly and CoroSplit passes.
Now, the final suspend point example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex5.ll).
Reviewers: majnemer
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D24068
llvm-svn: 280646
Craig Topper [Mon, 5 Sep 2016 02:20:53 +0000 (02:20 +0000)]
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test.
llvm-svn: 280645
Craig Topper [Mon, 5 Sep 2016 02:20:49 +0000 (02:20 +0000)]
[X86] Remove FsVMOVAPSrm/FsVMOVAPDrm/FsMOVAPSrm/FsMOVAPDrm. Due to their placement in the td file they had lower precedence than (V)MOVSS/SD and could almost never be selected.
The only way to select them was in AVX512 mode because EVEX VMOVSS/SD was below them and the patterns weren't qualified properly for AVX only. So if you happened to have an aligned FR32/FR64 load in AVX512 you could get a VEX encoded VMOVAPS/VMOVAPD.
I tried to search back through history and it seems like these instructions were probably unselectable for at least 5 years, at least to the time the VEX versions were added. But I can't prove they ever were.
llvm-svn: 280644
Marshall Clow [Mon, 5 Sep 2016 01:54:30 +0000 (01:54 +0000)]
Fix Bug 30240 - std::string: append(first, last) error when aliasing. Add test cases for append/insert/assign/replace while we're at it, and fix a similar bug in insert.
llvm-svn: 280643
Peter Zotov [Mon, 5 Sep 2016 01:42:22 +0000 (01:42 +0000)]
[CMake] [OCaml] Allow building OCaml bindings out of tree.
That is, add build system support for building the OCaml bindings
against preinstalled LLVM libraries. This is important for package
managers such as OPAM, because OCaml libraries need to be built
against a specific OCaml compiler installation.
llvm-svn: 280642
NAKAMURA Takumi [Mon, 5 Sep 2016 00:00:40 +0000 (00:00 +0000)]
lit/util.py: Another fix for py3.
'str' object has no attribute 'decode'.
llvm-svn: 280641
Kirill Bobyrev [Sun, 4 Sep 2016 22:50:41 +0000 (22:50 +0000)]
[clang-rename] Enforce LLVM policy about braces around single line control flow statement body.
Although it is not explicitly stated in LLVM Coding Standards, LLVM developers
prefer to omit braces around flow control statements with single line body.
For example the following piece of code
```
if (condition)
std::cout << "Hello, world!" << std::endl;
```
is preferred to
```
if (condition) {
std::cout << "Hello, world!" << std::endl;
}
```
So far clang-rename has ignored this. This patch makes clang-rename more
"LLVM-ish".
llvm-svn: 280640
Kirill Bobyrev [Sun, 4 Sep 2016 22:28:39 +0000 (22:28 +0000)]
[clang-rename] add failing test
For some reason clang-rename fails to rename method of templated class. Add
XFAIL test reproducing the issue.
llvm-svn: 280639
Kirill Bobyrev [Sun, 4 Sep 2016 22:19:52 +0000 (22:19 +0000)]
[clang-rename] Fix Clang-tidy and IWYU warnings; other minor fixes
Patch by Eugene Zelenko!
Differential Revision: https://reviews.llvm.org/D24178
Reviewers: omtcyfz
llvm-svn: 280638
Sanjay Patel [Sun, 4 Sep 2016 20:58:27 +0000 (20:58 +0000)]
[InstCombine] allow icmp (and X, C2), C1 folds for splat constant vectors
The code to calculate 'UsesRemoved' could be simplified.
As-is, that code is a victim of PR30273:
https://llvm.org/bugs/show_bug.cgi?id=30273
llvm-svn: 280637
Craig Topper [Sun, 4 Sep 2016 19:33:47 +0000 (19:33 +0000)]
[AVX-512] Add EVEX encoded scalar FMA intrinsic instructions to isNonFoldablePartialRegisterLoad.
llvm-svn: 280636
Craig Topper [Sun, 4 Sep 2016 18:30:17 +0000 (18:30 +0000)]
[AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div builtins and replace with native operations.
We can't do the 512-bit ones because they take a rounding mode argument that we can't represent.
llvm-svn: 280635
Simon Pilgrim [Sun, 4 Sep 2016 18:14:45 +0000 (18:14 +0000)]
[X86] Regenerate x64 mmx/f64 return value tests
llvm-svn: 280634
Craig Topper [Sun, 4 Sep 2016 18:13:33 +0000 (18:13 +0000)]
[AVX-512] Remove 128-bit and 256-bit masked floating point add/sub/mul/div intrinsics and upgrade to native IR.
llvm-svn: 280633
Lang Hames [Sun, 4 Sep 2016 17:53:30 +0000 (17:53 +0000)]
[ORC] Clone module flags metadata into the globals module in the
CompileOnDemandLayer.
Also contains a tweak to the orc-lazy jit in LLI to enable the test case.
llvm-svn: 280632
Simon Pilgrim [Sun, 4 Sep 2016 17:50:03 +0000 (17:50 +0000)]
[X86] Regenerate trunc-store legalization test
llvm-svn: 280631
Simon Atanasyan [Sun, 4 Sep 2016 17:40:12 +0000 (17:40 +0000)]
[ELF][MIPS] Do not emit DT_REL[A]COUNT for MIPS targets
It looks like MIPS dynamic loader does not support RELCOUNT tag.
Both gold/bfd linkers does not emit this tag on MIPS. I will investigate
the problem further but for now it is better to behave like GNU linkers.
llvm-svn: 280630
Simon Pilgrim [Sun, 4 Sep 2016 17:16:01 +0000 (17:16 +0000)]
[X86][SSE] Regenerate fcmp/uitofp combine tests
llvm-svn: 280629
Lang Hames [Sun, 4 Sep 2016 16:31:41 +0000 (16:31 +0000)]
[ORC] Fix an unfinished comment.
llvm-svn: 280628
Sanjay Patel [Sun, 4 Sep 2016 14:32:15 +0000 (14:32 +0000)]
[InstCombine] recode icmp fold in a vector-friendly way; NFC
The transform in question:
icmp (and (trunc W), C2), C1 -> icmp (and W, C2'), C1'
...is still not enabled for vectors, thus no functional change intended.
It's not clear to me if this is a good transform for vectors or even
scalars in general. Changing that behavior may be a follow-on patch.
llvm-svn: 280627
Hal Finkel [Sun, 4 Sep 2016 14:18:29 +0000 (14:18 +0000)]
[PowerPC] During branch relaxation, recompute padding offsets before each iteration
We used to compute the padding contributions to the block sizes during branch
relaxation only at the start of the transformation. As we perform branch
relaxation, we change the sizes of the blocks, and so the amount of inter-block
padding might change. Accordingly, we need to recompute the (alignment-based)
padding in between every iteration on our way toward the fixed point.
Unfortunately, I don't have a test case (and none was provided in the bug
report), and while this obviously seems needed, algorithmically, I don't have
any way of generating a small and/or non-fragile regression test.
llvm-svn: 280626
Igor Breger [Sun, 4 Sep 2016 14:03:52 +0000 (14:03 +0000)]
revert r279960.
https://llvm.org/bugs/show_bug.cgi?id=30249
llvm-svn: 280625
Simon Pilgrim [Sun, 4 Sep 2016 13:30:46 +0000 (13:30 +0000)]
EOL fixes
llvm-svn: 280624
Simon Pilgrim [Sun, 4 Sep 2016 13:28:46 +0000 (13:28 +0000)]
Strip trailing whitespace
llvm-svn: 280623
Joerg Sonnenberger [Sun, 4 Sep 2016 11:21:27 +0000 (11:21 +0000)]
Test case for r280607 to check presence and sanity of the *_LOCK_FREE
macros.
llvm-svn: 280622
Kuba Brecka [Sun, 4 Sep 2016 09:55:12 +0000 (09:55 +0000)]
[libcxx] Fix a data race in call_once
call_once is using relaxed atomic load to perform double-checked locking, which contains a data race. The fast-path load has to be an acquire atomic load.
Differential Revision: https://reviews.llvm.org/D24028
llvm-svn: 280621
Chandler Carruth [Sun, 4 Sep 2016 08:42:31 +0000 (08:42 +0000)]
[PM] Revert r280447: Add a unittest for invalidating module analyses with an SCC pass.
This was mistakenly committed. The world isn't ready for this test, the
test code has horrible debugging code in it that should never have
landed in tree, it currently passes because of bugs elsewhere, and it
needs to be rewritten to not be susceptible to passing for the wrong
reasons.
I'll re-land this in a better form when the prerequisite patches land.
So sorry that I got this mixed into a series of commits that *were*
ready to land. I shouldn't have. =[ What's worse is that it stuck around
for so long and I discovered it while fixing the underlying bug that
caused it to pass.
llvm-svn: 280620
Chandler Carruth [Sun, 4 Sep 2016 08:34:31 +0000 (08:34 +0000)]
[LCG] Clean up and make NDEBUG verify calls more rigorous with
make_scope_exit now that we have that utility.
This makes the code much more clear and readable by isolating the check.
It also makes it easy to go through and make sure all the interesting
update routines have a start and end verify so we don't slowly let the
graph drift into an invalid state.
llvm-svn: 280619
Chandler Carruth [Sun, 4 Sep 2016 08:34:24 +0000 (08:34 +0000)]
[LCG] A NFC refactoring to extract the logic for doing
a postorder-sequence based update after edge insertion into a generic
helper function.
This separates the SCC-specific logic into two fairly simple lambdas and
extracts the rest into a generic helper template function. I think this
is a net win on its own merits because it disentangles different pieces
of the algorithm. Now there is one place that does the two-step
partition to identify a set of newly connected components and at the
same time update the postorder sequence.
However, I'm also hoping to re-use this an upcoming patch to update
a cached post-order sequence of RefSCCs when doing the analogous update
to the RefSCC graph, and I don't want to have two copies.
The diff is quite messy but this really is just moving things around and
making types generic rather than specific.
llvm-svn: 280618
Dorit Nuzman [Sun, 4 Sep 2016 07:49:39 +0000 (07:49 +0000)]
[InstCombine] Preserve llvm.mem.parallel_loop_access metadata when replacing
memcpy with ld/st.
When InstCombine replaces a memcpy with loads+stores it does not copy over the
llvm.mem.parallel_loop_access from the memcpy instruction. This patch fixes
that.
Differential Revision: https://reviews.llvm.org/D23499
llvm-svn: 280617
Lang Hames [Sun, 4 Sep 2016 07:24:11 +0000 (07:24 +0000)]
[ExecutionEngine] Move ObjectCache::anchor from MCJIT to ExecutionEngine.
ObjectCache is an ExecutionEngine utility, so its anchor belongs there. The
practical impact of this change is that ORC users no longer need to link MCJIT
to use ObjectCaches.
llvm-svn: 280616
Dorit Nuzman [Sun, 4 Sep 2016 07:06:00 +0000 (07:06 +0000)]
Test commit.
llvm-svn: 280615
Hal Finkel [Sun, 4 Sep 2016 06:07:19 +0000 (06:07 +0000)]
[PowerPC] Zero-extend constants in FastISel
As it turns out, whether we zero-extend or sign-extend i8/i16 constants, which
are illegal types promoted to i32 on PowerPC, is a choice constrained by
assumptions within the infrastructure. Specifically, the logic in
FunctionLoweringInfo::ComputePHILiveOutRegInfo assumes that constant PHI
operands will be zero extended, and so, at least when materializing constants
that are PHI operands, we must do the same.
The rest of our fast-isel implementation does not appear to depend on the fact
that we were sign-extending i8/i16 constants, and all other targets also appear
to zero-extend small-bitwidth constants in fast-isel; we'll now do the same (we
had been doing this only for i1 constants, and sign-extending the others).
Fixes PR27721.
llvm-svn: 280614
Elad Cohen [Sun, 4 Sep 2016 06:00:42 +0000 (06:00 +0000)]
[Modules] Add 'freestanding' to the 'requires-declaration' feature-list.
This adds support for modules that require (non-)freestanding
environment, such as the compiler builtin mm_malloc submodule.
Differential Revision: https://reviews.llvm.org/D23871
llvm-svn: 280613
Eric Fiselier [Sun, 4 Sep 2016 04:09:25 +0000 (04:09 +0000)]
Apply curr_symbol.pass.cpp test fix to missed test case
llvm-svn: 280612
Craig Topper [Sun, 4 Sep 2016 02:09:53 +0000 (02:09 +0000)]
[AVX-512] Remove masked integer add/sub/mull intrinsics and upgrade to native IR.
llvm-svn: 280611
Joseph Tremoulet [Sun, 4 Sep 2016 01:23:20 +0000 (01:23 +0000)]
Fix inliner funclet unwind memoization
Summary:
The inliner may need to determine where a given funclet unwinds to,
and this determination may depend on other funclets throughout the
funclet tree. The code that performs this walk in getUnwindDestToken
memoizes results to avoid redundant computations. In the case that
a funclet's unwind destination is derived from its ancestor, there's
code to walk back down the tree from the ancestor updating the memo
map of its descendants to record the unwind destination. This change
fixes that code to account for the case that some descendant has a
different unwind destination, which can happen if that unwind dest
is a descendant of the EHPad being queried and thus didn't determine
its unwind destination.
Also update test inline-funclets.ll, which is supposed to cover such
scenarios, to include a case that fails an assertion without this fix
but passes with it.
Fixes PR29151.
Reviewers: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D24117
llvm-svn: 280610