Simon Pilgrim [Sat, 30 Apr 2022 10:00:28 +0000 (11:00 +0100)]
[X86] lowerShuffleAsRepeatedMaskAndLanePermute - permit 32-bit sublane permute for unary v32i8 cases
Increase the likelihood that we can lower to a permd(pshufb()) pattern, but only after we've attempted with 64-bit sublane permutes first
Fixes #55066
Sam McCall [Sat, 30 Apr 2022 09:02:31 +0000 (11:02 +0200)]
Reland [clangd] More precisely enable clang warnings through ClangTidy options
This reverts commit
26c82f3d1de11cdada57e499b63a05d24e18b656.
When tests enable 'Checks: *', we may get extra diagnostics.
NAKAMURA Takumi [Sat, 30 Apr 2022 08:10:40 +0000 (17:10 +0900)]
ClangDriverTests:ToolChainTest.cpp: Fix warnings. [-Wsign-compare]
EXPECT_EQ(num,num) is aware of signedness, even if rhs is a constant.
Yeting Kuo [Sun, 27 Mar 2022 11:35:10 +0000 (19:35 +0800)]
[RISCV] Add DAGCombine to fold base operation and reduction.
Transform (<bop> x, (reduce.<bop> vec, splat(neutral_element))) to
(reduce.<bop> vec, splat (x)).
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D122563
Amir Ayupov [Sat, 30 Apr 2022 03:37:32 +0000 (20:37 -0700)]
[BOLT][NFC] Reduce Target/{AArch64,X86} dependencies
We don't actually depend on entire X86/AArch64 components that pull in CodeGen,
SelectionDAG etc., just the Desc part with opcode and other definitions.
Note that it doesn't decouple BOLT from these components - we still pull in X86
and AArch64 from top-level llvm-bolt dependencies as we use assembler and
disassembler. It's difficult to reduce these as this requires non-trivial
changes to X86/AArch64 components themselves (e.g. moving out AsmPrinter).
Reviewed By: rafauler
Differential Revision: https://reviews.llvm.org/D124206
Kito Cheng [Sat, 30 Apr 2022 03:09:29 +0000 (11:09 +0800)]
[RISCV] Fix int16 -> __fp16 conversion code gen
clang emit wrong code sequence for `int16`(`short`) to `__fp16` conversion,
and that should fix the code gen directly is the right way I think,
but I found there is a FIXME comment in clang/Basic/TargetInfo.h say
that's should be removed in future so I think just let swich to using
generic LLVM IR rather than llvm.convert.to.fp16 intrinsics code gen
path is enough.
```
/// Check whether llvm intrinsics such as llvm.convert.to.fp16 should be used
/// to convert to and from __fp16.
/// FIXME: This function should be removed once all targets stop using the
/// conversion intrinsics.
virtual bool useFP16ConversionIntrinsics() const {
return true;
}
```
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D124509
Kito Cheng [Sat, 30 Apr 2022 03:08:30 +0000 (11:08 +0800)]
[RISCV] Precommit test for D124509
Test case to show the wrong code gen for `int16` -> `__fp16` conversion,
clang just emit a load and store without did conversion in the case,
and another case used for demonstrate the code gen change of `__fp16`
-> `int16`.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D124510
Joseph Huber [Sat, 30 Apr 2022 03:05:08 +0000 (23:05 -0400)]
[OpenMP] Fix printing commands twice in verbose mode
Summary:
A previous patch merged the command execution and printing into a helper
function. The old printing code wasn't removed causing each to be
printed twice.
Kito Cheng [Thu, 28 Apr 2022 08:38:58 +0000 (16:38 +0800)]
[compiler-rt][profile][RISCV] Enable profile for RISC-V
Profile library are written by standard libraries or POSIX calls depend on target support, so there is no porting effort for the target, we could enable that for both RV32 and RV64, verified on the RV64 platform.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D124599
Craig Topper [Sat, 30 Apr 2022 01:40:44 +0000 (18:40 -0700)]
[RISCV] Copy test from mem.ll to mem64.ll for completeness. NFC
Add nounwind to both copies.
Addresses post-commit feedback from
f91690f7db96aae16425241a17fe6649f5d156b4
Craig Topper [Sat, 30 Apr 2022 01:19:05 +0000 (18:19 -0700)]
[RISCV] Don't merge addi into load/store address if addi has a FrameIndex operand.
This fixes a crash from D124231.
We can't fold
(load (add base, (addi src, off1)), off2)
-> (load (add base, src), off1+off2)
if the src is a FrameIndex. FrameIndex cannot be the operand of an
add.
There was an immediate==0 check that I think was trying to catch
the common case of FrameIndex addis where the immediate is 0, but
they can also appear in non-zero form. Instead explicitly check
for a FrameIndex operand.
LLVM GN Syncbot [Sat, 30 Apr 2022 00:44:51 +0000 (00:44 +0000)]
[gn build] Port
73417c517644
Craig Topper [Sat, 30 Apr 2022 00:30:39 +0000 (17:30 -0700)]
[RISCV] Remove 'frameindex' from list for ComplexPattern. NFC
Putting a node in this list allows the node to be used as the root
of an isel pattern that would then call the ComplexPattern. The
usual case is to use the ComplexPattern as the operand of another
operator.
AddrFI is never used as a root operation. frameindex is handled
directly with custom code in RISCVISelDAGToDAG::Select. So adding
frameindex to the list here serves no purpose.
Nico Weber [Sat, 30 Apr 2022 00:31:57 +0000 (20:31 -0400)]
Revert "[clangd] More precisely enable clang warnings through ClangTidy options"
This reverts commit
5227be8b6aa0edb2edb0b76e1039a7dd5641c80a.
Broke check-clangd, see comment on https://reviews.llvm.org/D124679
Hongtao Yu [Thu, 28 Apr 2022 18:52:38 +0000 (11:52 -0700)]
[CSSPGO] Turn on priority inlining for probe-only profile
We have seen that the prioirty inliner delivered on-par performance with the old inliner for probe-only CSSPGO profile, as long as without a size budget. I'm turning on the priority inliner for probe-only profile by default.
Reviewed By: wenlei
Differential Revision: https://reviews.llvm.org/D124632
Craig Topper [Fri, 29 Apr 2022 20:41:40 +0000 (13:41 -0700)]
[SelectionDAG] Pre-commit test for D124696. NFC
joker881 [Thu, 28 Apr 2022 15:26:19 +0000 (23:26 +0800)]
[RISCV]Add CTZ Intrinsic for ZBB in Clang
Add Intrinsics and test for B extension (updating coming soon (:
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D124348
Hongtao Yu [Thu, 28 Apr 2022 18:31:02 +0000 (11:31 -0700)]
[CSSPGO] Rename ProfileIsCSNested and ProfileIsCSFlat
To be more clear and definitive, I'm renaming `ProfileIsCSFlat` back to `ProfileIsCS` which stands for full context-sensitive flat profiles. `ProfileIsCSNested` is now renamed to `ProfileIsPreInlined` and is extended to be applicable for CS flat profiles too. More specifically, `ProfileIsPreInlined` is for any kind of profiles (flat or nested) that contain 'ShouldBeInlined' contexts. The flag is encoded in the profile summary section for extbinary profiles and is computed on-the-fly for text profiles.
Reviewed By: wenlei
Differential Revision: https://reviews.llvm.org/D122602
python3kgae [Fri, 15 Apr 2022 23:22:54 +0000 (16:22 -0700)]
[HLSL][clang][Driver] Support validator version command line option.
The DXIL validator version option(/validator-version) decide the validator version when compile hlsl.
The format is major.minor like 1.0.
In normal case, the value of validator version should be got from DXIL validator. Before we got DXIL validator ready for llvm/main, DXIL validator version option is added first to set validator version.
It will affect code generation for DXIL, so it is treated as a code gen option.
A new member std::string DxilValidatorVersion is added to clang::CodeGenOptions.
Then CGHLSLRuntime is added to clang::CodeGenModule.
It is used to translate clang::CodeGenOptions::DxilValidatorVersion into a ModuleFlag under key "dx.valver" at end of clang code generation.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D123884
David Kreitzer [Fri, 29 Apr 2022 19:26:13 +0000 (12:26 -0700)]
Test commit. Fixed a typo in a comment.
Siva Chandra Reddy [Fri, 22 Apr 2022 23:32:42 +0000 (23:32 +0000)]
[libc] Add implementations of feof, ferror and clearerr.
The corresponding _unlocked functions have also been added.
Reviewed By: lntue, michaelrj
Differential Revision: https://reviews.llvm.org/D124311
Congzhe Cao [Fri, 29 Apr 2022 22:36:48 +0000 (18:36 -0400)]
[LoopCacheAnalysis] Minor test case update
Changed the test case in https://reviews.llvm.org/D122857
from using `CHECK` to using `CHECK-DAG` to incorporate
nondeterministic output.
Petr Hosek [Wed, 17 Nov 2021 19:06:03 +0000 (11:06 -0800)]
[Driver] Support for compressed debug info on Fuchsia
Pass the --compress-debug-sections=zlib argument to the linker when
the use of compressed debug info is requested.
Differential Revision: https://reviews.llvm.org/D114115
Dmitry Vassiliev [Fri, 29 Apr 2022 22:32:22 +0000 (15:32 -0700)]
[NVPTX] Add add.cc/addc.cc/sub.cc/subc.cc for i64
PTX supports those instructions for i64 starting from 4.3.
The patch also marks corresponding DAG nodes legal for both i32 and i64.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D124698
Simon Dardis [Thu, 28 Apr 2022 23:55:31 +0000 (00:55 +0100)]
[MIPS] Address instruction selection failure for abs.[sd]
Previously, the choice between the instruction selection of ISD::FABS was
decided at the point of setting the MIPS target lowering operation choice
either `Custom` lowering or `Legal`. This lead to instruction selection
failures as functions could be marked as having no NaNs.
Changing the lowering to always be `Custom` and directly handling the
the cases where MIPS selects the instructions for ISD::FABS resolves
this crash.
Thanks to kray for reporting the issue and to Simon Atanasyan for producing
the reduced test case.
This resolves PR/53722.
Differential Revision: https://reviews.llvm.org/D124651
Jason Molenda [Fri, 29 Apr 2022 22:00:20 +0000 (15:00 -0700)]
LocationListLookup test case failing on lldb-arm-ubuntu
Skip on linux+arm for now until I can try to repo the setup of the
lldb-arm-ubuntu bot. The name of the binary in argv[0] was not
able to be retrieved here; if the compiler's codegen had it stored
in a caller saved register, because it's not needed at this point,
it may not be retreivable.
Jason Molenda [Fri, 29 Apr 2022 21:34:06 +0000 (14:34 -0700)]
Decr pc when looking for DWARF loc list entry mid-stack
When looking for a variable location in a DWARF location list,
we search the list of ranges to find one that includes the pc.
With a function mid-stack, the "pc" is the return pc instead of
the call instruction, and in optimized code this can be another
function or a different basic block (with different variable
locations). Back up the "pc" value mid-stack to find the correct
location list entry.
Differential Revision: https://reviews.llvm.org/D124597
rdar://
63903416
James Y Knight [Fri, 29 Apr 2022 20:33:08 +0000 (20:33 +0000)]
Revert "[JumpThreading][NFC][CompileTime] Do not recompute BPI/BFI analyzes"
This change has caused non-reproducibility of a self-build of Clang
when using NewPM and providing profile data.
This reverts commit
35f38583d2f2484794f579bed69566b40e732206.
Aaron Puchert [Fri, 29 Apr 2022 20:28:51 +0000 (22:28 +0200)]
Thread safety analysis: Don't pass capability kind where not needed (NFC)
If no capability is held, or the capability expression is invalid, there
is obviously no capability kind and so none would be reported.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D124132
Aaron Puchert [Fri, 29 Apr 2022 20:12:21 +0000 (22:12 +0200)]
Thread safety analysis: Store capability kind in CapabilityExpr
This should make us print the right capability kind in many more cases,
especially when attributes name multiple capabilities of different kinds.
Previously we were trying to deduce the capability kind from the
original attribute, but most attributes can name multiple capabilities,
which could be of different kinds. So instead we derive the kind when
translating the attribute expression, and then store it in the returned
CapabilityExpr. Then we can extract the corresponding capability name
when we need it, which saves us lots of plumbing and almost guarantees
that the name is right.
I didn't bother adding any tests for this because it's just a usability
improvement and it's pretty much evident from the code that we don't
fall back to "mutex" anymore (save for a few cases that I'll address in
a separate change).
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D124131
Aaron Puchert [Fri, 29 Apr 2022 20:11:20 +0000 (22:11 +0200)]
Thread safety analysis: Store CapabilityExprs in ScopedLockableFactEntry (NFC)
For now this doesn't make a whole lot of sense, but it will allow us to
store the capability kind in a CapabilityExpr and make sure it doesn't
get lost. The capabilities managed by a scoped lockable can of course be
of different kind, so we'll need to store that per entry.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D124128
Aaron Puchert [Fri, 29 Apr 2022 20:10:50 +0000 (22:10 +0200)]
Thread safety analysis: Pack CapabilityExpr using PointerIntPair (NFC)
We're storing these quite frequently: FactEntry inherits from
CapabilityExpr, and the FactManager has a vector of such entries.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D124127
Sam McCall [Fri, 29 Apr 2022 15:47:20 +0000 (17:47 +0200)]
[clangd] More precisely enable clang warnings through ClangTidy options
clang-tidy's behavior is to add the -W flags, and then map all clang diagnostics
to "clang-diagnostic-foo" pseudo-check-names, then use Checks to filter those.
Previous to this patch, we were handling -W flags but not filtering the
diagnostics, assuming both sets of information encoded the same thing.
However this intersection is nontrivial when diagnostic group hierarchy is
involved. e.g. -Wunused + clang-diagnostic-unused-function should not enable
unused label warnings.
This patch more closely emulates clang-tidy's behavior, while not going to
the extreme of generating tidy check names for all clang diagnostics and
filtering them with regexes.
Differential Revision: https://reviews.llvm.org/D124679
Congzhe Cao [Fri, 29 Apr 2022 19:59:48 +0000 (15:59 -0400)]
[LoopCacheAnalysis] Enable delinearization of fixed sized arrays
Currently loop cache cost (LCC) cannot analyze fix-sized arrays
since it cannot delinearize them. This patch adds the capability
to delinearize fix-sized arrays to LCC. Most of the code is ported
from DependenceAnalysis.cpp and some refactoring will be done in a
next patch.
Reviewed By: #loopoptwg, Meinersbur
Differential Revision: https://reviews.llvm.org/D122857
Sanjay Patel [Fri, 29 Apr 2022 18:34:26 +0000 (14:34 -0400)]
[InstCombine] add tests for FP<->int casts; NFC
This overlaps with at least some existing tests,
but the smaller types should be faster for alive2
to verify. We know that at least one of these is
currently wrong (miscompile) as shown in #55150.
Chris Lattner [Fri, 29 Apr 2022 00:26:43 +0000 (17:26 -0700)]
[AsmParser] Introduce a new "Argument" abstraction + supporting logic
MLIR has a common pattern for "arguments" that uses syntax
like `%x : i32 {attrs} loc("sourceloc")` which is implemented
in adhoc ways throughout the codebase. The approach this uses
is verbose (because it is implemented with parallel arrays) and
inconsistent (e.g. lots of things drop source location info).
Solve this by introducing OpAsmParser::Argument and make addRegion
(which sets up BlockArguments for the region) take it. Convert the
world to propagating this down. This means that we correctly
capture and propagate source location information in a lot more
cases (e.g. see the affine.for testcase example), and it also
simplifies much code.
Differential Revision: https://reviews.llvm.org/D124649
Teresa Johnson [Fri, 29 Apr 2022 19:09:26 +0000 (12:09 -0700)]
[memprof] Correct comment in test [NFC]
Correct comment referring incorrectly to address sanitizer (from which
the memprof tests were originally forked).
AlexisPerry [Fri, 29 Apr 2022 17:53:54 +0000 (11:53 -0600)]
[flang] Update Google Doc link for Flang Biweekly Sync call notes
Notes from the Flang Biweekly Sync calls have been merged into the same document as the notes from the Flang Technical calls. This patch updates the link in the GettingInvolved document to point to the new location.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D124689
Martin Storsjö [Wed, 6 Apr 2022 11:10:40 +0000 (14:10 +0300)]
[lldb] Fix initialization of LazyBool/bool variables m_overwrite/m_overwrite_lazy. NFCI.
This silences a GCC warning after
1f7b58f2a50461493f083b2ed807b25e036286f6 / D122680:
lldb/source/Commands/CommandObjectCommands.cpp:1650:22: warning: enum constant in boolean context [-Wint-in-bool-context]
1650 | bool m_overwrite = eLazyBoolCalculate;
| ^~~~~~~~~~~~~~~~~~
Differential Revision: https://reviews.llvm.org/D123204
Greg Clayton [Wed, 27 Apr 2022 21:53:45 +0000 (14:53 -0700)]
Fix the encoding and decoding of UniqueCStringMap<T> objects when saved to cache files.
UniqueCStringMap<T> objects are a std::vector<UniqueCStringMap::Entry> objects where the Entry object contains a ConstString + T. The values in the vector are sorted first by ConstString and then by the T value. ConstString objects are simply uniqued "const char *" values and when we compare we use the actual string pointer as the value we sort by. This caused a problem when we saved the symbol table name indexes and debug info indexes to disk in one process when they were sorted, and then loaded them into another process when decoding them from the cache files. Why? Because the order in which the ConstString objects were created are now completely different and the string pointers will no longer be sorted in the new process the cache was loaded into.
The unit tests created for the initial patch didn't catch the encoding and decoding issues of UniqueCStringMap<T> because they were happening in the same process and encoding and decoding would end up createing sorted UniqueCStringMap<T> objects due to the constant string pool being exactly the same.
This patch does the sort and also reserves the right amount of entries in the UniqueCStringMap::m_map prior to adding them all to avoid doing multiple allocations.
Added a unit test that loads an object file from yaml, and then I created a cache file for the original file and removed the cache file's signature mod time check since we will generate an object file from the YAML, and use that as the object file for the Symtab object. Then we load the cache data from the array of symtab cache bytes so that the ConstString "const char *" values will not match the current process, and verify we can lookup the 4 names from the object file in the symbol table.
Differential Revision: https://reviews.llvm.org/D124572
Joe Nash [Wed, 13 Apr 2022 18:14:03 +0000 (14:14 -0400)]
[AMDGPU][clang] Definition of gfx11 subtarget
Contributors:
Jay Foad <jay.foad@amd.com>
Konstantin Zhuravlyov <kzhuravl_dev@outlook.com>
Patch 2/N for upstreaming of AMDGPU gfx11 architecture
Depends on D124536
Reviewed By: foad, kzhuravl, #amdgpu, arsenm
Differential Revision: https://reviews.llvm.org/D124537
Stanislav Mekhanoshin [Wed, 27 Apr 2022 23:28:44 +0000 (16:28 -0700)]
[AMDGPU] Produce waitcounts for LDS DMA
MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS written
can be accessed. A load from LDS to VMEM does not need a wait.
Differential Revision: https://reviews.llvm.org/D124626
Peter Klausler [Fri, 29 Apr 2022 16:28:30 +0000 (09:28 -0700)]
[flang] Fix build bot problem
A recent change is eliciting a valid warning from the out-of-tree
flang build bot; fix by using a reference in a range-based for().
Differential Revision: https://reviews.llvm.org/D124682
Jim Ingham [Fri, 29 Apr 2022 18:11:16 +0000 (11:11 -0700)]
Add a paragraph showing how to use container commands.
Differential Revision: https://reviews.llvm.org/D124028
Vitaly Buka [Wed, 27 Apr 2022 23:59:00 +0000 (16:59 -0700)]
[mlir] Prevent argStorage relocations
This fixes msan reports like https://reviews.llvm.org/P8285
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D124576
Jim Ingham [Fri, 29 Apr 2022 18:07:22 +0000 (11:07 -0700)]
Add a mutex to the ThreadPlanStackMap class.
We've seen very occasional crashes that we can only explain by
simultaneous access to the ThreadPlanStackMap, so I'm adding a
mutex to protect it.
Differential Revision: https://reviews.llvm.org/D124029
Bill Wendling [Fri, 29 Apr 2022 18:04:58 +0000 (11:04 -0700)]
[randstruct] Automatically randomize a structure of function pointers
Strutures of function pointers are a good surface area for attacks. We
should therefore randomize them unless explicitly told not to.
Reviewed By: aaron.ballman, MaskRay
Differential Revision: https://reviews.llvm.org/D123544
Joe Nash [Fri, 29 Apr 2022 17:30:29 +0000 (13:30 -0400)]
Fix sphinx build error in AMDGPUUsage.rst
Corrects error from
813e521e55b11165138b071f446eda94b14570dc
David Penry [Tue, 29 Mar 2022 17:13:55 +0000 (10:13 -0700)]
Reapply [CodeGen][ARM] Enable Swing Module Scheduling for ARM
Fixed "private field is not used" warning when compiled
with clang.
original commit:
28d09bbbc3d09c912b54a4d5edb32cab7de32a6f
reverted in:
fa49021c68ef7a7adcdf7b8a44b9006506523191
------
This patch permits Swing Modulo Scheduling for ARM targets
turns it on by default for the Cortex-M7. The t2Bcc
instruction is recognized as a loop-ending branch.
MachinePipeliner is extended by adding support for
"unpipelineable" instructions. These instructions are
those which contribute to the loop exit test; in the SMS
papers they are removed before creating the dependence graph
and then inserted into the final schedule of the kernel and
prologues. Support for these instructions was not previously
necessary because current targets supporting SMS have only
supported it for hardware loop branches, which have no
loop-exit-contributing instructions in the loop body.
The current structure of the MachinePipeliner makes it difficult
to remove/exclude these instructions from the dependence graph.
Therefore, this patch leaves them in the graph, but adds a
"normalization" method which moves them in the schedule to
stage 0, which causes them to appear properly in kernel and
prologues.
It was also necessary to be more careful about boundary nodes
when iterating across successors in the dependence graph because
the loop exit branch is now a non-artificial successor to
instructions in the graph. In additional, schedules with physical
use/def pairs in the same cycle should be treated as creating an
invalid schedule because the scheduling logic doesn't respect
physical register dependence once scheduled to the same cycle.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D122672
Aaron Ballman [Fri, 29 Apr 2022 17:36:53 +0000 (13:36 -0400)]
Silence -Wstrict-prototype diagnostics in C2x mode
This also disables the diagnostic when the user passes -fno-knr-functions.
Dimitry Andric [Fri, 29 Apr 2022 13:24:15 +0000 (15:24 +0200)]
[lldb] Define LLDB_VERSION_PATCH correctly
In commit
ccf1469a4cdb lldb got its own generated Version.inc file, with
`LLDB_VERSION` macros. However, it used `LLDB_VERSION_PATCHLEVEL`
instead of the actually correct `LLDB_VERSION_PATCH`. Correct this.
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D124672
Joseph Huber [Fri, 29 Apr 2022 17:05:36 +0000 (13:05 -0400)]
[Clang][Docs] Add new offloading flags to the clang documentation
Summary:
Some previous patches introduced the `--offload-new-driver` flag, which
is a generic way to enable the new driver, and the `--offload-host-only`
and `--offload-device-only` flags which allow users to compile for one
side, making it easier to inspect intermediate code for offloading
compilations. This patch just documents them in the command line
reference.
Philip Reames [Fri, 29 Apr 2022 17:00:14 +0000 (10:00 -0700)]
[RISCV] Factor repeating code into getMaskTypeFor(VT) [nfc]
Joe Nash [Tue, 12 Apr 2022 20:05:06 +0000 (16:05 -0400)]
[AMDGPU] Add gfx11 subtarget ELF definition
This is the first patch of a series to upstream support for the new
subtarget.
Contributors:
Jay Foad <jay.foad@amd.com>
Konstantin Zhuravlyov <kzhuravl_dev@outlook.com>
Patch 1/N for upstreaming AMDGPU gfx11 architectures.
Reviewed By: foad, kzhuravl, #amdgpu
Differential Revision: https://reviews.llvm.org/D124536
Paul Walker [Thu, 10 Feb 2022 17:21:32 +0000 (17:21 +0000)]
[SVE] Move reg+reg gather/scatter addressing optimisations from lowering into DAG combine.
This is essentially a refactoring patch but allows more cases to
be caught, hence the output changes to some tests.
Differential Revision: https://reviews.llvm.org/D122994
Philip Reames [Thu, 28 Apr 2022 21:56:27 +0000 (14:56 -0700)]
[RISCV] Extract getAllOnesMask helper [nfc]
Alexey Bataev [Fri, 29 Apr 2022 16:27:13 +0000 (09:27 -0700)]
[SLP][NFC]Fix a comment.
Craig Topper [Fri, 29 Apr 2022 15:41:52 +0000 (08:41 -0700)]
[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.
It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+ADDI. Because ADDI uses a sign
extended constant, it's possible that after subtracting it out, we
end up with a simm32 that maps to LUI.
This patch detects this case after removing Lo12 and before shifting
the value for SLLI.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D124222
Joseph Huber [Mon, 21 Feb 2022 19:39:58 +0000 (14:39 -0500)]
[OpenMP] Allow CUDA to be linked with OpenMP using the new driver
After basic support for embedding and handling CUDA files was added to
the new driver, we should be able to call CUDA functions from OpenMP
code. This patch makes the necessary changes to successfuly link in CUDA
programs that were compiled using the new driver. With this patch it
should be possible to compile device-only CUDA code (no kernels) and
call it from OpenMP as follows:
```
$ clang++ cuda.cu -fopenmp-new-driver -offload-arch=sm_70 -c
$ clang++ openmp.cpp cuda.o -fopenmp-new-driver -fopenmp -fopenmp-targets=nvptx64 -Xopenmp-target=nvptx64 -march=sm_70
```
Currently this requires using a host variant to suppress the generation
of a CPU-side fallback call.
Depends on D120272
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D120273
Nikita Popov [Fri, 29 Apr 2022 15:33:49 +0000 (17:33 +0200)]
[InstCombine] Require LoopInfo in test (NFC)
This test case doesn't show what it was intended to without
require<loops>.
Joseph Huber [Fri, 22 Apr 2022 00:13:33 +0000 (20:13 -0400)]
[OpenMP] Add options to only compile the host or device when offloading
OpenMP recently moved to the new offloading driver, this had the effect
of making it more difficult to inspect intermediate code for the device.
This patch adds `-foffload-host-only` and `-foffload-device-only` to
control which sides get compiled. This will allow users to more easily
inspect output without needing the temp files.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D124220
Nikita Popov [Fri, 29 Apr 2022 15:10:13 +0000 (17:10 +0200)]
[InstCombine] Add additional tests for gep of minus ptrtoint (NFC)
Simon Pilgrim [Fri, 29 Apr 2022 12:39:16 +0000 (13:39 +0100)]
[X86] lowerShuffleAsRepeatedMaskAndLanePermute - move the sublane split code into a lambda helper. NFC.
This is a NFC cleanup as part of the work on #55066 - the idea being that we will be able to check for multiple sub lane scales.
Alexey Bataev [Fri, 29 Apr 2022 13:46:38 +0000 (06:46 -0700)]
[COST]Fix crash for non-power-2 vector shuffle mask.
Need to normalizize the mask to avoid possible crashes during attempts
to estimate cost of the very long shuffles with non-power-2 number of
elements in masks.
Florian Hahn [Fri, 29 Apr 2022 14:19:06 +0000 (15:19 +0100)]
[SimplifyCFG] Avoid shifting by a too large exponent.
TI->getBitWidth can be > 64 and in those cases the shift will be UB due
to the exponent being too large.
To fix this, cap the shift at 63. I think this should work out fine,
because TableSize is itself a 64 bit type and the maximum table size
must fit in the type. Also, if we would underestimate the size here, at
most we get an extra ZExt.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D124608
David Candler [Fri, 29 Apr 2022 14:06:12 +0000 (15:06 +0100)]
Additionally set f32 mode with denormal-fp-math
When the denormal-fp-math option is used, this should set the
denormal handling mode for all floating point types. However,
currently 32-bit float types can ignore this setting as there is a
variant of the option, denormal-fp-math-f32, specifically for that type
which takes priority when checking the mode based on type and remains
at the default of IEEE. From the description, denormal-fp-math would
be expected to set the mode for floats unless overridden by the f32
variant, and code in the front end only emits the f32 option if it is
different to the general one, so setting just denormal-fp-math should
be valid.
This patch changes the denormal-fp-math option to also set the f32
mode. If denormal-fp-math-f32 is also specified, this is then
overridden as expected, but if it is absent floats will be set to the
mode specified by the former option, rather than remain on the default.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D122589
Anna Thomas [Wed, 27 Apr 2022 15:00:58 +0000 (11:00 -0400)]
[CompileTime] [Passes] Avoid computing unnecessary analyses. NFC
Similar to
c515b2f39e77, If there are no loops in the function as seen
through LI, we should avoid computing the remaining expensive analyses
(such as SCEV, BPI). Reordered the analyses requests and early return
if there are no loops.
The logic of avoiding expensive analyses is applied to LoopVectorizer,
LoopLoadElimination and LoopUnrollPass, i.e. all function passes which operate
on loops.
This is an NFC with compile time improvement.
Differential Revision: https://reviews.llvm.org/D124529
Stefan Pintilie [Mon, 25 Apr 2022 20:03:23 +0000 (15:03 -0500)]
[PowerPC][NFC] Add a function to determine if a call needs to be NOTOC.
Add the isNoTOCCallInstr function to PPCInstrInfo to determine if a call opcode
does not need a TOC restore after the call. All call opcodes should be listed in
this function. A default unreachable in this function should force future call
opcodes to also be added.
This is a follow up patch to D122012
Reviewed By: jsji, shchenz
Differential Revision: https://reviews.llvm.org/D124415
Martin Boehme [Thu, 28 Apr 2022 14:41:47 +0000 (16:41 +0200)]
[clang] Eliminate TypeProcessingState::trivial.
This flag is redundant -- it's true iff `savedAttrs` is empty.
Querying `savedAttrs.empty()` should not take any more time than querying the
`trivial` flag, so this should not have a performance impact either.
I noticed this while working on https://reviews.llvm.org/D111548.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D123783
Paul Walker [Thu, 7 Apr 2022 17:24:36 +0000 (18:24 +0100)]
[DAGCombiner] Stop invalid sign conversion in refineIndexType.
When looking through extends of gather/scatter indices it's safe
to convert a known positive signed index to unsigned, but unsigned
indices must remain unsigned.
Depends On D123318
Differential Revision: https://reviews.llvm.org/D123326
Paul Walker [Thu, 7 Apr 2022 16:42:11 +0000 (17:42 +0100)]
[SVE][ISel] Ensure explicit gather/scatter offset extension isn't lost.
getGatherScatterIndexIsExtended currently looks through all
SIGN_EXTEND_INREG operations regardless of their input type. This
patch restricts the code to only look through i32->i64 extensions,
which are the ones supported implicitly by SVE addressing modes.
Differential Revision: https://reviews.llvm.org/D123318
Joseph Huber [Mon, 21 Feb 2022 15:08:26 +0000 (10:08 -0500)]
[CUDA] Add driver support for compiling CUDA with the new driver
This patch adds the basic support for the clang driver to compile and link CUDA
using the new offloading driver. This requires handling the CUDA offloading kind
and embedding the generated files into the host. This will allow us to link
OpenMP code with CUDA code in the linker wrapper. More support will be required
to create functional CUDA / HIP binaries using this method.
Depends on D120270 D120271 D120934
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D120272
Joseph Huber [Thu, 7 Apr 2022 17:12:21 +0000 (13:12 -0400)]
[Clang] Make enabling the new driver more generic
In preparation for allowing other offloading kinds to use the new driver
a new opt-in flag `-foffload-new-driver` is added. This is distinct from
the existing `-fopenmp-new-driver` because OpenMP will soon use the new
driver by default while the others should not.
Reviewed By: yaxunl, tra
Differential Revision: https://reviews.llvm.org/D123325
Joseph Huber [Thu, 7 Apr 2022 15:05:29 +0000 (11:05 -0400)]
[OpenMP] Make clang argument handling for the new driver more generic
In preparation for accepting other offloading kinds with the new driver,
this patch makes the way we handle offloading actions more generic. A
new field to get the associated device action's toolchain is used rather
than manually iterating a list. This makes building the arguments easier
and makes sure that we doin't rely on any implicit ordering.
Reviewed By: yaxunl
Differential Revision: https://reviews.llvm.org/D123313
Joseph Huber [Sun, 10 Apr 2022 02:32:49 +0000 (22:32 -0400)]
[OpenMP] Make generating offloading entries more generic
This patch moves the logic for generating the offloading entries to the
OpenMPIRBuilder. This makes it easier to re-use in other places, such as
for OpenMP support in Flang or using the same method for generating
offloading entires for other languages like Cuda.
Reviewed By: tianshilei1992
Differential Revision: https://reviews.llvm.org/D123460
Nikita Popov [Fri, 29 Apr 2022 13:08:17 +0000 (15:08 +0200)]
[InstCombine] Add test for unused atomic load from non-constant global (NFC)
Nikita Popov [Wed, 27 Apr 2022 15:19:52 +0000 (17:19 +0200)]
[SelectionDAGBuilder] Don't create MGATHER/MSCATTER with Scale != ElemSize
This is an alternative to D124530. In getUniformBase() only create
scales that match the gather/scatter element size. If targets also
support other scales, then they can produce those scales in target
DAG combines. This is what X86 already does (as long as the
resulting scale would be 1, 2, 4 or 8).
This essentially restores the pre-opaque-pointer state of things.
Fixes https://github.com/llvm/llvm-project/issues/55021.
Differential Revision: https://reviews.llvm.org/D124605
Jean Perier [Fri, 29 Apr 2022 12:52:27 +0000 (14:52 +0200)]
[flang] Handle common block with different sizes in same file
Semantics is not preventing a named common block to appear with
different size in a same file (named common block should always have
the same storage size (see Fortran 2018 8.10.2.5), but it is a common
extension to accept different sizes).
Lowering was not coping with this well, since it just use the first
common block appearance, starting with BLOCK DATAs to define common
blocks (this also was an issue with the blank common block, which can
legally appear with different size in different scoping units).
Semantics is also not preventing named common from being initialized
outside of a BLOCK DATA, and lowering was dealing badly with this,
since it only gave an initial value to common blocks Globals if the
first common block appearance, starting with BLOCK DATAs had an initial
value.
Semantics is also allowing blank common to be initialized, while
lowering was assuming this would never happen, and was never creating
an initial value for it.
Lastly, semantics was not complaining if a COMMON block was initialized
in several scoping unit in a same file, while lowering can only generate
one of these initial value.
To fix this, add a structure to keep track of COMMON block properties
(biggest size, and initial value if any) at the Program level. Once the
size of a common block appearance is know, the common block appearance
is checked against this information. It allows semantics to emit an error
in case of multiple initialization in different scopes of a same common
block, and to warn in case named common blocks appears with different
sizes. Lastly, this allows lowering to use the Program level info about
common blocks to emit the right GlobalOp for a Common Block, regardless
of the COMMON Block appearances order: It emits a GlobalOp with the
biggest size, whose lowest bytes are initialized with the initial value
if any is given in a scope where the common block appears.
Lowering is updated to go emit the common blocks before anything else so
that the related GlobalOps are available when lowering the scopes where
common block appear. It is also updated to not assume that blank common
are never initialized.
Differential Revision: https://reviews.llvm.org/D124622
Nikita Popov [Thu, 21 Apr 2022 13:57:37 +0000 (15:57 +0200)]
[InstCombine] Remove memset of undef value
This removes memset with undef char. We already do this for stores
of undef value.
This comes with the caveat that this optimization is not, strictly
speaking, legal for undef values, because we might be overwriting
a poison value. However, our entire load/store model currently still
operates on undef values, so we need to support undef here as well
for internal consistency.
Once https://github.com/llvm/llvm-project/issues/52930 is resolved,
these and related folds can be limited to poison -- I've added
FIXMEs to that effect.
Differential Revision: https://reviews.llvm.org/D124173
Ricky Zhou [Fri, 29 Apr 2022 12:42:00 +0000 (13:42 +0100)]
[LV] Rename CountRoundDown to VectorTripCount (NFC)
The name CountRoundDown is potentially misleading, as the number of
iterations can be rounded up when folding the tail.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D119681
Nikita Popov [Fri, 29 Apr 2022 10:49:52 +0000 (12:49 +0200)]
[InstCombine] Fold logical and/or of range icmps with nowrap flags
This is an edge-case where we don't convert to bitwise and/or based
on implies poison reasoning, so explicitly try to perform the fold
in logical form. The transform itself is poison-safe, as both icmps
are based on the same value and any nowrap flags are discarded as
part of the fold (https://alive2.llvm.org/ce/z/aCwC8b for the used
example).
Matthias Springer [Fri, 29 Apr 2022 12:34:41 +0000 (21:34 +0900)]
[mlir][linalg][transform] Add TileOp to transform dialect
This commit adds a tiling op to the transform dialect as an external op.
Differential Revision: https://reviews.llvm.org/D124661
Florian Hahn [Fri, 29 Apr 2022 12:34:54 +0000 (13:34 +0100)]
[VPlan] Simplify & adjust code as suggested in D123005.
Improve code as suggested in D123005. Applied separately, because the
comments where made a diff that has not been rebased to current main.
David Spickett [Fri, 29 Apr 2022 12:22:33 +0000 (12:22 +0000)]
[lldb] Allow EXE or exe in toolchain-msvc.test
I suspect that one of link or cl is found by shutil.which
and one isn't, hence the case difference. It doesn't really
matter for what the test is looking for.
NAKAMURA Takumi [Fri, 29 Apr 2022 11:15:07 +0000 (20:15 +0900)]
llvm/Support/Debug.h: Suppress warnings with -Asserts. [-Wunused-variable]
Re. setCurrentDebugTypes(X,N), the only user is llvm-ml.cpp (exc. DebugTests)
since llvmorg-15-init-8355-g82ecf9a0b1b3.
FIXME: X and N are evaluated regardless of NDEBUG.
Could we avoid evaluating (but w/o warnings) with NDEBUG?
NAKAMURA Takumi [Fri, 29 Apr 2022 11:32:46 +0000 (20:32 +0900)]
AVRExpandPseudoInsts.cpp: Fix a warning. [-Wunused-but-set-variable]
It has been enabled since llvmorg-15-init-5683-g2af845a6519c, aka D122271.
Paul Walker [Tue, 5 Apr 2022 16:49:01 +0000 (17:49 +0100)]
[DAGCombiner][SVE] Ensure MGATHER/MSCATTER addressing mode combines preserve index scaling
refineUniformBase and selectGatherScatterAddrMode both attempt the
transformation:
base(0) + index(A+splat(B)) => base(B) + index(A)
However, this is only safe when index is not implicitly scaled.
Differential Revision: https://reviews.llvm.org/D123222
David Spickett [Fri, 29 Apr 2022 11:21:59 +0000 (11:21 +0000)]
Reland "[lldb] Use shutil.which in Shell tests find_executable"
This reverts commit
d9247cc84825539d346c74eb1379c6cb948d3a71.
With the Windows tests updated to expect .EXE suffixes. This changed
because shutil.which uses PATHEXT which will contain, amongst others,
"EXE".
Also I noticed the "." in ".exe" was the wildcard dot not literal
dot so I've escaped those.
Nikita Popov [Fri, 29 Apr 2022 11:24:04 +0000 (13:24 +0200)]
[InstCombine] Add test for is_alpha check with logical or and nsw (NFC)
The combination of logical or and nsw prevents the fold from
happening.
Jay Foad [Fri, 29 Apr 2022 11:05:27 +0000 (12:05 +0100)]
[AMDGPU] Simplify the test case for D124450
Simon Pilgrim [Fri, 29 Apr 2022 11:08:27 +0000 (12:08 +0100)]
[X86] SimplifyDemandedVectorEltsForTargetNode - fold (uniform) shift(0,x) -> 0
Sam McCall [Fri, 29 Apr 2022 11:08:28 +0000 (13:08 +0200)]
[include-cleaner] Add missing deps from unittests
David Spickett [Fri, 29 Apr 2022 11:02:59 +0000 (11:02 +0000)]
Revert "[lldb] Use shutil.which in Shell tests find_executable"
This reverts commit
713752610edd3d8766f56e2704bb7241434cd15b.
Some test output needs updating for Windows builders:
https://lab.llvm.org/buildbot/#/builders/83/builds/18356
Nikita Popov [Fri, 29 Apr 2022 10:45:42 +0000 (12:45 +0200)]
[InstCombine] Pass ICmpInsts to foldAndOrOfICmpsUsingRanges() (NFC)
Pass the whole instruction rather than unpacking it. This makes it
easier to reuse the function in another place, as the entire
logic is encapsulated.
Simon Pilgrim [Fri, 29 Apr 2022 10:32:22 +0000 (11:32 +0100)]
[X86] SimplifyDemandedVectorEltsForTargetNode - fold shift(0,x) -> 0
Nikita Popov [Fri, 29 Apr 2022 10:15:03 +0000 (12:15 +0200)]
[InstCombine] Remove foldAndOrOfEqualityCmpsWithConstants() fold
This fold handles a special subset of foldAndOrOfICmpsUsingRanges(),
use the more generic implementation instead.
The result can differ if a representation using a range comparison
is possible, in which case that is preferred over masking. There is
a canonicalization opportunity here.
Florian Hahn [Fri, 29 Apr 2022 10:09:19 +0000 (11:09 +0100)]
[OCaml] Remove add_loop_unswitch use in test.
Nikita Popov [Fri, 29 Apr 2022 09:31:12 +0000 (11:31 +0200)]
[InstCombine] Fold and of two ranges differing by mask
This is the de Morgan conjugated variant of the existing fold for
ors. Implement this by switching the range code to always work
on ors and perform invert operands at the start and end. This makes
reasoning easier and makes the extension more obviosuly correct.
David Spickett [Thu, 28 Apr 2022 10:24:49 +0000 (10:24 +0000)]
[lldb] Use shutil.which in Shell tests find_executable
In build.py we have our own find_executable that looks
a lot like the distutils one that I switched to shutil.which.
This find_executable isn't quite the same as shutil.which
so I've refactored it to call that in the correct way.
Note that the path passed to shutil.which is in the form that
PATH would be, meaning separators are allowed.
```
>>> shutil.which("gcc", path="/home/david.spickett:/bin")
'/bin/gcc'
```
We just need to make sure it doesn't ignore the existing PATH
and normalise the result if it does find the binary.
The .exe extension is automatically added to the binary name
if we are on Windows.
Depends on D124601
Reviewed By: JDevlieghere
Differential Revision: https://reviews.llvm.org/D124604
Florian Hahn [Fri, 29 Apr 2022 09:53:17 +0000 (10:53 +0100)]
Remove loop-unswitch from various bindings.
LoopUnswitch has been removed in
fb4113ef0c8b.
Also remove it from various bindings.