nir/gather_info: take texture vars into account when counting textures

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>

glsl: add texture subpass variants

Dzn needs those as it lowers images to textures and we want to be more
consistent about texture ops using texture vars instead of images.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>

glsl: fix buffer texture type

Fixes: 3ace6b968b3 ("compiler/types: Add a texture type")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19381>

ac/nir: do not convert GS outputs to the expected variable size on GFX11

Outputs are always considered 32-bits.
Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19612>

zink: Only #include <vulkan/vulkan_core.h> instead #include <vulkan/vulkan.h> in kopper_interface.h

It's pulled too much system dependent headers before this commit
when #include <vulkan/vulkan.h> directly,

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>

zink: struct kopper_surface is not accessed, remove it in kopper_interface.h

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>

zink: Indent with 3 space in zink/zink_kopper.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>

wgl: Trim trailing spaces in stw_st.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19491>

util: Use include_directories('..') instead include_directories('.') for inc_util

So include util headers are always using util/ prefix in mesa code base
And prevent including files under src/util without util/ prefix

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19546>

util: normalize include files under src/util/*.h with util/ prefix in mesa code base

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19546>

util: Move texcompress template files into util/format

Because these files are accessed in  util/format/u_format_*.c
To make sure util are self contained we need move these files

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19547>

mesa: include <util/*.h> instead macros.h in texcompress_bptc_tmp.h

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19547>

util: Replace the usage of ALIGN16 with alignas(16) and them remove ALIGN16 macro

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19565>

vulkan: Replace _Alignas with alignas

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19565>

meson: Use deps_for_libmesa_util for idep_mesautil instead hand crafted list

Now the idep_mesautilc11 have no need reference when idep_mesautil is referenced

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19526>

meson: Indent util/meson.build with 2 space

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19526>

agx: Don't assert on texop twice

This is already asserted for lod modes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Implement unary math ops

Implement nir_op_bitfield_reverse, nir_op_bit_count, and
nir_op_ufind_msb. These map to native instructions.  With appropriate
integer render target and multiple render target support, passes:

   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldreverse.*fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.bitcount.*fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findLSB.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findLSB.*fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findMSB.*vertex
   dEQP-GLES31.functional.shaders.builtin_functions.integer.findMSB.*fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Implement {i,u}mul_2x32_64

With support for MRT in the driver (not included here), passes:

   dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.int_highp_fragment
   dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.int_highp_fragment

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Implement nir_op_unpack_64_2x32_split_{x,y}

Used in the umul_extended lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx/ra: Remove index_to_reg

Use stronger asserts instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Add CSE optimization pass

Ported from the Bifrost compiler, in turn based on the ir3 one. This
cleans up a lot of junk we emit during NIR->AGX and will help with some
SSA RA troubles.

total instructions in shared programs: 34803 -> 34381 (-1.21%)
instructions in affected programs: 18652 -> 18230 (-2.26%)
helped: 198
HURT: 0
helped stats (abs) min: 1.0 max: 28.0 x̄: 2.13 x̃: 1
helped stats (rel) min: 0.31% max: 12.50% x̄: 3.94% x̃: 2.78%
95% mean confidence interval for instructions value: -2.45 -1.81
95% mean confidence interval for instructions %-change: -4.40% -3.48%
Instructions are helped.

total bytes in shared programs: 238094 -> 234824 (-1.37%)
bytes in affected programs: 126472 -> 123202 (-2.59%)
helped: 200
HURT: 0
helped stats (abs) min: 6.0 max: 168.0 x̄: 16.35 x̃: 8
helped stats (rel) min: 0.37% max: 17.65% x̄: 4.25% x̃: 3.38%
95% mean confidence interval for bytes value: -18.49 -14.21
95% mean confidence interval for bytes %-change: -4.67% -3.84%
Bytes are helped.

total halfregs in shared programs: 10078 -> 10107 (0.29%)
halfregs in affected programs: 565 -> 594 (5.13%)
helped: 22
HURT: 22
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.23 x̃: 1
helped stats (rel) min: 5.71% max: 25.00% x̄: 23.38% x̃: 25.00%
HURT stats (abs)   min: 2.0 max: 4.0 x̄: 2.55 x̃: 2
HURT stats (rel)   min: 4.44% max: 30.77% x̄: 15.61% x̃: 12.73%
95% mean confidence interval for halfregs value: 0.03 1.28
95% mean confidence interval for halfregs %-change: -10.17% 2.40%
Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Describe whether instructions may be reordered

As per NIR, for the benefit of CSE. It is assumed that instructions that
cannot be eliminated also cannot be reordered.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Add and use replace_src helper

From Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Use nir_opt_phi_precision

No shader-db changes, but helped a custom shader I wrote to test loops.
My shader-db is too small.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Pass agx_index to agx_copy

More straightforward interface and will allow including immediates later
if we want to.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Coalesce collects when possible

Track collects and use them as affinities when choosing registers. On
glmark2:

total instructions in shared programs: 5498 -> 5388 (-2.00%)
instructions in affected programs: 2748 -> 2638 (-4.00%)
helped: 31
HURT: 0
helped stats (abs) min: 1.0 max: 12.0 x̄: 3.55 x̃: 3
helped stats (rel) min: 0.09% max: 57.14% x̄: 10.58% x̃: 5.97%
95% mean confidence interval for instructions value: -4.61 -2.49
95% mean confidence interval for instructions %-change: -15.16% -6.00%
Instructions are helped.

total bytes in shared programs: 37280 -> 36620 (-1.77%)
bytes in affected programs: 18880 -> 18220 (-3.50%)
helped: 31
HURT: 0
helped stats (abs) min: 6.0 max: 72.0 x̄: 21.29 x̃: 18
helped stats (rel) min: 0.07% max: 48.98% x̄: 9.16% x̃: 5.17%
95% mean confidence interval for bytes value: -27.64 -14.94
95% mean confidence interval for bytes %-change: -13.03% -5.29%
Bytes are helped.

total halfregs in shared programs: 1267 -> 1279 (0.95%)
halfregs in affected programs: 37 -> 49 (32.43%)
helped: 0
HURT: 9
HURT stats (abs)   min: 1.0 max: 2.0 x̄: 1.33 x̃: 1
HURT stats (rel)   min: 16.67% max: 66.67% x̄: 35.58% x̃: 28.57%
95% mean confidence interval for halfregs value: 0.95 1.72
95% mean confidence interval for halfregs %-change: 21.50% 49.67%
Halfregs are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Introduce agx_foreach_ssa_{src,dest} macros

These are convenient iterators especially in the register allocator.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx/ra: Factor out assign_regs

Prepare to record bookkeeping needed for live range splits.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx/ra: Use BITSET_*_RANGE in some places

A bit neater.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Free dests of splits that are never read

Otherwise the registers "leak", bloating register pressure by
arbitrarily large amounts. This is easy to handle in DCE by rewriting to
a null destination, though we could use a sideband channel if we didn't
want null destinations in the IR.

glmark2 subset of shader-db is much improved:

total instructions in shared programs: 7324 -> 7313 (-0.15%)
instructions in affected programs: 483 -> 472 (-2.28%)
helped: 5
HURT: 2

total bytes in shared programs: 42788 -> 42722 (-0.15%)
bytes in affected programs: 2808 -> 2742 (-2.35%)
helped: 5
HURT: 2

total halfregs in shared programs: 2421 -> 2058 (-14.99%)
halfregs in affected programs: 1235 -> 872 (-29.39%)
helped: 28
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Refuse to handle discontiguous iter

This will cause problems with register allocation.

instructions HURT:   shaders/glmark/1-24.shader_test MESA_SHADER_FRAGMENT: 135 -> 136 (0.74%)
instructions HURT:   shaders/glmark/1-8.shader_test MESA_SHADER_FRAGMENT: 84 -> 85 (1.19%)

bytes HURT:   shaders/glmark/1-24.shader_test MESA_SHADER_FRAGMENT: 914 -> 922 (0.88%)
bytes HURT:   shaders/glmark/1-8.shader_test MESA_SHADER_FRAGMENT: 574 -> 580 (1.05%)

halfregs helped:   shaders/glmark/1-8.shader_test MESA_SHADER_FRAGMENT: 20 -> 19 (-5.00%)
halfregs helped:   shaders/glmark/1-24.shader_test MESA_SHADER_FRAGMENT: 25 -> 23 (-8.00%)
halfregs helped:   shaders/glmark/7-3.shader_test MESA_SHADER_FRAGMENT: 11 -> 10 (-9.09%)
halfregs helped:   shaders/glmark/4-2.shader_test MESA_SHADER_FRAGMENT: 23 -> 19 (-17.39%)

total instructions in shared programs: 5716 -> 5718 (0.03%)
instructions in affected programs: 219 -> 221 (0.91%)
helped: 0
HURT: 2

total bytes in shared programs: 38118 -> 38132 (0.04%)
bytes in affected programs: 1488 -> 1502 (0.94%)
helped: 0
HURT: 2

total halfregs in shared programs: 1639 -> 1631 (-0.49%)
halfregs in affected programs: 79 -> 71 (-10.13%)
helped: 4
HURT: 0
helped stats (abs) min: 1.0 max: 4.0 x̄: 2.00 x̃: 1
helped stats (rel) min: 5.00% max: 17.39% x̄: 9.87% x̃: 8.55%
95% mean confidence interval for halfregs value: -4.25 0.25
95% mean confidence interval for halfregs %-change: -18.31% -1.43%
Inconclusive result (value mean confidence interval includes 0).

Total CPU time (seconds): 11.41 -> 11.72 (2.72%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

agx: Don't emit writeout 0xC200

Metal omits this in OpenGL mode, and since we have no clue what it does,
I see no reason for us not to do the same.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>

mesa: fix typo from adding glGetObjectLabelEXT

Fixes:  675bcbb7a1c0 ("mesa: add EXT_debug_label support")

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19607>

docs: update calendar for 22.3.0-rc2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19631>

ci/iris: Add some flakes from the new testing on JSL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19628>

intel/fs: Enable nir_op_imul_32x16 and nir_op_umul_32x16 on pre-Gfx7

Even though Intel's CI doesn't test these old platforms anymore, the
validation added in "intel/eu/validate: Validate integer multiplication
source size restrictions" combined with full shader-db runs gives me
confidence in the changes.

Sandy Bridge
total instructions in shared programs: 13902341 -> 13902167 (<.01%)
instructions in affected programs: 30771 -> 30597 (-0.57%)
helped: 66 / HURT: 0

total cycles in shared programs: 741795500 -> 741791931 (<.01%)
cycles in affected programs: 987602 -> 984033 (-0.36%)
helped: 28 / HURT: 5

Iron Lake
total instructions in shared programs: 8365806 -> 8365754 (<.01%)
instructions in affected programs: 1766 -> 1714 (-2.94%)
helped: 10 / HURT: 0

total cycles in shared programs: 248542694 -> 248542378 (<.01%)
cycles in affected programs: 29836 -> 29520 (-1.06%)
helped: 9 / HURT: 0

GM45
total instructions in shared programs: 5187127 -> 5187101 (<.01%)
instructions in affected programs: 891 -> 865 (-2.92%)
helped: 5 / HURT: 0

total cycles in shared programs: 163643914 -> 163643750 (<.01%)
cycles in affected programs: 22206 -> 22042 (-0.74%)
helped: 5 / HURT: 0

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

intel/fs: Slightly restructure emitting nir_op_imul_32x16 and nir_op_umul_32x16

There are no immediate values at this point, so all of this code was
bunk. :face_palm:

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

intel/eu/validate: Validate integer multiplication source size restrictions

v2: Expect correct result on BDW in test_eu.

v3: Fix SNB type-size check. Noticed by Marcin.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

intel/compiler: Fix signed integer range analysis of imax and imin

Some review feedback of an earlier commit caused me to rearrange some
code quite a bit. I wasn't paying enough attention while applying the
later commits, and these breaks should have been returns. As it is, the
result of the imin or imax analysis is overwritten by the default case
handling... effectively the original commit does nothing. :(

Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs: 19914090 -> 19904772 (-0.05%)
instructions in affected programs: 121258 -> 111940 (-7.68%)
helped: 445 / HURT: 0

total cycles in shared programs: 855291535 -> 855266659 (<.01%)
cycles in affected programs: 2737005 -> 2712129 (-0.91%)
helped: 426 / HURT: 17

LOST:   0
GAINED: 3

Skylake and Broadwell had similar results. (Skylake shown)
total cycles in shared programs: 842395356 -> 842338259 (<.01%)
cycles in affected programs: 5460985 -> 5403888 (-1.05%)
helped: 458 / HURT: 0

Haswell and Ivy Bridge had similar results. (Haswell shown)
total instructions in shared programs: 16710449 -> 16708449 (-0.01%)
instructions in affected programs: 44101 -> 42101 (-4.54%)
helped: 75 / HURT: 0

total cycles in shared programs: 882760230 -> 882727923 (<.01%)
cycles in affected programs: 2867797 -> 2835490 (-1.13%)
helped: 62 / HURT: 10

No shader-db change on any other Intel platform.

No fossil-db changes on any Intel platform.

Fixes: 5ec75ca10d3 ("intel/compiler: Teach signed integer range analysis about imax and imin")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19602>

drm-shim/nouveau: fix the shim to work with nvif ioctl.

The new nouveau code asks the kernel for supported class,
this needs the new nvif interface, so stub it up using
the old code.

unfortunately this also needs a clang warning turned off
so the gnu extension this code needs is enabled in meson

Reviewed-by: M Henning <drawoc@darkrefraction.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

gv100/ir: noop OP_BAR for now

Let's get stuff rolling and deal with figuring this out later.

Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: fix ga10x compute launch

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: no tex cb mthd on ga10x

I somewhat expect this isn't necessary on Volta and newer too, as the
index is coded into shaders now, but, HW doesn't complain, so leave it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: recognise ga10x chipsets

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: properly allocate copy engine class before using it

Important for upcoming kernel changes to more correctly manage the CE
context on Volta and newer, or the channel will be killed in response
to a CTXNOTVALID error from the GPU.

The kernel will have a workaround for Volta and Turing GPUs to preserve
ABI, but will require userspace to behave correctly on Ampere and newer.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

nvc0: lookup supported classes instead of determining from chipset

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

broadcom/compiler: avoid using ldvary sequence to hide latency of branching

This can cause us to stomp the contents of r5 before we have a chance to read
it, like this:

0x3d103186bb800000 nop                           ; nop                         ; ldvary.r0
0x3d105686bbf40000 nop                           ; mov rf26, r5                ; ldvary.r1
0x020000ef0000d000 bu.allna  232, r:unif (0x0000001c / 0.000000)
0x3d1096c6bbf40000 nop                           ; mov rf27, r5                ; ldvary.r2

Here, the MOV in the last instruction is supposed to read r5 produced from
ldvary.r0, but because we have inserted the bu instruction in between now
that read happens at the same time that ldvary.r1 updates r5, stomping the
value we were supposed to read.

Fix this by disallowing injection of a branch instruction in between an ldvary
instruction and its write to the r5 register 2 instructions later.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7062
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19616>

nir/lower_io_to_vector: Demote the old scalar vars to globals.

This prevents nir_lower_io_to_temporaries from emitting new writes to the
old globals that we meant to have disappear through
DCE/remove_unused_variables.  If you don't do this, then unless you call
nir_opt_undef() and it successfully catches io_to_temps' new writes of
undefs to the scalar components, the scalar vars will stick around and
have stores that conflict with the real vector vars.

This hasn't been a problem for the end result of codegen because
nir_opt_undef() did succeed.  However, things went south with vars_to_ssa
mediump lowering, which obscured the result from opt_undef.  And, it's
really mind-bending to see undef writes to the outputs for a chunk of the
shader compiler pipeline anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18218>

intel: Don't cross DWORD boundaries with byte scratch load/store

The back-end swizzles dwords so that our indirect scratch messages match
the memory layout of spill/fill messages for better cache coherency.
The swizzle happens at a DWORD granularity.  If a read or write crosses
a DWORD boundary, the first bit will get correctly swizzled but whatever
piece lands in the next dword will not because the scatter instructions
assume sequential addresses for all bytes.  For DWORD writes, this is
handled naturally as part of scalarizing.  For smaller writes, we need
to be sure that a single write never escapes a dword.

Fixes: fd04f858b0aa ("intel/nir: Don't try to emit vector load_scratch instructions")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7364
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19580>

intel/lower_mem_access_bit_sizes: Compute alignments automatically

Because dup_mem_intrinsic() retains the SSA offset from the original
intrinsic and only modifies it by adding a constant, we can compute the
alignment based on the original alignment and the constant offset.  This
is both easier and more accurate.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19580>

vulkan/wsi/display: Reset connector state in vkReleaseDisplay().

If an application was transitioning out of fullscreen exclusive
display mode, the wsi_display_connector->active state was not
reset in vkReleaseDisplay() from fullscreen. When the app then
later tried to go to fullscreen display mode again on the same
display output with the same video mode, this caused
_wsi_display_queue_next() to skip a required drmModeSetCrtc()
during the first vkQueuePresent() after entering direct display
mode.

While this often worked by pure luck on a single-display setup,
it goes sideways on a multi-display setup where the viewport
of the associated crtc does not have a (x,y) offset of (0,0).
E.g., XOrg/X11 RandR output leasing of an output whose viewport
starts at x = 1920:

1. X-Server has RandR outputs viewport at x = 1920, in a shared
   framebuffer, shared across all crtc's on a X-Screen.

2. Application leases that output for direct display mode,
   1st vkQueuePresent() triggers drmModeSetCrtc() of output
   to (x,y) = 0,0, as required for Vulkan/wsi/direct framebuffer
   setup.

3. Application does rendering and presenting.

4. Application vkReleaseDisplay() the output, terminates the
   RandR lease. X-Server takes over again.

5. X-Server modesets to reconfigure output back to viewport
   with (x,y) = 1920, 0.

6. Application leases same output again later on, and tries
   vkQueuePresent() again. Because of the bug fixed in this
   commit, the required drmModeSetCrtc() to (x,y) = 0,0 is
   erroneously skipped due to the stale cached connector state.

7. drmModePageflip() fails due to the wrong crtc viewport
   (x,y) = 1920, 0, mismatched for the need of the Vulkan
   framebuffer of (x,y) = 0,0. Kernel returns -ENOSPACE,
   Swapchain goes into permanent VK_ERROR_SURFACE_LOST state.
   Destroying and recreating the swapchain, as recommended
   by the Vulkan spec for error handling won't help. Game over!

Resetting wsi_display_connector->active = false; fixes the
problem of wrong / stale connector state and Vulkan/wsi/display
clients are happy on multi-display setups again, as tested
in various single- and multi-display configurations.

This bug affects all Mesa releases with Vulkan/WSI/Display
support and should therefore be backported.

Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Fixes: 352d320a0745 ("vulkan: Add EXT_direct_mode_display [v2]")
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19484>

rusticl/nir: copy alignment info when lowering kernel input loads

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19614>

docs: use ext-role for GL / VK extensions

This makes sure that we generate proper links to all of these
extensions.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: add ext-role for spec extension links

This is a custom Sphinx role that generates links to GL and VK
extensions.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: drop rogue backtick

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: NV_gpu_shader4 -> NV_gpu_program4

There's no GL_NV_gpu_shader4 extension, and the TEX opcode is defined in
NV_gpu_program4. Correct the mistake.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

docs: feeddback -> feedback

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19594>

panfrost: DRY buffer range special case

Pattern from iris.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19576>

panfrost: Remove out-of-band CRC support

Without additional signalling of modifiers, CRCs cannot possibly in a correct
way work across process boundaries. Since we don't do that signalling, we should
not be allocating private CRCs for imported resources, and we should not be
using our own private CRCs for internal resources.

The entire out-of-bands CRC infrastructure is a hack to let us do CRCs even for
imported/exported BOs, but that can't possibly work. Remove it, and remove a
pile of special cases across the driver.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19576>

panfrost: Copy resources when necessary

If the map doesn't set MAP_DISCARD_RANGE, we do have to copy the existing
contents over. MAP_WRITE on its only gives permission to replace the contents,
unfortunately it does not require that the application actually do so.

Closes: #7640
Fixes: 0b26a9f7739 ("panfrost: Don't copy resources if replaced")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Roman Elshin
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19576>

radv: use radv_max_descriptor_set_size() for Vulkan 1.2 properties

Instead of copying this limit entirely.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19598>

panfrost: Fix build with Perfetto (again)

Sync UAPI for the upstream fix.

Upstream commit: https://cgit.freedesktop.org/drm-misc/commit/?h=drm-misc-fixes&id=c4299907c09a638c0a30f029338d07941c049d73

Closes: #7195
Fixes: 6a4532cbabf ("panfrost: Sync panfrost_drm.h from drm-misc-next")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Tested-by: Chris Healy <healych@amazon.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19581>

ci: Fixes macos.yml

Stick to macos-11 to prevent accident broken
always install meson with pip to prevent pull new version of python

Cc: mesa-stable
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19615>

meson: -DVK_ENABLE_BETA_EXTENSIONS at a single place

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19549>

radv/ci: add more subtests to VanGogh's flakes list

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19591>

docs: use c:expr role shorthand

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19575>

docs: remove needless c:expr roles

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19575>

docs: make c:expr the default-role

Mesa is a C-project, so c:expr is a really handy role to default to.
This means that `foo` is a short-hand for :c:expr:`foo`.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19575>

radv/rra: Fix node type validation

Silly mistake...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19584>

nir: Don't reorder volatile intrinsics

Fixes issue with "is helper invocation" that in recent SPIR-V is mapped to
a volatile Load.  The CSE was catching the loads before they were transformed
in the new is_helper_invocation intrinsic (that is not reorderable).

Fixes: 729df14e452 ("nir: Handle volatile semantics for loading HelperInvocation builtin")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19432>

freedreno/a6xx: set chroma offsets to MIDPOINT

Vulkan has VkChromaLocation and all drivers suggest
VK_CHROMA_LOCATION_MIDPOINT on Android.  The blob also uses MIDPOINT.
Based on my limited tests, the image quality is higher with MIDPOINT.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19514>

freedreno/a6xx: set CHROMA_LINEAR

This seems to have no effect on a618, but restores linear filtering on
a635 when the texture is yuv.  The blob sets it on a635 as well (but not
on a618).

Fixed android.media.cts.DecodeAccuracyTest#* on a635.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19514>

c11: Remove _MTX_INITIALIZER_NP for windows

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

egl: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER in egllog.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

nir: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER in nir/nir_validate.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

glsl: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

llvmpipe: Remove the need of _MTX_INITIALIZER_NP by using simple_mtx_t/SIMPLE_MTX_INITIALIZER in lp_texture.c

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

vulkan/device-select-layer: Remove the need of call_once by using simple_mtx_t instead mtx_t

Function device_select_once_init are removed in-favor of SIMPLE_MTX_INITIALIZER

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18493>

freedreno/a6xx: Switch to global bcolor buffer

Since we expect a limited # of unique border-color entry states, we can
use a global table of border-color entries, rather than constructing the
state at draw time.  This shifts all the border-color overhead from draw
time to sampler state CSO creation time.  And it's less code!

A hashtable is used to map unique border-color table value to entry so
multiple usages of what maps to the same table entry all re-use a single
slot in the table.  This puts an upper bound on the # of unique border-
color plus format value.  In practice this shouldn't be a problem, we'll
just size the table to be large enough to not run into problems with
CTS.  Note that the border-color table entry is not completely format
dependent (mostly just integer vs float dependent), so for example a
single color with different float formats can map to a single table
entry.

This also fixes the problem that we completely ignored border-color for
GS/tess stages.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7518
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno/a6xx: Rename tex cache key/equals fxns

We'll need different functions for border-color cache.  Prep for next
patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno/a6xx: Move bcolor entry setup

Just code motion, in prep for a following patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno/ci: Update a5xx expectations

These seem to have not been updated in a while.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

freedreno: Use our border-color quirk

This will let us remove our assumption that samplers and views map 1:1,
and generally simplify our border-color handling.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19561>

ci/bare-metal: remove consolidations leftovers

All defined in the baremetal-test-arm*

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19548>

freedreno/ir3: Reduce compiler thread pool size

With the current scheme, looking at game startup which should be the
worst case (most heavily loaded) time for the compiler threads, and they
seem to be ~10% busy.  Furthermore we typically have a mix of "big" and
"LITTLE" cores.. with about half being "big".  So sizing the thread pool
to the half the # of CPU cores seems reasonable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19387>

util/disk_cache: Add some blob cache traces

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19387>

util/disk_cache: Add compression in blob cb path

Android's implementation of the blob-cache get/put funcs do not
implement any compression.  And the default cache size is rather small,
at 2MB (!!) per app (although I assume everyone patches android to
increase the size limit).

We don't bother compressing the has_key/put_key path, since that path is
only storing a uint32_t.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19387>

vulkan/wsi/wayland: return VK_ERROR_NATIVE_WINDOW_IN_USE_KHR

If the surface is already in use by another swapchain, return
VK_ERROR_NATIVE_WINDOW_IN_USE_KHR. The spec states:

> If pCreateInfo->oldSwapchain is VK_NULL_HANDLE, and the native
> window referred to by pCreateInfo->surface is already associated
> with a Vulkan swapchain, VK_ERROR_NATIVE_WINDOW_IN_USE_KHR must
> be returned.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7467
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19229>

ci: run shaderdb on vc4 as well

Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19305>

vc4: add DRM_VC4_CREATE_SHADER_BO support to drm-shim

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19305>

nv50/ir: Support fmulz and ffmaz

Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19333>

nv50/ir: add prefer_nir flag for getting compiler options

So that we dont expose certain options for nir_to_tgsi

Signed-off-by: Yusuf Khan <yusiamerican@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19333>

tu: Support GMEM with layered rendering and multiview

It turns out that this actually is supported. GMEM can hold multiple
layers which are cleared, loaded, and resolved separately. The stride
between layers seems to be implicitly calculated based on the tile size,
and we have to match it when blitting to/from GMEM. One tricky thing is
that now we may realize that we don't have enough space for GMEM only
when computing the tiling config, because we may not know the number of
framebuffer layers until we have the framebuffer and too many
framebuffer layers will exhaust GMEM.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19505>

radv: stop emulating number of generated primitives by GS on GFX11

According to RadeonSI, only GFX10 and GFX10.3 need to emulate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19319>

anv: fix missing VkPhysicalDeviceExtendedDynamicState3PropertiesEXT handling

Fixes: 13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19573>

crocus: enable NV_alpha_to_coverage_dither_control

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19463>

iris: enable NV_alpha_to_coverage_dither_control

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19463>

radv: advertise extendedDynamicState3ColorWriteMask

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19589>

radv: add support for dynamic color write mask

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19589>