Simon Glass [Sat, 29 Jul 2017 17:35:09 +0000 (11:35 -0600)]
dm: sata: dw_sata: Rename the dwc_ahsata private header
Rename dwc_ahsata.h to indicate that it is a private header file. We plan
to create another header with some public functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:08 +0000 (11:35 -0600)]
dm: sata: dw_sata: Sort #include directives
Sort the header file inclusions into the correct order.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:07 +0000 (11:35 -0600)]
dm: sata: dw_sata: Drop unnecessary brackets
There is a strange &(var) coding style in this driver. Adjust it to use
&var instead, which is more usual.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:06 +0000 (11:35 -0600)]
dm: sata: dw_sata: Pass uc_priv to internal functions
With driver model sata_dev_desc[] does not exist. We still want to use the
common code of this driver so update it to pass struct ahci_uc_priv * to
each of these functions, instead of an integer which must be looked up in
sata_dev_desc[].
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:05 +0000 (11:35 -0600)]
dm: sata: dw_sata: Drop unnecessary casts
Most of the casts in this driver are not necessary. With driver model we
do not cast from void *. Update the driver to follow this rule.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:04 +0000 (11:35 -0600)]
dm: sata: dw_sata: Rename 'probe_ent' to uc_priv
With driver model this becomes uclass-private data. Rename the parameter
varable to reflect this.
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:03 +0000 (11:35 -0600)]
dm: sata: dw_sata: Move exported functions to the end
With the driver model conversion we will not have any exported functions.
Move all exported functions to be together at the end of the file so that
we can deal with them in one #ifdef block.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:02 +0000 (11:35 -0600)]
dm: sata: dw_sata: Drop dwc_ahsata_rw_ncq_cmd()
This function is not called from anywhere. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:01 +0000 (11:35 -0600)]
dm: sata: dwc_ahsata: Make functions static
Some functions are not called from outside this file. Make these static
to make that obvious.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:35:00 +0000 (11:35 -0600)]
dm: core: Add a comment about the device_remove() flags
We should explain which flags are used for this function. Update the
comment to indicate this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:34:59 +0000 (11:34 -0600)]
dm: blk: Update return value in blk_create_devicef()
This returns 'ret' but the value is always zero. Update it to simply
return 0, for clarity.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:34:58 +0000 (11:34 -0600)]
dm: usb: Adjust the 'usb' command to use blk_common_cmd()
Instead of having separate code in the 'usb' command, adjust it to use
the common function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 29 Jul 2017 17:34:57 +0000 (11:34 -0600)]
dm: ide: Adjust the 'ide' command to use blk_common_cmd()
Instead of having separate code in the 'ide' command, adjust it to use
the common function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 29 Jul 2017 17:34:56 +0000 (11:34 -0600)]
dm: scsi: Adjust the 'scsi' command to use blk_common_cmd()
Instead of having separate code in the 'scsi' command, adjust it to use
the common function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 29 Jul 2017 17:34:55 +0000 (11:34 -0600)]
dm: sata: Adjust the 'sata' command to use blk_common_cmd()
Instead of having separate code in the 'sata' command, adjust it to use
the common function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 29 Jul 2017 17:34:54 +0000 (11:34 -0600)]
dm: blk: Add a generic function for block device commands
Most block devices provide a command (e.g. 'sata', 'scsi', 'ide') and
these commands generally do the same thing. This makes it harder to
maintain this code and keep it consistent.
We now have a block device interface which is either implemented by driver
model (when CONFIG_BLK is enabled) or with a legacy interface. Therefore
it is possible to handle most of what these commands do with generic code.
Add a new generic function to process block-device commands using the
interface type and the current device number for that type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:34:53 +0000 (11:34 -0600)]
dm: blk: Add a function to find an interface-type name
Add a function to find the name of an interface type (e.g. "sata", "scsi")
from the interface type enum.
This is useful for generic code (not specific to SATA or SCSI, for
example) that wants to display the type of interface it is dealing with.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Jul 2017 17:34:52 +0000 (11:34 -0600)]
dm: core: Avoid calling dm_scan_fdt_dev() with of-platdata
We cannot call dm_scan_fdt_dev() with of-platdata since there is no device
tree. Fix this with an #if check.
Fixes: 3be9a37 (dm: syscon: scan sub-nodes of the syscon node)
Signed-off-by: Simon Glass <sjg@chromium.org>
Wenyou.Yang@microchip.com [Wed, 26 Jul 2017 06:35:42 +0000 (14:35 +0800)]
mmc: gen_atmel_mci: Fix wrong arguments used of bind()
The bind() method is called before the device is probed and so the
device has no private data, should use the platform data, and set up
a new struct to hold the mmc and cfg members.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Fri, 21 Jul 2017 21:22:56 +0000 (23:22 +0200)]
mmc: sd_sdhi: Enable clock using clock framework
Since we now have clock driver for the RCar Gen3 , add support for
enabling the clock into the SH SDHI driver to prevent hacks in the
board files.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 21 Jul 2017 21:22:55 +0000 (23:22 +0200)]
mmc: sh_sdhi: Fix the ACMD handling
The command handling in this driver is awful, esp. because the driver
depends on command numbers to determine whether this is APPCMD or not.
Also, handling of command RSP response types is totally wrong.
This patch at least plucks out some of the custom command encoding and
fixes the APPCMD handling. The RSP handling still needs work, yet that
might not be needed as it turns out the uniphier-sd.c driver is in much
better shape and supports the same IP, so we might be able to just drop
this driver in favor of the uniphier one.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 21 Jul 2017 21:22:54 +0000 (23:22 +0200)]
mmc: sh_sdhi: Add DM and DT probing support
Add MMC DM and DT probing support into the SH SDHI driver.
This patch abstracts out the common bits of the send command
and set ios functions, so they can be used both by DM and non
DM setups and adds the DM probe support.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 21 Jul 2017 21:11:59 +0000 (23:11 +0200)]
mmc: uniphier-sd: Fix long response processing
The long response entry 0..3 LSByte comes from the next response
register MSByte, not from the next response register LSByte. Fix
this to make the driver report correct values in response 136 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Tue, 15 Aug 2017 00:02:11 +0000 (20:02 -0400)]
Prepare v2017.09-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 14 Aug 2017 23:58:53 +0000 (19:58 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 14 Aug 2017 21:06:58 +0000 (17:06 -0400)]
Merge git://git.denx.de/u-boot-net
Sam Protsenko [Mon, 14 Aug 2017 17:22:17 +0000 (20:22 +0300)]
common: Move CONFIG_BOOTARGS to Kconfig
Also introduce CONFIG_USE_BOOTARGS option so we can control if
CONFIG_BOOTARGS defined at all.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
[trini: Resync r8a779[56]_ulcb, various ls10xx targets]
Signed-off-by: Tom Rini <trini@konsulko.com>
Prabhakar Kushwaha [Wed, 15 Feb 2017 15:26:03 +0000 (20:56 +0530)]
driver: net: ldpaa: Update priv->phydev after free()
Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Yuiko Oshino [Fri, 11 Aug 2017 16:44:58 +0000 (12:44 -0400)]
usb: net: Add support for Microchip LAN75xx and LAN78xx
Add support for Microchip LAN7500, LAN7800 and LAN7850,
USB to 10/100/1000 Ethernet Controllers.
Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Yuiko Oshino [Fri, 11 Aug 2017 16:44:57 +0000 (12:44 -0400)]
net: Add mii_resolve_flowctrl_fdx()
Add an mii helper function to resolve flow control status per
IEEE 802.3-2005 table 28B-3.
This function was taken from the Linux source tree.
Signed-off-by: Yuiko Oshino <yuiko.oshino@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Madalin Bucur [Fri, 4 Aug 2017 06:14:53 +0000 (09:14 +0300)]
net: fman: add support RGMII_TXID to memac
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 14 Aug 2017 17:21:44 +0000 (13:21 -0400)]
ARM: rockchip: rock: Correct test to use CONFIG_IS_ENABLED not defined
While it is likely that this entire case is superfluous and can be
removed, correct the test now to match what is in rockchip-common.h and
makes sense based on context of the code. Otherwise we get a large
number of warnings.
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 14 Aug 2017 14:40:01 +0000 (10:40 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Patrice Chotard [Wed, 9 Aug 2017 13:13:02 +0000 (15:13 +0200)]
stm32f1: remove stm32f1 support
A few years ago STM32F1 SoCs support has been added :
0144caf22ce6acd5c gpio: stm32: add stm32f1 support
2d18ef2364fd3561a ARMv7M: add STM32F1 support
But neither STM32F1 dedicated defconfig nor board was
associated to these commits.
Got confirmation from Tom Rini and Matt Porter to remove
all this code [1]
[1] http://u-boot.10912.n7.nabble.com/Remove-STM32F1-support-td301603.html
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Chris Packham [Mon, 7 Aug 2017 04:04:14 +0000 (16:04 +1200)]
cmd/bdinfo: correct comment in board_detail
This appears to be a simple typo that dates back to the original
implementation of board_detail in commit
e79394643b26 ("common: Update
cmd_bdinfo for PPC").
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Simon Glass [Sat, 5 Aug 2017 16:28:41 +0000 (10:28 -0600)]
test: Move the FIT test into the correct place
Move this test so that it will run when 'make tests' is used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 5 Aug 2017 16:28:40 +0000 (10:28 -0600)]
test: Convert the FIT test to test/py
Convert this test to use the pytest framework.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 5 Aug 2017 16:28:39 +0000 (10:28 -0600)]
test: Indent test-fit.py to match the next patch
We plan to rewrite this script to use the pytest framework. To make it
easier to review the changes, indent the code to match the next patch.
This gets all of the whitespace changes out of the way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Nishanth Menon [Sat, 5 Aug 2017 02:42:09 +0000 (21:42 -0500)]
ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices
OMAP5432 did go into production with AVS class0 registers which were
mutually exclusive from AVS Class 1.5 registers.
Most OMAP5-uEVM boards use the pre-production Class1.5 which has
production efuse registers set to 0. However on production devices,
these are set to valid data.
scale_vcore logic is already smart enough to detect this and use the
"Nominal voltage" on devices that do not have efuse registers populated.
On a test production device populated as follows:
MPU OPP_NOM:
=> md.l 0x04A0021C4 1
4a0021c4:
03a003e9 ....
(0x3e9 = 1.01v) vs nom voltage of 1.06v
MPU OPP_HIGH:
=> md.l 0x04A0021C8 1
4a0021c8:
03400485 ..@.
MM OPP_NOM:
=> md.l 0x04A0021A4 1
4a0021a4:
038003d4 ....
(0x3d4 = 980mV) vs nom voltage of 1.025v
MM OPP_OD:
=> md.l 0x04A0021A8 1
4a0021a8:
03600403 ..`.
CORE OPP_NOM:
=> md.l 0x04A0021D8 1
4a0021d8:
000003cf ....
(0x3cf = 975mV) vs nom voltage of 1.040v
Since the efuse values are'nt currently used, we do not regress on
existing pre-production samples (they continue to use nominal voltage).
But on boards that do have production samples populated, we can leverage
the optimal voltages necessary for proper operation.
Tested on:
a) 720-2644-001 OMAP5UEVM with production sample.
b) 750-2628-222(A) UEVM5432G-02 with pre-production sample.
Data based on OMAP5432 Technical reference Manual SWPU282AF (May
2012-Revised Aug 2016)
NOTE: All collaterals on OMAP5432 silicon itself seems to have been
removed from ti.com, though EVM details are still available:
http://www.ti.com/tool/OMAP5432-EVM
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Nishanth Menon [Sat, 5 Aug 2017 02:42:08 +0000 (21:42 -0500)]
ARM: OMAP5: Remove OPP_LOW Definitions for ES2.0
ES2.0 descopes OPP_LOW definition. So remove it from macros defined.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Simon Glass [Fri, 4 Aug 2017 22:20:16 +0000 (16:20 -0600)]
test: Fix FIT test to pass again
A recent change adjusted a test string so that the test no-longer passes.
Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Heiko Schocher <hs@denx.de>
Fixes:
b28c5fcc (test-fit.py: Minor grammar/spelling/clarification tweaks)
Andy Shevchenko [Fri, 4 Aug 2017 21:48:28 +0000 (15:48 -0600)]
wdt: Update uclass to make clear that the timeout is in ms
Convert name to show explicitly that we are using milliseconds. For a
watchdog timer this is precise enough.
No functional change intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Nobuhiro Iwamatsu [Fri, 4 Aug 2017 20:47:02 +0000 (05:47 +0900)]
boot_fit: Change return value from FDT_ERROR to -EINVAL in fdt_offset()
FDT_ERROR is defined as unsigned long. However, since the return value of
fdt_offset() is int, a warning will occur when compiling. Also, it is better
to use -EINVAL than FDT_ERROR.
This fixes this problem by change return value from FDT_ERROR to -EINVAL.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Franklin S Cooper Jr <fcooper@ti.com>
Bin Meng [Thu, 3 Aug 2017 09:31:03 +0000 (02:31 -0700)]
x86: qemu: Enable NVMe driver
QEMU supports NVMe emulation. Enable the NVMe driver on QEMU x86.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Bin Meng [Thu, 3 Aug 2017 09:31:02 +0000 (02:31 -0700)]
nvme: Handle zero Maximum Data Transfer Size (MDTS)
Maximum Data Transfer Size (MDTS) field indicates the maximum
data transfer size between the host and the controller. The
host should not submit a command that exceeds this transfer
size. The value is in units of the minimum memory page size
and is reported as a power of two (2^n).
The spec also says: a value of 0h indicates no restrictions
on transfer size. On the real NVMe card this is normally not
0 due to hardware restrictions, but with QEMU emulated NVMe
device it reports as 0. In nvme_blk_read/write() below we
have the following algorithm for maximum number of logic
blocks per transfer:
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
dev->max_transfer_shift being 0 will for sure cause lbas to
overflow. Let's use 20. With this fix, the NVMe driver works
on QEMU emulated NVMe device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Jon Nettleton [Thu, 3 Aug 2017 09:31:01 +0000 (02:31 -0700)]
nvme: Fix number of blocks detection
NVMe should use the nsze value from the queried device. This will
reflect the total number of blocks of the device and fix detecting
my Samsung 960 EVO 256GB.
Original:
Capacity: 40386.6 MB = 39.4 GB (
82711872 x 512)
Fixed:
Capacity: 238475.1 MB = 232.8 GB (
488397168 x 512)
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Jon Nettleton [Thu, 3 Aug 2017 09:31:00 +0000 (02:31 -0700)]
nvme: Detect devices that are class Storage Express
This adds support to detect the catchall PCI class for NVMe devices.
It allows the drivers to work with most NVMe devices that don't need
specific detection due to quirks etc.
Tested against a Samsung 960 EVO drive.
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Zhikang Zhang [Thu, 3 Aug 2017 09:30:59 +0000 (02:30 -0700)]
nvme: Add nvme commands
Add nvme commands in U-Boot command line.
1. "nvme scan" - scan NVMe blk devices
2. "nvme list" - show all available NVMe blk devices
3. "nvme info" - show current or a specific NVMe blk device
4. "nvme device" - show or set current device
5. "nvme part" - print partition table
6. "nvme read" - read data from NVMe blk device
7. "nvme write" - write data to NVMe blk device
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Zhikang Zhang [Thu, 3 Aug 2017 09:30:58 +0000 (02:30 -0700)]
nvme: Add show routine to print detailed information
This adds nvme_print_info() to show detailed NVMe controller and
namespace information.
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Zhikang Zhang [Thu, 3 Aug 2017 09:30:57 +0000 (02:30 -0700)]
nvme: Add NVM Express driver support
NVM Express (NVMe) is a register level interface that allows host
software to communicate with a non-volatile memory subsystem. This
interface is optimized for enterprise and client solid state drives,
typically attached to the PCI express interface.
This adds a U-Boot driver support of devices that follow the NVMe
standard [1] and supports basic read/write operations.
Tested with a 400GB Intel SSD 750 series NVMe card with controller
id 8086:0953.
[1] http://www.nvmexpress.org/resources/specifications/
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Zhikang Zhang [Thu, 3 Aug 2017 09:30:56 +0000 (02:30 -0700)]
dm: blk: part: Add UCLASS_NVME and IF_TYPE_NVME
This adds a new uclass id and block interface type for NVMe.
Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:54:56 +0000 (21:54 +0200)]
arm: mvebu: ddr3_debug: remove self assignments
Remove superfluous self assignements.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:51:05 +0000 (21:51 +0200)]
arm: mvebu: remove self assignment
Assigning dev_num to itself is superfluous.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:40:37 +0000 (21:40 +0200)]
tpm: add missing va_end
va_start must always be matched by va_end.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 19:30:55 +0000 (21:30 +0200)]
ARM: hisilicon: hikey: do not rely on random stack value
If CONFIG_MMC_DW is not defined the return value of
init_dwmmc should not rely on a random stack value.
Instead indicate that no error occured.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:46:05 +0000 (20:46 +0200)]
stm32: remove redundant 'else if'
The if in the else branch is superfluous.
We can use a simple if.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:40:43 +0000 (20:40 +0200)]
arm: mvebu: avoid possible NULL dereference
It does not make sense to check if info is NULL after
dereferencing it.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:34:20 +0000 (20:34 +0200)]
armv7m: mpu_config add missing break
For DEVICE_NON_SHARED the newly assigned value of attr
is overwritten due to a missing break.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:27:16 +0000 (20:27 +0200)]
bcm281xx: clock: avoid possible NULL dereference
It does not make sense first to dereference c and then
to check if it is NULL.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:22:47 +0000 (20:22 +0200)]
arm: bcm235xx: clk_set_rate avoid possible NULL deref
It does not make sense first to dereference c and then
to check if it is NULL.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:15:51 +0000 (20:15 +0200)]
arm: bcm235xx: avoid possible NULL dereference
It does not make sense to first dereference c and then
check if it is NULL.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 18:09:38 +0000 (20:09 +0200)]
arm: spear: do not return random value from stack
If the NOR device is not available do not return
a random value from the stack.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
xypron.glpk@gmx.de [Sun, 30 Jul 2017 17:54:37 +0000 (19:54 +0200)]
api: remove superfluous assignment
No need to assign a value to sig if the next statement using sig
is itself an assignment of a value to sig.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Thu, 27 Jul 2017 03:25:30 +0000 (22:25 -0500)]
Convert CONFIG_OMAP3_SPI to Kconfig
This converts the following to Kconfig:
CONFIG_OMAP3_SPI
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Minor comment tweaks]
Signed-off-by: Tom Rini <trini@konsulko.com>
Kever Yang [Thu, 27 Jul 2017 04:54:02 +0000 (12:54 +0800)]
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Thu, 27 Jul 2017 04:54:01 +0000 (12:54 +0800)]
rockchip: clk: update dwmmc clock div
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[fixup for 'missing DIV_ROUND_UP' conflict for clk_rk3288.c:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Thu, 27 Jul 2017 04:54:00 +0000 (12:54 +0800)]
rockchip: rk322x: update max-frequency for mmc node
mmc using
150000000 as max-frequency like what rk3288 sets.
This can speed up the mmc read/write, the actual mmc clock is:
Before this patch: 37.125M
After this patch: 49.5M
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Fri, 21 Jul 2017 10:21:09 +0000 (18:21 +0800)]
rockchip: dts: rk322x: add sdmmc device node
add node for sdmmc in dts and rk3229-evb.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Tue, 8 Aug 2017 13:26:12 +0000 (15:26 +0200)]
scripts: setlocalversion: safely extract variables from auto.conf using awk
Moving SPL_LDSCRIPT to Kconfig triggered an unfortunate attempt of
command substitution, as the sourced auto.conf may include $(ARCH)
which tries to execute a command 'ARCH'.
This showed up as a warning similar to the following:
include/config/auto.conf: line 209: ARCH: command not found
This change does no longer attempt to source auto.conf, but rather
passes it through awk to retrieve the values for CONFIG_LOCALVERSION
and CONFIG_LOCALVERSION_AUTO. This will also mitigate the risk of
unintended command substitution.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reported-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Kever Yang [Thu, 27 Jul 2017 04:53:59 +0000 (12:53 +0800)]
rockchip: rk322x: set the DDR region as non-secure in SPL
Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Mon, 31 Jul 2017 01:28:14 +0000 (09:28 +0800)]
rockchip: rk3288: fix EMMC_DIV_MASK definition in header
It should be '<<' instead of '<' for _MASK definition, fix it.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 4 Aug 2017 12:12:26 +0000 (14:12 +0200)]
rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig
With the new way of doing things (i.e. the hierarchical selection of
SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting
for the RK3368 from defconfig back into Kconfig.
With this done, there should be no lingering cases of SPL_LDSCRIPT
outside of Kconfig files.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 4 Aug 2017 12:01:32 +0000 (14:01 +0200)]
spl: moveconfig: remove SPL_LDSCRIPT definitions for header-files
With the hierarchical defaults set up, we remove these from the header
files. To do so, I've run moveconfig on SPL_LDSCRIPT and this commits
the changes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Thu, 3 Aug 2017 21:23:55 +0000 (23:23 +0200)]
spl: add hierarchical defaults for SPL_LDSCRIPT
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.
As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig. Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Thu, 3 Aug 2017 20:52:04 +0000 (22:52 +0200)]
rockchip: rk3188: rock: adjust for SPL/TPL split
With the changes to split SPL/TPL for the RK3368, I apparently missed
some needed adjustments to the RK3188 Kconfig and rock_defconfig.
This fixes build-issues for the rock board after applying the RK3368
enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT,
TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols
now.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Wed, 2 Aug 2017 13:10:56 +0000 (21:10 +0800)]
rockchip: remove the hard coded uart iomux setting for px5 evb
As the debug uart is marked as dm-pre-reloc, the pinctrl driver
will handle the correct iomux setting.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Yan [Wed, 2 Aug 2017 13:10:13 +0000 (21:10 +0800)]
rockchip: set Pre-reloc malloc pool size to 4kb for rk3368 based boards
The default 1kb pre-reloc malloc pool is not enough for dm
core to enable the dm-pre-reloc device drivers.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Andy Yan [Wed, 2 Aug 2017 13:08:59 +0000 (21:08 +0800)]
rockchip: add u-boot specific dts for rk3368 based boards
Device drivers like debug serial, dmc should be enabled before
relocation, so add u-boot.dtsi files to contain devices that
should be marked as dm-pre-reloc.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 16:01:49 +0000 (18:01 +0200)]
rockchip: rk3368: remove setup of secure timer from TPL/SPL
When using DM timers w/ the timer0 block within the RK3368, we no
longer depend on the ARMv8 generic timer counting. This allows us to
drop the secure timer initialisation from the TPL and SPL stages.
The secure timer will later be set up by ATF, which starts the ARMv8
generic timer. Thus, there will be a dependency from Linux to the ATF
through the ARMv8 generic timer... this seems reasonable, as Linux
will require the ATF (and PSCI) to start up the secondary cores anyway
(in other words: we don't add any new dependencies).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 16:00:27 +0000 (18:00 +0200)]
rockchip: lion-rk3368: defconfig: enable DM timer for all stages
There is no reasonably robust way (this will be needed so early that
diagnostics will be limited) to specify the base-address of the secure
timer through the DTS for TPL and SPL. In order to allow us a cleaner
way to structure our SPL and TPL stage, we now move to a DM timer
driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 15:46:39 +0000 (17:46 +0200)]
dts: rk3368: make timer0 accessible for SPL and TPL
To use it with the DM timer driver in SPL and TPL, timer0 needs to be
marked as pre-reloc.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 15:43:19 +0000 (17:43 +0200)]
rockchip: timer: add device-model timer driver for RK3368 (and similar)
This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.
This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 15:38:42 +0000 (17:38 +0200)]
dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
decision for each stage and under control of $(SPL_TPL_)TIMER
instead of having the two-level configuration with TIMER and
$(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 15:19:58 +0000 (17:19 +0200)]
timer: add OF_PLATDATA support for timer-uclass
The timer-uclass depends on full OF_CONTROL through its interrogation
of /chosen and the code to determine the clock-frequency.
For the OF_PLATDATA case, these code-paths are disabled and it becomes
the timer driver's responsibility to correctly set the clock-frequency
in the uclass priv-data.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 11 Aug 2017 18:35:30 +0000 (20:35 +0200)]
configs: mpc85xx: fix fallout from SPL/TPL changes
Splitting the feature selection for SPL and TPL, caused a few build
failures to mpx85xx boards. This fixes the fallout by adding the
needed new option names to the respective defconfig files.
Signed-off-byL Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Klaus Goger [Tue, 18 Jul 2017 19:41:28 +0000 (21:41 +0200)]
rockchip: board: puma_rk3399: rename ATF firmware
prefix the bl31 firmware needed to build uboot.itb so it can coexist in
the build area with ATFs from other boards (i.e. lion_rk3368)
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 5 May 2017 10:33:24 +0000 (12:33 +0200)]
rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its
The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /images/pmu@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /configurations/conf@1 has a unit name, but no reg property
This removes the @<num> part from the names, as we only have a single
image for each payload aspect (and only a single configuration) anyway.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 18:20:41 +0000 (20:20 +0200)]
moveconfig: migrate TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the
whitelist (this time it's really happening!) and migrate the setting
(only used on the RK3368-uQ7 so far) into Kconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 18:03:07 +0000 (20:03 +0200)]
rockchip: rk3368: mark TPL as not inheriting its stack, text-base and size from SPL
The RK3368 needs to have a different base-address and stack-pointer
for its TPL stage. Now that we want to do this via Kconfig, we need
to tick the appropriate 'TPL_NEEDS_...' boxes.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 18:04:09 +0000 (20:04 +0200)]
armv8: TPL_STACK will always be defined, so test CONFIG_TPL_NEEDS_SEPARATE_STACK
Now that TPL_STACK has been moved off the whitelist (ok, I'm lying:
the 'moving off the whitelist' part comes in once moveconfig
runs... which will be a few commits down the line) and added to
Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see
whether the value from TPL_STACK should be used or whether we try to
inherit whatever SPL uses.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 28 Jul 2017 18:02:34 +0000 (20:02 +0200)]
spl: support TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE via Kconfig
Let's clean up behind ourselves and move the (newly defined)
TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig. Given that
0x0 might be considered to be valid values for TPL_TEXT_BASE and
TPL_STACK, we need to introduce helper config options
("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used
(and not inherited from their SPL variants) for any given
target-platform.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 2 Aug 2017 19:26:18 +0000 (21:26 +0200)]
rockchip: Kconfig: preset TPL_LDSCRIPT via Kconfig for the RK3368
Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our
header file.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Fri, 28 Jul 2017 17:20:49 +0000 (19:20 +0200)]
spl: Kconfig: migrate $(SPL_TPL_)LDSCRIPT to Kconfig
Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and
have started to use the TPL-variant for the RK3368, it's time to clean
up behind ourselves: move both variants into Kconfig and remove them
from the whitelist.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 12 Jul 2017 23:36:39 +0000 (01:36 +0200)]
rockchip: board: lion-rk3368: add support for the RK3368-uQ7
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.
It provides the following features:
- 8x Cortex-A53 (in 2 clusters of 4 cores each)
- (on-module) up to 4GB of DDR3 memory
- (on-module) SPI-NOR flash
- (on-module) eMMC
- Gigabit Ethernet (with an on-module KSZ9031 PHY)
- USB
- HDMI
- MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
- various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 25 Jul 2017 14:25:30 +0000 (16:25 +0200)]
rockchip: spi: enable support for the rk_spi driver for the RK3368
For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.
Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Sun, 11 Jun 2017 21:46:25 +0000 (23:46 +0200)]
rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368. As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.
Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Mon, 12 Jun 2017 08:33:20 +0000 (10:33 +0200)]
rockchip: rk3368: spl: add SPL support
Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 19 Jul 2017 20:04:32 +0000 (22:04 +0200)]
rockchip: spl: make spl-boot-order code reusable (split from rk3399)
In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Tue, 4 Jul 2017 12:40:01 +0000 (14:40 +0200)]
rockchip: rk3368: spl: add TPL support
This adds the TPL support for the RK3368, including the u-boot-tpl.lds.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Fri, 14 Jul 2017 15:51:44 +0000 (17:51 +0200)]
rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
To build TPL and SPL stages for the RK3368, we will also need to
enable the SPL_FRAMEWORK.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>