Heinrich Schuchardt [Fri, 26 Jun 2020 17:57:55 +0000 (19:57 +0200)]
ARM: mx6: make CAAM usable on the i.MX6 boards
Even if the HAB fuse is not set we want to be able to use the Cryptographic
Accelerator and Assurance Module (CAAM) for generating random numbers. So
SYS_FSL_HAS_SEC should be selected even if IMX_HAB is not set.
arch_misc_init() has to be called to initialize the CAAM.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Fabio Estevam [Mon, 22 Jun 2020 00:32:26 +0000 (21:32 -0300)]
pico-imx6ul: Fix Quick Start Guide URL
The current URL for the pico imx6ul board is not valid anymore. Change
to a different URL that works.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Ye Li [Wed, 10 Jun 2020 03:29:51 +0000 (20:29 -0700)]
gpio: mxc_gpio: Improve to use ofdata_to_platdata
Current mxc_gpio DM driver allocates the platdata in bind function to
handle both OF_CONTROL enabled case and disabled case. This implementation
puts the devfdt_get_addr in bind, which introduces much overhead especially
in board_f phase.
Change the driver to a common way for handling the cases by using
ofdata_to_platdata and using DM framework to allocate platdata.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 9 Jun 2020 10:34:42 +0000 (03:34 -0700)]
misc: scu_api: Add SCFW API to get the index of boot container set
Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 9 Jun 2020 07:59:06 +0000 (00:59 -0700)]
spi: fsl_qspi: Support to use full AHB space on i.MX
i.MX platforms provide large AHB mapped space for QSPI, each
controller has 256MB. However, current driver only maps small
size (AHB buffer size) of AHB space, this implementation
causes i.MX failed to boot M4 with QSPI XIP image.
Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX)
to address above problem.
When the config is set:
1. Full AHB space is divided to each CS.
2. A dedicated LUT entry is used for AHB read only.
3. The MODE instruction in LUT is replaced to standard ADDR instruction
4. The address in spi_mem_op is used to SFAR and AHB read
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Ye Li [Tue, 9 Jun 2020 07:59:05 +0000 (00:59 -0700)]
spi: fsl_qspi: Add support for i.MX7ULP
Add compatible string and driver data for i.MX7ULP.
Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should
align with 1KB, because the lowest 10 bits are reserved by the
registers definition.
For i.MX7ULP which has only 128Bytes AHB buffer, must align it
when setting the registers and selecting cs.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Niel Fourie [Tue, 19 May 2020 12:01:43 +0000 (14:01 +0200)]
arm: imx6q: pcm058: Convert pcm058 to use DM with DTs
Convert pcm058 support to use device trees and the driver model.
Add rudimentary boot scripts to the environment, expand README.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Niel Fourie [Tue, 19 May 2020 12:01:42 +0000 (14:01 +0200)]
arm: imx6q: pcm058: change MAINTAINER
Change the MAINTAINER of pcm058.
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Niel Fourie [Tue, 19 May 2020 12:01:41 +0000 (14:01 +0200)]
arm: dts: imx6q: Add Linux dts files for Phytec Mira
Add Phytec Mira device tree files, for use with pcm058.
>From Linux 5.6, commit
7111951b8d49 upstream
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Niel Fourie [Tue, 19 May 2020 12:01:40 +0000 (14:01 +0200)]
dts-bindings: regulator: Add dlg,da9063-regulator
Add da9063-regulator bindings from Linux 5.6:
commit
7111951b8d49 upstream
Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Peng Fan [Fri, 10 Jul 2020 03:24:42 +0000 (11:24 +0800)]
imx8mm_evk: enlarge CONFIG_SYS_BOOTM_LEN
Enlarge CONFIG_SYS_BOOTM_LEN when booting FIT image with kernel.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Fri, 10 Jul 2020 03:22:20 +0000 (11:22 +0800)]
imx8m: implement armv8_el2_to_aarch32
Add iMX8M specific armv8_el2_to_aarch32 to let AArch64 mode U-Boot
could boot aarch32 mode linux with FIT image as below:
/dts-v1/;
/ {
description = "Configuration to load ARM32 Linux";
images {
kernel@1 {
description = "ARM32 Linux kernel";
data = /incbin/("./Image");
type = "kernel";
arch = "arm";
os = "linux";
compression = "none";
load = <0x40008000>;
entry = <0x40008000>;
hash@1 {
algo = "md5";
};
};
fdt@1 {
description = "Flattened Device Tree blob";
data = /incbin/("./imx8mm-evk.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
load = <0x43000000>;
hash@1 {
algo = "md5";
};
};
};
configurations {
default = "config@1";
config@1 {
description = "fsl-imx8mm-evk";
kernel = "kernel@1";
fdt = "fdt@1";
};
};
};
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 07:26:06 +0000 (15:26 +0800)]
imx8m: Refactor the OPTEE memory removal
Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.
When OPTEE memory is removed from first bank, it may split the first bank
to two banks, adjust the MMU table for the split case,
Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge
i.MX8MP evk to default to avoid issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 07:36:22 +0000 (15:36 +0800)]
clk: imx8m: drop clk settings
We use non-dm code to configure the clk settings in order to simplify
dm clk driver in future, so remove the duplicated code from clk driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 06:06:49 +0000 (14:06 +0800)]
imx8m: disable nodes before kernel/mfgtool boot for fused part
To fused part, we need to disable nodes of dtb to let kernel boot.
To mfgtool, USB issue when using super-speed for mfgtool, temporally
work around the problem to use high-speed only.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 15 Jul 2019 08:16:46 +0000 (01:16 -0700)]
imx8mn/imx8mp: override env_get_offset and env_get_location
To use one defconfig for all boot device, we have to runtime set
env offset and return env medium according to the boot device.
This patch overrides the env_get_offset and env_get_location to
implement the feature.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 05:52:41 +0000 (13:52 +0800)]
imx8m: power down fused cores
For non-Quad SoCs, the fused cpu cores could be powered down in SPL
to save power.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 21 Apr 2020 03:12:54 +0000 (20:12 -0700)]
imx8mp: Add fused parts support
iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.
The configuration tables for enabled modules:
MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA Quad Core, NPU, ISP
MIMX8ML6DVNLZAA Quad Core, VPU, ISP
MIMX8ML5DVNLZAA Quad Core, VPU
MIMX8ML4DVNLZAA Quad Lite
MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSP
Add the support in U-Boot
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 05:39:26 +0000 (13:39 +0800)]
imx8m: workaround ROM serror
ROM SError happens on two cases:
1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.
2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause
SError.
Since ROM mask SError until ATF unmask it, so then ATF always meets the
exception. This patch works around the issue in SPL by enabling SPL
Exception vectors table and the SError exception, take the exception
to eret immediately to clear the SError.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 05:14:20 +0000 (13:14 +0800)]
imx8m: add eqos clk
Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the
weak function in driver
Add set_clk_eqos to configure eQoS clk
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 03:35:15 +0000 (11:35 +0800)]
imx8m: add sdhc/nand/ecspi clk api
Current DM CLK is a bit complicated, for simplity, let DM clk only
support enable/disable/get_rate. For the expected rate settings,
we use non-DM clk to do that. Then we could have simple DM clk for
i.MX and could also share between SPL/U-Boot proper.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 03:18:50 +0000 (11:18 +0800)]
imx8m: configure NoC clk
Configure NoC clk for better system performance
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Thu, 9 Jul 2020 03:06:24 +0000 (11:06 +0800)]
imx8m: configure arm clk sources from PLL
A53 CCM root max support 1GHz, to support high freq, we need
to switch ARM clk sources from ARM PLL directly.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Wed, 22 Apr 2020 03:19:24 +0000 (20:19 -0700)]
clk: imx8mp: Update imx8mp ccf clock driver
Add clocks for FEC and flexspi, and add set parent clock callback,
so DTS can assign clocks
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sun, 19 Apr 2020 09:22:09 +0000 (02:22 -0700)]
clk: imx8mm/8mn: Add USB clocks
Add USB relevant clocks to support usb clock settings for both
DM USB host and gadget drivers
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Sat, 18 Apr 2020 15:19:12 +0000 (08:19 -0700)]
clk: clk-imx8mn: Update clock tree and support set parent
Add set clock parent support.
Add ENET and flexspi related clocks to support assigned clocks
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 27 Jun 2020 07:49:28 +0000 (15:49 +0800)]
clk: imx8mm: Add qspi clock
Add qspi clock
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 27 Jun 2020 07:48:04 +0000 (15:48 +0800)]
clk: imx8mm: fix clk set parent
Fix clk set parent, so we could still have correct clocks after
parent changing.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 11 May 2020 07:19:53 +0000 (15:19 +0800)]
imx: remove imx sip file
We have switch to use arm_smccc_smc, no need to keep i.MX specific
sip wrapper.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 11 May 2020 07:16:37 +0000 (15:16 +0800)]
imx: power-domain: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 11 May 2020 07:16:07 +0000 (15:16 +0800)]
imx8: fuse: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 11 May 2020 07:15:21 +0000 (15:15 +0800)]
imx: bootaux: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 11 May 2020 07:14:04 +0000 (15:14 +0800)]
imx8m: soc: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Mon, 11 May 2020 07:13:34 +0000 (15:13 +0800)]
imx8: misc: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 30 May 2020 08:43:20 +0000 (16:43 +0800)]
pinctrl: imx5: move soc info to data section
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 30 May 2020 08:39:14 +0000 (16:39 +0800)]
pinctrl: imx8m: move soc info to data section
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Sat, 30 May 2020 08:37:39 +0000 (16:37 +0800)]
pinctrl: imx7: move soc info to data section
The soc info without initialization value should be put into
data section. The driver could be used before relocation,
with it in BSS section could cause issue, since BSS section
is not initializated and it might overwrite other areas that
used by others, such as dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Oliver Chen [Tue, 21 Apr 2020 06:48:09 +0000 (14:48 +0800)]
drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue
Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jian Li [Thu, 27 Feb 2020 01:40:10 +0000 (09:40 +0800)]
imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit
In uMCTL2 Databook, for LPDDR4, it is recommended to set
this register to 1. This can avoid ddr bandwidth is lower
after booting with running for a while.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jian Li [Mon, 20 Jan 2020 07:14:42 +0000 (15:14 +0800)]
imx8mp: DDR performance tunning
1. set SCHED.rdwr_idle_gap=0
2. set SCHED.pageclose=1
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jian Li [Wed, 8 Jan 2020 02:14:16 +0000 (10:14 +0800)]
imx8mp: enable rd_port_urgent
Need to enable read urgent for NoC panic signal
Signed-off-by: Jian Li <jian.li@nxp.com
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sherry Sun [Mon, 20 Jan 2020 03:13:14 +0000 (11:13 +0800)]
drivers: ddr: imx8mp: Add inline ECC feature support
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jacky Bai [Mon, 10 Feb 2020 10:02:00 +0000 (18:02 +0800)]
driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m
The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.
Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Jacky Bai [Wed, 5 Jun 2019 03:26:12 +0000 (11:26 +0800)]
driver: ddr: imx: skip ddr_ss_gpr config on imx8mn
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Sat, 11 Jul 2020 21:40:00 +0000 (17:40 -0400)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- Enable DM_SPI on siemens omap boards (Jagan)
- Dropped some non-dm supported omap3 boards (Jagan)
- Dropped non-dm code in omap3 spi driver (Jagan)
- Dropped non-dm code in kirkwood spi driver (Bhargav)
Tom Rini [Sat, 11 Jul 2020 15:50:49 +0000 (11:50 -0400)]
Merge tag 'uniphier-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2020.10
- remove workaround for Cortex-A72
- increase U-Boot proper size to 2MB
- sync DT with Linux
- add system bus controller driver
- improve serial driver
- add reset assertion to Denali NAND driver
Masahiro Yamada [Fri, 10 Jul 2020 13:31:27 +0000 (22:31 +0900)]
ARM: uniphier: remove NAND reset code
Now that commit
3e57f879eee6 ("mtd: nand: raw: denali: Assert reset
before deassert") added the reset assertion, this code in the board
file is unneeded.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Ley Foon Tan [Fri, 10 Jul 2020 06:58:15 +0000 (14:58 +0800)]
mtd: nand: raw: denali: Wait for reset completion status
Fixed delay 200us is not working in certain platforms. Change to
poll for reset completion status to have more reliable reset process.
Controller will set the rst_comp bit in intr_status register after
controller has completed its reset and initialization process.
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Ley Foon Tan [Fri, 10 Jul 2020 06:58:14 +0000 (14:58 +0800)]
mtd: nand: raw: denali: Assert reset before deassert
Always put the controller in reset, then take it out of reset.
This is to make sure controller always in reset state in both SPL and
proper Uboot.
This is preparation for the next patch to poll for reset completion
(rst_comp) bit after reset.
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Radu Bacrau <radu.bacrau@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 16:12:08 +0000 (01:12 +0900)]
serial: uniphier: enable FIFO
This UART controller is integrated with a FIFO. Enable it.
You can put the next character into the FIFO while the transmitter
is sending out the current character. This works slightly faster.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 16:12:07 +0000 (01:12 +0900)]
serial: uniphier: flush transmitter before changing hardware settings
Ensure the transmitter is empty when chaining the baudrate or any
hardware settings. If a character is remaining in the transmitter,
the console will be garbled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 16:12:06 +0000 (01:12 +0900)]
serial: uniphier: use register macros instead of structure
After all, I am not a big fan of using a structure to represent the
hardware register map.
You do not need to know the entire register map.
Add only necessary register macros.
Use FIELD_PREP() instead of maintaining a pair of shift and mask.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:20 +0000 (15:08 +0900)]
ARM: uniphier: remove sbc/ directory
Now that this directory contains only uniphier_sbc_boot_is_swapped(),
move it to boot-device.c and delete the sbc/ directory entirely.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:19 +0000 (15:08 +0900)]
bus: uniphier-system-bus: move hardware init from board files
Move the bus initialization code to this driver from board files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:18 +0000 (15:08 +0900)]
bus: uniphier-system-bus: add UniPhier System Bus driver
Since commit
1517126fdac2 ("ARM: uniphier: select DM_ETH"), DM-based
drivers/net/smc911x.c is compiled, but it is never probed because the
parent node lacks the DM-based driver.
I need a skeleton driver to populate child devices (but the next commit
will move more hardware settings to the this driver).
I put this to drivers/bus/uniphier-system-bus.c because this is the
same path as the driver in Linux kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:17 +0000 (15:08 +0900)]
ARM: uniphier: remove support for NOR Flash on support card
I actually do not see this used these days because eMMC or NAND is used
for non-volatile devices. Dump the burden to maintain this crappy code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:16 +0000 (15:08 +0900)]
ARM: uniphier: remove unused uniphier_sbc_init_admulti()
This was used by the old sLD3 SoC, the support of which was removed
by commit
00aa453ebf56 ("ARM: uniphier: remove sLD3 SoC support").
There is no more user of this function.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:15 +0000 (15:08 +0900)]
ARM: uniphier: fix build error when CONFIG_MICRO_SUPPORT_CARD=n
If CONFIG_MICRO_SUPPORT_CARD is unset, the build fails due to
function redefinition.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:14 +0000 (15:08 +0900)]
ARM: uniphier: sync with Linux 5.8-rc4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:13 +0000 (15:08 +0900)]
ARM: uniphier: consolidate SoC select menu
Currently, the supports for the following two ARMv7 SoC groups
are exclusive, because the boot ROM loads the SPL to a different
address:
- LD4, sLD8 (SPL is loaded at 0x00040000)
- Pro4, Pro5, PXs2, LD6b (SPL is loaded at 0x00100000)
This limitation exists only when CONFIG_SPL=y.
Instead of using crappy CONFIG options, checking SPL and SPL_TEXT_BASE
is cleaner.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:12 +0000 (15:08 +0900)]
ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN to 2MB
I increased the maximum U-Boot proper size from time to time, but
configs/uniphier_v7_defconfig hit the current limit 832KB.
Some historical info:
In the initial support, the max size was 512MB.
Commit
58d702274c09 ("ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN")
increased it to 576KB, and commit
3ce5b1a8d86d ("ARM: uniphier: move
SPL stack address") moved the SPL stack location to avoid the memory
map conflict. It was the solution to increase the size without changing
the NOR boot image map.
commit
1a4bd3a095b2 ("ARM: uniphier: increase CONFIG_SYS_MONITOR_LEN
again") ended up with increasing the max size again, breaking the NOR
boot image map. The limit was set to 832KB, otherwise the SPL stack
would overwrite the U-Boot proper image:
CONFIG_SPL_STACK - CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header) = 0xd0000
To increase CONFIG_SYS_MONITOR_LEN even more, the SPL stack must be
moved somewhere. I put it back to the original location prior to
commit
3ce5b1a8d86d.
With this change, there is no more practical size limit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Thu, 9 Jul 2020 06:08:11 +0000 (15:08 +0900)]
Revert "ARM: uniphier: add weird workaround code for LD20"
This reverts commit
45f41c134baf5ff1bbf59d33027f6c79884fa4d9.
This weird workaround was the best I came up with at that time
to boot U-Boot from TF-A.
I noticed U-Boot successfully boots on LD20 (i.e. CA72 CPU) by using
the latest TF-A.
Specifically, since the following TF-A commit, U-Boot runs at EL2
instead of EL1, and this issue went away as a side-effect.
|commit
f998a052fd94ea082833109f25b94ed5bfa24e8b
|Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|Date: Thu Jul 25 10:57:38 2019 +0900
|
| uniphier: run BL33 at EL2
|
| All the SoCs in 64-bit UniPhier SoC family support EL2.
|
| Just hard-code MODE_EL2 instead of using el_implemented() helper.
|
| Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0
| Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
However, if I reverted that, this problem would come back, presumably
because some EL1 code in U-Boot triggers this issue.
Now that commit
f8ddd8cbb513 ("arm64: issue ISB after updating system
registers") fixed this issue properly, this weird workaround is no
longer needed irrespective of the exception level at which U-Boot runs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Fri, 10 Jul 2020 20:22:57 +0000 (16:22 -0400)]
Merge tag 'dm-pull-10jul20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
of-platdata: better phandle and compatible-string support
patman support for Python3 on Ubuntu 14.04
new checkpatch check to avoid #ifdefs
Heinrich Schuchardt [Fri, 10 Jul 2020 20:04:40 +0000 (22:04 +0200)]
CI: show skipped Python tests
Call pytest3 with argument -ra to display the reason why Python tests are
skipped.
The -r flag displays a test summary info for each test. -ra eliminates
this info for passed tests.
Pros an cons were discussed in:
https://lists.denx.de/pipermail/u-boot/2020-June/417090.html
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 10 Jul 2020 18:31:22 +0000 (14:31 -0400)]
Merge tag 'rpi-next-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi
- add support for PCI and XHCI for RPi4 (64 bit only)
- optionally reset XHCI device on registration
- enable USB_KEYBOARD for rpi_4_defconfig
Tom Rini [Fri, 10 Jul 2020 18:30:46 +0000 (14:30 -0400)]
Merge branch '2020-08-10-arbitrary-virt-phys-mappings'
- Bring in Marek Szyprowski's series to allow for arbitrary
virtual-physical address mappings.
Marek Szyprowski [Wed, 3 Jun 2020 12:43:45 +0000 (14:43 +0200)]
config: Enable support for the XHCI controller on RPI4 board
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Marek Szyprowski [Wed, 3 Jun 2020 12:43:44 +0000 (14:43 +0200)]
rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Seung-Woo Kim [Wed, 3 Jun 2020 12:43:43 +0000 (14:43 +0200)]
mmc: bcm283x: fix int to pointer cast
On build with 32 bit, there is a warning for int-to-pointer-cast.
Fix the int to pointer cast by using uintptr_t.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Marek Szyprowski [Wed, 3 Jun 2020 12:43:42 +0000 (14:43 +0200)]
arm: provide a function for boards init code to modify MMU virtual-physical map
Provide function for setting arbitrary virtual-physical MMU mapping
and cache settings for the given region.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Szyprowski [Wed, 3 Jun 2020 12:43:41 +0000 (14:43 +0200)]
arm: update comments to the common style
Update the comments in include/asm/system.h to the common style.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Marek Szyprowski [Wed, 3 Jun 2020 12:43:40 +0000 (14:43 +0200)]
powerpc: move ADDR_MAP to Kconfig
Move ADDR_MAP related config options from include/configs/*.h to the
proper place in lib/Kconfig. This has been done using
./tools/moveconfig.py and manual inspection of the generated changes.
This is a preparation to use ADDR_MAP helper on ARM 32bit Raspberry Pi4
board for mapping the PCIe XHCI MMIO, which is above the 4GiB identity
mapping limit.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Nicolas Saenz Julienne [Tue, 5 May 2020 14:51:29 +0000 (16:51 +0200)]
config: Enable USB Keyboard support on RPi4
Supporting USB keyboards out of the box is both handy for development
and production. Notably if u-boot is used to boot into GRUB.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[mb: drop rpi_4_32b_defconfig hunk]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Nicolas Saenz Julienne [Mon, 29 Jun 2020 16:37:25 +0000 (18:37 +0200)]
usb: xhci: Add reset controller support
Some atypical users of xhci might need to manually reset their xHCI
controller before starting the HCD setup. Check if a reset controller
device is available to the PCI bus and trigger a reset.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
[mb: squash fix to only build xhci_reset_hw() if CONFIG_DM_BUS]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Nicolas Saenz Julienne [Mon, 29 Jun 2020 16:37:24 +0000 (18:37 +0200)]
configs: Enable support for reset controllers on RPi4
This is required in order to access the reset controller used to
initialize the board's xHCI chip.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Nicolas Saenz Julienne [Mon, 29 Jun 2020 16:37:23 +0000 (18:37 +0200)]
reset: Add Raspberry Pi 4 firmware reset controller
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. Introduce a reset controller capable of interfacing with
RPi4's co-processor that models these firmware initialization routines as
reset lines.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Nicolas Saenz Julienne [Mon, 29 Jun 2020 16:37:22 +0000 (18:37 +0200)]
arm: rpi: Add function to trigger VL805's firmware load
On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
may either be loaded directly from an EEPROM or, if not present, by the
SoC's VideCore (the SoC's co-processor). Introduce the function that
informs VideCore that VL805 may need its firmware loaded.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Marek Szyprowski [Mon, 25 May 2020 11:39:59 +0000 (13:39 +0200)]
configs: Enable support for the XHCI controller on RPI4 board (ARM 64-bit)
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is already configured to get this feature working out of the box.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Sylwester Nawrocki [Mon, 25 May 2020 11:39:58 +0000 (13:39 +0200)]
pci: Add driver for Broadcom BCM2711 SoC PCIe controller
This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is used.
The patch has been tested on RPI4 board, i.e. on BCM2711 SoC with VL805
USB Host Controller.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Sylwester Nawrocki [Mon, 25 May 2020 11:39:57 +0000 (13:39 +0200)]
pci: Add some PCI Express capability register offset definitions
Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Nicolas Saenz Julienne [Mon, 25 May 2020 11:39:56 +0000 (13:39 +0200)]
linux/bitfield.h: Add primitives for manipulating bitfields both in host- and fixed-endian
Imports Al Viro's original Linux commit
00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
37a3862e12382 "bitfield: add u8 helpers".
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
[s.nawrocki: added empty lines between functions and macros]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[mb: squash fix including byteorder.h]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Jagan Teki [Thu, 9 Jul 2020 15:53:58 +0000 (21:23 +0530)]
doc: driver-model: Update SPI migration status
All SPI drivers are converted to DM_SPI but 3 drivers
still operate in nondm mode for SPL due to footprint
constraints.
Update the migration status for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Bhargav Shah [Thu, 18 Jun 2020 17:45:13 +0000 (23:15 +0530)]
spi: kirkwood: Drop nondm code
Drop the nondm code from kirkwood_spi.c since there
is no board or any other code using for it.
Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Walter Lozano [Thu, 25 Jun 2020 04:10:17 +0000 (01:10 -0300)]
dtoc: add test for cd-gpios
Add a test for dtoc taking into account the cd-gpios property.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:16 +0000 (01:10 -0300)]
dtoc: update dtb_platdata to support cd-gpios
Currently dtoc does not support the property cd-gpios used to declare
the gpios for card detect in mmc.
This patch adds support to cd-gpios property.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:15 +0000 (01:10 -0300)]
arm: dts: include gpio nodes for card detect
Several MMC drivers use GPIO for card detection with cd-gpios property in
the MMC node pointing to a GPIO node. However, as U-Boot tries to save
space by keeping only required nodes using u-boot* properties, several
devices tree result in having only in the MMC node but not the GPIO node
associated to cd-gpios.
This patch, fixes several ocurrence of this issue.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
Walter Lozano [Thu, 25 Jun 2020 04:10:14 +0000 (01:10 -0300)]
dm: doc: update of-plat with new phandle support
Update documentation to reflect the new phandle support when OF_PLATDATA
is used. Now phandles are implemented as pointers to U_BOOT_DEVICE,
which makes it possible to get a pointer to the actual device.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:13 +0000 (01:10 -0300)]
dtoc: extend dtoc to use struct driver_info when linking nodes
In the current implementation, when dtoc parses a dtb to generate a struct
platdata it converts the information related to linked nodes as pointers
to struct platdata of destination nodes. By doing this, it makes
difficult to get pointer to udevices created based on these
information.
This patch extends dtoc to use struct driver_info when populating
information about linked nodes, which makes it easier to later get
the devices created. In this context, reimplement functions like
clk_get_by_index_platdata() which made use of the previous approach.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:12 +0000 (01:10 -0300)]
sandbox: Move section u_boot_list to make it RW
In order to be able to update data in u_boot_list, move this section to
make it RW.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:11 +0000 (01:10 -0300)]
core: extend struct driver_info to point to device
Currently when creating an U_BOOT_DEVICE entry a struct driver_info
is declared, which contains the data needed to instantiate the device.
However, the actual device is created at runtime and there is no proper
way to get the device based on its struct driver_info.
This patch extends struct driver_info adding a pointer to udevice which
is populated during the bind process, allowing to generate a set of
functions to get the device based on its struct driver_info.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:10 +0000 (01:10 -0300)]
core: drop const for struct driver_info
In order to prepare for a new support of phandle when OF_PLATDATA is used
drop the const for struct driver_info as this struct will need to be
updated on runtime.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:09 +0000 (01:10 -0300)]
dm: doc: update of-plat with the support for driver aliases
Update the documentation with the support for driver aliases using
U_BOOT_DRIVER_ALIAS.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:08 +0000 (01:10 -0300)]
dtoc: add option to disable warnings
As dtoc now performs checks for valid driver names, when running dtoc
tests several warnings arise as these tests don't use valid driver
names.
This patch adds an option to disable those warning, which is only
intended for running tests.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Fri, 3 Jul 2020 11:07:17 +0000 (08:07 -0300)]
dtoc: add support to scan drivers
Currently dtoc scans dtbs to convert them to struct platdata and
to generate U_BOOT_DEVICE entries. These entries need to be filled
with the driver name, but at this moment the information used is the
compatible name present in the dtb. This causes that only nodes with
a compatible name that matches a driver name generate a working
entry.
In order to improve this behaviour, this patch adds to dtoc the
capability of scan drivers source code to generate a list of valid driver
names and aliases. This allows to generate U_BOOT_DEVICE entries using
valid driver names and rise a warning in the case a name is not valid.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Open files in utf-8 mode:
Signed-off-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:06 +0000 (01:10 -0300)]
core: add support for U_BOOT_DRIVER_ALIAS
Currently when using OF_PLATDATA the binding between devices and drivers
is done trying to match the compatible string in the node with a driver
name. However, usually a single driver supports multiple compatible strings
which causes that only devices which its compatible string matches a
driver name get bound.
To overcome this issue, this patch adds the U_BOOT_DRIVER_ALIAS macro,
which generates no code at all, but allows an easy way to declare driver
name aliases. Thanks to this, dtoc could be improve to look for the driver
name based on its alias when it populates the U_BOOT_DEVICE entry.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:05 +0000 (01:10 -0300)]
dtoc: add missing code comments
Add missing information about internal class members in order to make
the code easier to follow.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Walter Lozano [Thu, 25 Jun 2020 04:10:04 +0000 (01:10 -0300)]
drivers: rename drivers to match compatible string
When using OF_PLATDATA, the bind process between devices and drivers
is performed trying to match compatible string with driver names.
However driver names are not strictly defined, and also there are different
names used when declaring a driver with U_BOOT_DRIVER, the name of the
symbol used in the linker list and the used in the struct driver_info.
In order to make things a bit more clear, rename the drivers names. This
will also help for further OF_PLATDATA improvements, such as checking
for valid driver names.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour:
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2020 05:55:49 +0000 (22:55 -0700)]
test/dm: fdtdec: Add tests for fdtdec_add_reserved_memory()
This adds a test case to test the functionality of the fdtdec API
fdtdec_add_reserved_memory().
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2020 05:55:48 +0000 (22:55 -0700)]
test/dm: fdtdec: Corect a typo in dm_test_fdtdec_set_carveout()
It should be "writable".
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2020 05:55:47 +0000 (22:55 -0700)]
test/dm: fdtdec: Add the missing gd declaration
Add DECLARE_GLOBAL_DATA_PTR since it is referenced in the test codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Simon Glass <sjg@chromium.org>