Alex Smith [Wed, 6 Dec 2017 10:28:14 +0000 (10:28 +0000)]
radv: Add LLVM version to the device name string
Allows apps to determine the LLVM version so that they can decide
whether or not to enable workarounds for LLVM issues.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Alejandro Piñeiro [Wed, 6 Dec 2017 10:38:59 +0000 (11:38 +0100)]
mesa: remove set_entry from forward type declarations
This type was used at gl_sync_object, but it is not used anymore.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Kenneth Graunke [Tue, 21 Mar 2017 07:30:06 +0000 (00:30 -0700)]
meta: Fix ClearTexture with GL_DEPTH_COMPONENT.
We only handled unpacking for GL_DEPTH_STENCIL formats.
Cemu was hitting _mesa_problem() for an unsupported format in
_mesa_unpack_float_32_uint_24_8_depth_stencil_row(), because the
format was depth-only, rather than depth-stencil.
Cc: "13.0 12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94739
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103966
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Kenneth Graunke [Tue, 5 Dec 2017 19:09:13 +0000 (11:09 -0800)]
meta: Initialize depth/clear values on declaration.
This helps avoid compiler warningss in the next commit - everything
was initialized, but it wasn't obvious to static analysis.
Suggested-by: Tapani Pälli <tapani.palli@intel.com>
Timothy Arceri [Wed, 6 Dec 2017 23:16:55 +0000 (10:16 +1100)]
glsl: get correct member type when processing xfb ifc arrays
This fixes a crash in:
KHR-GL45.enhanced_layouts.xfb_block_stride
Fixes:
0822517936d4 "glsl: add helper to process xfb qualifiers during linking"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Gert Wollny [Wed, 6 Dec 2017 16:42:02 +0000 (17:42 +0100)]
r600/sb: do not convert if-blocks that contain indirect array access
If an array is accessed within an if block, then currently it is not known
whether the value in the address register is involved in the evaluation of the
if condition, and converting the if condition may actually result in
out-of-bounds array access. Consequently, if blocks that contain indirect array
access should not be converted.
Fixes piglits on r600/BARTS:
spec/glsl-1.10/execution/variable-indexing/
vs-output-array-float-index-wr
vs-output-array-vec3-index-wr
vs-output-array-vec4-index-wr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104143
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 28 Nov 2017 02:53:02 +0000 (12:53 +1000)]
r600: add support for compute grid/block sizes. (v2)
We just pass these in from outside in a constant buffer.
The shader side stores them once they are accessed once.
v2: fix to not use a temp_reg.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 27 Nov 2017 06:12:18 +0000 (16:12 +1000)]
r600: handle image/buffer sizes correctly.
This adds support to compute for the resq workarounds (buffer/cube sizes)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:47:55 +0000 (11:47 +1000)]
r600/compute: add support for emitting compute image/buffer atoms
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:47:31 +0000 (11:47 +1000)]
r600/compute: handle atomic counters in compute state.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:44:06 +0000 (11:44 +1000)]
r600/compute: add support for TGSI compute shaders. (v1.1)
This add paths to handle TGSI compute shaders and shader selection.
It also avoids emitting certain things on tgsi paths,
CBs, vertex buffers, config reg init (not required).
v1.1: fix rat mask calc
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:15:26 +0000 (11:15 +1000)]
r600/shader: add compute support to shader assembler
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:35:03 +0000 (11:35 +1000)]
r600/texture: drop lowering 1d/2d images to linear.
This appears to cause hangs with compute images. Unless
we can find more specifics, just don't do this for now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Alejandro Piñeiro [Wed, 6 Dec 2017 08:57:18 +0000 (09:57 +0100)]
mesa: define nir_spirv_supported_capabilities
Until now it was part of spirv_to_nir_options. But it will be used on
the implementation of ARB_gl_spirv and ARB_spirv_extensions, and added
to the OpenGL context, as a way to save what SPIR-V capabilities the
current OpenGL implementation supports.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fredrik Höglund [Tue, 5 Dec 2017 20:19:51 +0000 (21:19 +0100)]
anv: fix a case statement in GetMemoryFdPropertiesKHR
The handle type in the case statement is supposed to be VK_EXTERNAL_-
MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT.
Fixes:
ab18e8e59b6 ("anv: Implement VK_EXT_external_memory_dma_buf")
Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fredrik Höglund [Tue, 5 Dec 2017 20:15:25 +0000 (21:15 +0100)]
radv: fix a case statement in GetMemoryFdPropertiesKHR
The handle type in the case statement is supposed to be VK_EXTERNAL_-
MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT.
Fixes:
546e747867c ("radv: Implement VK_EXT_external_memory_dma_buf")
Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Eric Engestrom [Wed, 6 Dec 2017 13:27:52 +0000 (13:27 +0000)]
meson: fix keyword argument in declare_dependency()
`declare_dependency()` takes `compile_args`, not `c_args`.
It was correct in all the other `declare_dependency()` from that commit.
Fixes:
0bbecc5a8548883f76a71 "meson: define driver dependencies"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Emil Velikov [Wed, 6 Dec 2017 17:33:00 +0000 (17:33 +0000)]
i965: include brw_pipe_control.h in the tarball
Fixes:
bfe0f3a7027 ("i965: Move PIPE_CONTROL defines and prototypes to
brw_pipe_control.h.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 16 Nov 2017 14:22:18 +0000 (14:22 +0000)]
mesa: document _mesa_extension_override_* variables
Currently there are no users of these outside of extensions.c.
Provide some information why they exist and how to use them.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
Emil Velikov [Thu, 23 Nov 2017 16:56:44 +0000 (16:56 +0000)]
docs: annotate MESA_program_debug as obsolete
It has been obsolete for years - state it explicitly.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
George Kyriazis [Tue, 5 Dec 2017 16:47:12 +0000 (10:47 -0600)]
swr/scons: Fix another intermittent build failure
gen_BackendPixelRate*.cpp depends on gen_ar_eventhandler.hpp.
Fix missing dependency.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Marek Olšák [Fri, 1 Dec 2017 02:08:16 +0000 (03:08 +0100)]
radeonsi: make const and stream uploaders allocate read-only memory
and anything that clones these uploaders, like u_threaded_context.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Dec 2017 19:04:11 +0000 (20:04 +0100)]
radeonsi: use a separate allocator for fine fences
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Dec 2017 12:32:47 +0000 (13:32 +0100)]
radeonsi/gfx9: make shader binaries use read-only memory
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 5 Dec 2017 12:32:33 +0000 (13:32 +0100)]
winsys/amdgpu: make IBs use read-only memory
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 4 Dec 2017 22:02:54 +0000 (23:02 +0100)]
radeonsi: print the buffer list for CHECK_VM
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 21:49:10 +0000 (22:49 +0100)]
radeonsi: allow DMABUF exports for local buffers
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 23 Nov 2017 09:29:49 +0000 (10:29 +0100)]
radeonsi: always place sparse buffers in VRAM
Together with "radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check",
this ensures that sparse buffers are placed in VRAM.
Noticed by an assertion that started triggering with commit
d4fac1e1d7
("gallium/radeon: enable suballocations for VRAM with no CPU access")
Fixes KHR-GL45.sparse_buffer_tests.BufferStorageTest in debug builds.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Nicolai Hähnle [Thu, 23 Nov 2017 09:25:34 +0000 (10:25 +0100)]
radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check
The flag is on the pipe_resource, not the r600_resource.
I don't see an obvious bug related to this, but it could potentially lead
to suboptimal placement of some resources.
Fixes:
a41587433c4d ("gallium/radeon: add R600_RESOURCE_FLAG_UNMAPPABLE")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Jose Maria Casanova Crespo [Mon, 24 Jul 2017 20:42:59 +0000 (22:42 +0200)]
i965/fs: Use untyped_surface_read for 16-bit load_ssbo
SSBO loads were using byte_scattered read messages as they allow
reading 16-bit size components. byte_scattered messages can only
operate one component at a time so we needed to emit as many messages
as components.
But for vec2 and vec4 of 16-bit, being multiple of 32-bit we can use the
untyped_surface_read message to read pairs of 16-bit components using only
one message. Once each pair is read it is unshuffled to return the proper
16-bit components. vec3 case is assimilated to vec4 but the 4th component
is ignored.
16-bit scalars are read using one byte_scattered_read message.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Rework optimization using unshuffle 16 reads (Chema Casanova)
v3: Use W and D types insead of HF and F in shuffle to avoid rounding
erros (Jason Ekstrand)
Use untyped_surface_read for 16-bit vec3. (Jason Ekstrand)
v4: Use subscript insead of chaging type and stride (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Wed, 12 Jul 2017 12:49:41 +0000 (14:49 +0200)]
i965/fs: Optimize 16-bit SSBO stores by packing two into a 32-bit reg
Currently, we use byte-scattered write messages for storing 16-bit
into an SSBO. This is because untyped surface messages have a fixed
32-bit size.
This patch optimizes these 16-bit writes by combining 2 values (e.g,
two consecutive components aligned with 32-bits) into a 32-bit register,
packing the two 16-bit words.
16-bit single component values will continue to use byte-scattered
write messages. The same will happens when the first consecutive
component is not aligned 32-bits.
This optimization reduces the number of SEND messages used for storing
16-bit values potentially by 2 or 4, which cuts down execution time
significantly because byte-scattered writes are an expensive
operation as they only write a component for message.
v2: Removed use of stride = 2 on sources (Jason Ekstrand)
Rework optimization using shuffle 16 write and enable writes
of 16bit vec4 with only one message of 32-bits. (Chema Casanova)
v3: - Fix coding style (Eduardo Lima)
- Reorganize code to avoid duplication. (Jason Ekstrand)
- Include new comments to explain the length calculations to
fix alignment issues of components. (Jason Ekstrand)
- Fix issues with writemask yz with 16-bit writes. (Jason Ektrand)
v4: (Jason Ekstrand)
- Reorganize 64-bit ssbo-writes to avoid using slots_per_component.
- Comment about why suffle is needed when using byte_scattered_write.
Signed-off-by: Eduardo Lima <elima@igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:32:17 +0000 (08:32 +0200)]
anv: Enable SPV_KHR_16bit_storage and VK_KHR_16bit_storage for SSBO/UBO
Enables SPV_KHR_16bit_storage on gen 8+.
VK_KHR_16bit_storage is enabled for SSBO/UBO using the
VK_KHR_get_physical_device_properties2 functionality to expose
if the extension is supported or not.
v2: update due rebase against master (Alejandro)
v3: (Jason Ekstrand)
- Move this patch up in VK_KHR_16bit_storage series enabling only
storageBuffer16BitAccess and uniformAndStorageBuffer16BitAccess.
- Only expose VK_KHR_16bit_storage on Gen8+
v4: (Jason Ekstrand)
- Squash enable SPV_KHR_16bit_storage into VK_KHR_16bit_storage
enablement for SSBO/UBO.
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Mon, 20 Nov 2017 23:03:46 +0000 (00:03 +0100)]
i965/fs: Enables 16-bit load_ubo with sampler
load_ubo is using 32-bit loads as uniforms surfaces have a 32-bit
surface format defined. So when reading 16-bit components with the
sampler we need to unshuffle two 16-bit components from each 32-bit
component.
Using the sampler avoids the use of the byte_scattered_read message
that needs one message for each component and is supposed to be
slower.
v2: (Jason Ekstrand)
- Simplify component selection and unshuffling for different bitsizes
- Remove SKL optimization of reading only two 32-bit components when
reading 16-bits types.
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Jose Maria Casanova Crespo [Mon, 20 Nov 2017 22:10:51 +0000 (23:10 +0100)]
i965/fs: Helpers for un/shuffle 16-bit pairs in 32-bit components
This helpers are used to load/store 16-bit types from/to 32-bit
components.
The functions shuffle_32bit_load_result_to_16bit_data and
shuffle_16bit_data_for_32bit_write are implemented in a similar
way than the analogous functions for handling 64-bit types.
v1: Explain need of temporary in shuffle operations. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:20:07 +0000 (08:20 +0200)]
i965/fs: Use byte scattered read for 16-bit load_ssbo
Used to enable 16-bit reads at do_untyped_vector_read, that is used on
the following intrinsics:
* nir_intrinsic_load_shared
* nir_intrinsic_load_ssbo
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: - Add bitsize to scattered read operation (Jason Ekstrand)
- Remove implementation of 16-bit UBO read from this patch.
- Avoid assertion at opt_algebraic caused by ADD of two IMM with
offset with BRW_REGISTER_TYPE_UD type found on matrix tests.
(Jose Maria Casanova)
v4: (Jason Ekstrand)
- Put if case for 16-bits at the beginning of the if ladder.
- Use type_sz(dest.type) * 8 as bit_size parameter for scattered read.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:19:17 +0000 (08:19 +0200)]
i965/fs: Add byte scattered read message and fs support
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_read.
v3: (Jason Ekstrand)
- Use renamed brw_byte_scattered_data_element_from_bit_size method
- Assert scattered read for Gen8+ and Haswell.
- Use conditional expresion at components_read.
- Include comment about params for scattered opcodes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 29 Jul 2017 14:10:02 +0000 (16:10 +0200)]
i965/fs: Predicate byte scattered writes if needed
While on Untyped Surface messages the bits of the execution mask are
ANDed with the corresponding bits of the Pixel/Sample Mask, that is
not the case for byte scattered writes. That is needed to avoid ssbo
stores writing on helper invocations. So when that can affect, we load
the sample mask, and predicate the send message.
Note: the need for this patch was tested with a custom test. Right now
the 16 bit storage CTS tests doesnt need this path in order to get a
full pass.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:17:09 +0000 (08:17 +0200)]
i965/fs: Use byte_scattered_write on 16-bit store_ssbo
We need to rely on byte scattered writes as untyped writes are 32-bit
size. We could try to keep using 32-bit messages when we have two or
four 16-bit elements, but for simplicity sake, we use the same message
for any component number. We revisit this aproach in the follwing
patches.
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: (Jason Ekstrand)
- Include bit_size to scattered write message and remove namespace
- specific for scattered messages.
- Move comment to proper place.
- Squashed with i965/fs: Adjust type_size/type_slots on store_ssbo.
(Jose Maria Casanova)
- Take into account that get_nir_src returns now WORD types for
16-bit sources instead of DWORD.
v4: (Jason Ekstrand)
- Rename lenght variable to num_components.
- Include assertions before emit_untyped_write.
- Remove type_slot in favor of num_slot and first_slot.
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:16:01 +0000 (08:16 +0200)]
i965/fs: Add byte scattered write message and fs support
v2: (Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_write.
v3: - Remove leftover newline (Topi Pohjolainen)
- Rename brw_data_size to brw_scattered_data_element and use
defines instead of an enum (Jason Ekstrand)
- Assert scattered write for Gen8+ and Haswell (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:14:56 +0000 (08:14 +0200)]
i965/fs: Add remove_extra_rounding_modes optimization
Although from SPIR-V point of view, rounding modes are attached to the
operation/destination, on i965 it is a status, so we don't need to
explicitly set the rounding mode if the one we want is already set.
Taking into account that the default mode is RTE, one possible
optimization would be optimize out the first RTE set for each
block. For in order to work, we would need to take into account block
interrelationships. At this point, it is not worth to complicate the
optimization for such small gain.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
v3: Reset optimization for every block. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:14:09 +0000 (08:14 +0200)]
i965/fs: Enable rounding mode on f2f16 ops
By default we don't set the rounding mode. We only set
round-to-near-even or round-to-zero mode if explicitly set from nir.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
v3: Use new helper brw_rnd_mode_from_nir_op (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:12:59 +0000 (08:12 +0200)]
i965/fs: Define new shader opcode to set rounding modes
Although it is possible to emit them directly as AND/OR on brw_fs_nir,
having a specific opcode makes it easier to remove duplicate settings
later.
v2: (Curro)
- Set thread control to 'switch' when using the control register
- Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode.
- Avoid magic numbers setting rounding mode field at control register.
v3: (Curro)
- Remove redundant and add missing whitespace lines.
- Match printing instruction to IR opcode "rnd_mode"
v4: (Topi Pohjolainen)
- Fix code style.
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:11:58 +0000 (08:11 +0200)]
i965: Add support for control register
Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.
From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
subsection "Control Register" (page 754):
"Subregister cr0.0:ud contains normal operation control fields such as the
floating-point mode ... "
Floating-point Rounding mode is changed at bits 5:4 of cr0.0:
"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
00b = Round to Nearest or Even (RTNE)
01b = Round Up, toward +inf (RU)
10b = Round Down, toward -inf (RD)
11b = Round Toward Zero (RTZ)"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:11:05 +0000 (08:11 +0200)]
i965/fs: Handle 32-bit to 16-bit conversions
Conversions to 16-bit need having aligment between the 16-bit
and 32-bit types. So the conversion operations unpack 16-bit types
to with an stride=2 and then applies a MOV with the conversion.
v2 (Jason Ekstrand):
- Avoid the general use of stride=2 for 16-bit register types.
v3 (Topi Pohjolainen)
- Code style fix
(Jason Ekstrand)
- Now nir_op_f2f16 was renamed to nir_op_f2f16_undef
because conversion to f16 with undefined rounding is explicit
Signed-off-by: Eduardo Lima <elima@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:08:20 +0000 (08:08 +0200)]
i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type
Note that we don't remove the assert at i965/vec4. At this point half
float support is only for the scalar backend.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:06:45 +0000 (08:06 +0200)]
i965: Support for 16-bit base types in helper functions
v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand)
v3: Fix coding style (Topi Pohjolainen)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:06:17 +0000 (08:06 +0200)]
i965/vec4: Handle 16-bit types at type_size_xvec4
These types have similar vec4 sizes as their 32-bit counterparts.
The vec4 backend doesn't support 16-bit types and probably never will,
but this method is called by the scalar backend at
fs_visitor::nir_setup_outputs(), so we still need to provide valid vec4
sizes for 16-bit types. In the future, something different should be
implemented to avoid this dependency.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 06:02:45 +0000 (08:02 +0200)]
spirv/nir: Add support for SPV_KHR_16bit_storage
v2: Minor changes after rebase against recent master (Alejandro
Pinheiro)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:05:55 +0000 (08:05 +0200)]
spirv: Enable FPRoundingMode decorator to nir operations
SpvOpFConvert now manages the FPRoundingMode decorator for the
returning values enabling the nir_rounding_mode in the conversion
operation to fp16 values.
v2: Fixed breaking of specialization constants. (Jason Ekstrand)
v3: Avoid nir_rounding_mode * casting. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 06:04:40 +0000 (08:04 +0200)]
spirv/nir: Handle 16-bit types
v2: Added more missing implementations of 16-bit types. (Jason Ekstrand)
v3: Store values in values[0].u16[i] (Jason Ekstrand)
Include switches based on bitsize for 16-bit types
(Chema Casanova)
v4: Coding style fixes (Jason Ekstrand)
Use vtn_u64_literal and u64[0] at 64-bit SpvOpConstant (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 05:58:26 +0000 (07:58 +0200)]
nir: Handle fp16 rounding modes at nir_type_conversion_op
nir_type_conversion enables new operations to handle rounding modes to
convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
and nir_op_f2f16_rtz.
The undefined behaviour doesn't has any effect and uses the original
nir_op_f2f16 operation.
v2: Indentation fixed (Jason Ekstrand)
v3: Use explicit case for undefined rounding and assert if
rounding mode is used for non 16-bit float conversions
(Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 06:01:21 +0000 (08:01 +0200)]
nir: Populate conversion opcodes to 16-bit types
This will include the following NIR ALU opcodes:
* nir_op_i2i16
* nir_op_i2f16
* nir_op_u2u16
* nir_op_u2f16
* nir_op_f2i16
* nir_op_f2u16
* nir_op_f2f16
v2: Remove "from" 16-bit in commit subject (Topi Pohjolainen)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 05:56:51 +0000 (07:56 +0200)]
nir: Add rounding modes enum
v2: Added comments describing each of the rounding modes. (Jason
Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 05:54:50 +0000 (07:54 +0200)]
nir: Add support for 16-bit types (half float, int16 and uint16)
v2: Renamed glsl_half_float_type() to glsl_float16_t_type().
(Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Thu, 17 Aug 2017 07:51:22 +0000 (09:51 +0200)]
mesa/st: Handle 16-bit types at st_glsl_storage_type_size()
This is basically to avoid "not handle in switch" warnings.
v2: Let the new types hit the assertion instead. (Marek Olšák
and Jason Ekstrand)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 05:46:41 +0000 (07:46 +0200)]
glsl: Add 16-bit types
Adds new INT16, UINT16 and FLOAT16 base types.
The corresponding GL types for half floats were reused from the
AMD_gpu_shader_half_float extension. The int16 and uint16 types come from
NV_gpu_shader_5 extension.
This adds the builtins and the lexer support.
To avoid a bunch of warnings due to cases not handled in switch, the
new types have been added to a few places using same behavior as
their 32-bit counterparts, except for a few trivial cases where they are
already handled properly. Subsequent patches in this set will provide
correct 16-bit implementations when needed.
v2: * Use FLOAT16 instead of HALF_FLOAT as name of the base type.
* Removed float16_t from builtin types.
* Don't copy 16-bit types as if they were 32-bit values in
copy_constant_to_storage().
* Use get_scalar_type() instead of adding a new custom switch
statement.
(Jason Ekstrand)
v3: Use GL_FLOAT16_NV instead of GL_HALF_FLOAT for consistency
(Ilia Mirkin)
v4: Add missing 16-bit base types support in glsl_to_nir (Eduardo Lima).
v5: Fix coding style (Topi Poholainen).
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Thu, 19 Oct 2017 01:02:49 +0000 (18:02 -0700)]
anv: Add support for the variablePointers feature
Not to be confused with variablePointersStorageBuffer which is the
subset of VK_KHR_variable_pointers required to enable the extension.
This means we now have "full" support for variable pointers.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 1 Dec 2017 00:55:45 +0000 (16:55 -0800)]
spirv: Allow OpPtrAccessChain for block indices
The SPIR-V spec is a bit underspecified when it comes to exactly how
you're allowed to use OpPtrAccessChain and what it means in certain edge
cases. In particular, what if the base pointer of the OpPtrAccessChain
points to the base struct of an SSBO instead of an element in that SSBO.
The original variable pointers implementation in mesa assumed that you
weren't allowed to do an OpPtrAccessChain that adjusted the block index
and asserted such. However, there are some CTS tests that do this and,
if the CTS does it, someone will do it in the wild so we should probably
handle it. With this commit, we significantly reduce our assumptions
and should be able to handle more-or-less anything.
The one assumption we still make for correctness is that if we see an
OpPtrAccessChain on a pointer to a struct decorated block that the block
index should be adjusted. In theory, someone could try to put an array
stride on such a pointer and try to make the SSBO an implicit array of
the base struct and we would not give them what they want. That said,
any index other than 0 would count as an out-of-bounds access which is
invalid.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 1 Dec 2017 01:13:56 +0000 (17:13 -0800)]
anv: Handle nir_intrinsic_vulkan_resource_reindex
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 30 Nov 2017 23:56:39 +0000 (15:56 -0800)]
nir: Add a vulkan_resource_reindex intrinsic
This is required for being able to handle OpPtrAccessChain in SPIR-V
where the base type of the incoming pointer requires us to add to the
block index instead of the byte offset.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 00:59:47 +0000 (17:59 -0700)]
spirv: Add support for lowering workgroup access to offsets
Before, we always left workgroup variables as shared nir_variables and
let the driver call nir_lower_io. This adds an option to do the
lowering directly in spirv_to_nir. To do this, we implicitly assign the
variables a std430 layout and then treat them like a UBO or SSBO and
immediately lower all the way to an offset.
As a side-effect, the spirv_to_nir pass now handles variable pointers
for workgroup variables.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 14:40:59 +0000 (07:40 -0700)]
spirv: Rename get_shared_nir_atomic_op to get_var_nir_atomic_op
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 00:58:11 +0000 (17:58 -0700)]
spirv: Add theoretical support for single component pointers
Up until now, all pointers have been ivec2s. We're about to add support
for pointers to workgroup storage and those are going to be uints.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 16:23:07 +0000 (09:23 -0700)]
spirv: Use offset_pointer_dereference to instead of get_vulkan_resource_index
There is no good reason why we should have the same logic repeated in
get_vulkan_resource_index and vtn_ssa_offset_pointer_dereference. If
we're a bit more careful about how we do things, we can just use the one
function and get rid of the other entirely. This also makes the push
constant special case a lot more clear.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 00:38:57 +0000 (17:38 -0700)]
spirv: Refactor a couple of pointer query helpers
This commit moves them both into vtn_variables.c towards the top, makes
them take a vtn_builder, and replaces a hand-rolled instance of
is_external_block with a function call.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Wed, 18 Oct 2017 23:40:39 +0000 (16:40 -0700)]
spirv: Refactor the base case of offset_pointer_dereference
This makes us key off of !offset instead of !block_index. It also puts
the guts inside a switch statement so that we can handle more than just
UBOs and SSBOs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Wed, 18 Oct 2017 23:36:04 +0000 (16:36 -0700)]
spirv: Add a switch statement for the block store opcode
This parallels what we do for vtn_block_load except that we don't yet
support anything except SSBO loads through this path.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Wed, 18 Oct 2017 23:33:32 +0000 (16:33 -0700)]
spirv: Use a dereference instead of vtn_variable_resource_index
This is equivalent and means we don't have resource index code scattered
about.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Brian Paul [Tue, 5 Dec 2017 19:05:48 +0000 (12:05 -0700)]
mesa: add const qualifier on _mesa_is_renderable_texture_format()
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Brian Paul [Tue, 5 Dec 2017 19:05:18 +0000 (12:05 -0700)]
mesa: add const qualifier on _mesa_base_fbo_format()
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Brian Paul [Tue, 5 Dec 2017 16:57:23 +0000 (09:57 -0700)]
mesa: s/%u/%d/ in _mesa_error() call in check_layer()
The layer parameter is signed. Fixes the error message seen when
running the arb_texture_multisample-errors test which checks a
negative layer value.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 16:27:52 +0000 (09:27 -0700)]
mesa: simplify/improve some _mesa_error() calls in teximage.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 14:14:08 +0000 (07:14 -0700)]
mesa: trivial whitespace fixes in transformfeedback.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 04:27:54 +0000 (21:27 -0700)]
mesa: add const qualifier in test_attachment_completeness()
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 14:13:53 +0000 (07:13 -0700)]
st/mesa: remove unneeded #include in st_format.h
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 04:32:33 +0000 (21:32 -0700)]
st/mesa: rename a few vars to 'bindings'
To be consistent.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 04:28:34 +0000 (21:28 -0700)]
st/mesa: whitespace fixes in st_format.c
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Tue, 5 Dec 2017 20:58:31 +0000 (15:58 -0500)]
freedreno/a5xx: hide ARB_base_instance
Grrr..
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 5 Dec 2017 13:40:18 +0000 (08:40 -0500)]
freedreno/ir3: handle input/output component
After the mesa/st nir linking support, we start to see inputs/outputs
like:
decl_var shader_out INTERP_MODE_NONE float packed:uv (VARYING_SLOT_VAR9.x, 1, 0)
decl_var shader_out INTERP_MODE_NONE float packed:uv@0 (VARYING_SLOT_VAR9.y, 1, 0)
(ie. were location_frac != .x)
Unfortunately I overlooked the addition of the component parameter to
load_input/store_output, so when we started encountering inputs/outputs
with component other than .x, we'd end up loading/storing the wrong
input/output.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 5 Dec 2017 14:53:56 +0000 (09:53 -0500)]
mesa/st: move cloning of NIR shader for compute
Since in the NIR case, driver takes ownership of the NIR shader, we need
to clone what is passed to the driver. Normally this is done as part of
creating the shader variant (where is clone is anyways needed). But
compute shaders have no variants, so we were cloning earlier.
The problem is that after the NIR linking optimizations, we ended up
cloning *before* all the lowering passes where done.
So move this into st_get_cp_variant(), to make compute shaders work more
like other shader stages.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Fri, 3 Nov 2017 01:33:44 +0000 (11:33 +1000)]
r600: refactor and export some shader selector code for compute
This just moves some code around to make it easier to add compute.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:27:23 +0000 (11:27 +1000)]
r600: add compute support to compressed resource handling.
This just adds support for decompressing compute resources.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:23:55 +0000 (11:23 +1000)]
r600: update max threads per block for evergreen compute
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:14:28 +0000 (11:14 +1000)]
r600/shader: add local memory support to shader assembler.
This is needed for compute shaders.
v1.1: make work for vectors, fix missing lds ops.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:11:15 +0000 (11:11 +1000)]
r600/cs: add support for compute to image/buffers/atomics state
This just adds the compute paths to state handling for the
main objects
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 02:23:26 +0000 (12:23 +1000)]
r600: handle compute null key shader state
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 27 Nov 2017 06:54:00 +0000 (06:54 +0000)]
r600: add some missing cayman register defines
These are just taken from the kernel, and were seen in some fglrx dumps.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 23 Nov 2017 04:05:05 +0000 (14:05 +1000)]
r600: don't set EOP on pop or loop end
This appears to bad, compute shaders hang without it.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:41:35 +0000 (08:41 +0000)]
r600/ssbo: refactor out buffer coord calcs and use for atomic path.
The atomic rat path has a bug in the ssbo path, refactor out the
address calcs from the load/store paths and reuse to fix the bug
in the buffer rat atomic path.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:38:26 +0000 (08:38 +0000)]
r600/ssbo: fix multi-dword buffer loads.
This fixes loading from different channels.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:35:24 +0000 (08:35 +0000)]
r600/ssbo: use r32ui format for ssbo resources.
This works best for returning the correct values and sizes in
tests.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:34:26 +0000 (08:34 +0000)]
r600: refactor out the immediate setup code.
This just refactors the same code out of the images/buffers paths.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:28:13 +0000 (08:28 +0000)]
r600/shader: fix ssbo atomic operations formats.
Don't try and use the image format for ssbo, just 32-bit uint.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:27:38 +0000 (08:27 +0000)]
r600/shader: fix thread id loading.
This just changes how thread id loading is done, it makes
smaller shaders if we don't use thread id gprs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Herring [Tue, 5 Dec 2017 00:35:48 +0000 (18:35 -0600)]
Android: enable noreturn and returns_nonnull attributes
Commit
94ca8e04adf6 ("spirv: Add vtn_fail and vtn_assert helpers") broke
Android builds which have -Werror enabled with the following errors:
external/mesa3d/src/compiler/spirv/spirv_to_nir.c:272:1: error: control may reach end of non-void function [-Werror,-Wreturn-type]
external/mesa3d/src/compiler/spirv/spirv_to_nir.c:810:1: error: control may reach end of non-void function [-Werror,-Wreturn-type]
...
The problem is the noreturn attribute is not enabled and we to define
HAVE_FUNC_ATTRIBUTE_NORETURN.
Auditing src/util/macros.h, we're also missing
HAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL and HAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT,
so add them too.
Fixes:
94ca8e04adf6 ("spirv: Add vtn_fail and vtn_assert helpers")
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Marek Olšák [Fri, 1 Dec 2017 02:05:18 +0000 (03:05 +0100)]
gallium/u_upload_mgr: allow drivers to specify pipe_resource::flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Dec 2017 01:07:05 +0000 (02:07 +0100)]
winsys/amdgpu: add RADEON_FLAG_READ_ONLY
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 23:14:51 +0000 (00:14 +0100)]
gallium/radeon: remove RADEON_HEAP_VRAM_GTT
Only winsyses can set VRAM|GTT. Drivers shouldn't if they want to use
winsys allocators.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 23:06:34 +0000 (00:06 +0100)]
gallium/radeon: move setting VRAM|GTT into winsyses
The combined VRAM|GTT heap will be removed.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 21:46:39 +0000 (22:46 +0100)]
radeonsi: flush the context after resource_copy_region for buffer exports
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>