frontend/dri: add environment variable DRI_NO_MSAA for performance comparisons

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12491>

radeonsi: remove vertices_per_patch parameter from draw-related functions

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12351>

gallium: remove vertices_per_patch, add pipe_context::set_patch_vertices

We would like draw-only display lists to have immutable draw info and
this is the only GL non-draw state in pipe_draw_info (not counting
view_mask).

It also allows removing some code from draw_vbo for tessellation.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12351>

tu: Remove some stale bypass xfails

These were fixed by 09e0b29bb63f60231b26b4c8f02eadb68e51b623 which was
missed during the suite conversion. For the remaining still-valid fail,
there is a CTS patch in progress.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12488>

freedreno/crashdec: Quiet spammy print in query mode

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>

freedreno/crashdec: Decode full RB in verbose mode

This is useful to get a better view of previous commands in the
ringbuffer.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>

freedreno/cffdec: Fix gpuaddr comparision

gpuaddrs are 64b, and they can be more than 2^^32 apart.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>

freedreno/cffdec: Fix indentation

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12489>

pan/bi: Extend bi_add_nop_for_atest for tilebuffer loads

Fixes framebuffer_fetch and blend_equation_advanced dEQP tests on v6.

v2: Use clause dependencies rather than comparing the message type
v3: Shift the BIFROST_SLOT_* constants before using them as a mask

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12375>

tu: Free device->bo_idx and device->bo_list on init failure

Two related changes:

- in tu_device.c:tu_CreateDevice we need to free both pointers in the
  teardown path after tu_bo_finish(global_bo), which uses the pointers.
  They are allocated in the first call to tu_bo_init(), which happens
  when global_bo is allocated.

- in tu_drm.c:tu_bo_init we need to free bo_list if the bo_idx
  allocation fails. Convert to the goto teardown pattern as well.

Fixes the following dEQP-VK tests:
  dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail
  dEQP-VK.api.object_management.alloc_callback_fail.device
  dEQP-VK.api.object_management.alloc_callback_fail.device_group

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12481>

pan/bi: Use CLPER_V6 on Mali G31

Apparently, CLPER_V7 is missing from Mali G31, but CLPER_V6 works. Fixes
INSTR_INVALID_ENC faults and failures in
dEQP-GLES3.functional.shaders.derivate.* on Dvalin.

Technically not an errata but an implementation difference. I suspect
Mali G51 will need this as well, should we ever allowlist it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

pan/bi: Use ST_TILE for multisampled blend output

ST_TILE lets us specify an explicit sample, whereas BLEND replicates to
all samples. This fully fixes the interaction between blend shaders and
multisampling on Bifrost, manifesting as
dEQP-GLES3.functional.fragment_ops.random.* failures with the
configuration rgba8888d24s8ms4.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

panfrost: Evaluate blend shaders per-sample

This varies the sample ID value, which will be used in the next commit.
This is less complicated than keying blend shaders to the content of
this flag and trying to make mega blend shaders covering all samples at
once ... complexity I'd rather not think about right now. The DDK does
it this way.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

pan/bi: Set the sample ID for blend shader LD_TILE

Use the explicit sample mode and set the sample ID in the pixel indices
structure to the current sample ID. This fixes tilebuffer loads in blend
shaders on multisampled framebuffers.

Make sure the new routine is broken out to a helper for use with ST_TILE
in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

pan/bi: Extract load_sample_id to a helper

Will be reused in the next commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

pan/bi: Correct the sr_count on +ST_TILE

Otherwise we'll get validator fails when emitting +ST_TILE.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

pan/bi: Don't set td in blend shaders

This breaks screen-space derivatives in a shader that uses multiple
render targets, if the derivative calculation is scheduled after a BLEND
instruction calling into a blend shader.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

pan/bi: Set eldest_colour dependency for ST_TILE

I don't think we'll ever hit this in practice, since it's not needed for
blend shaders, but better to correct the code anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

panfrost: Disable shader-assisted indirect draws

Although it is passing all of dEQP-GLES31, it is failing a few
KHR-GLES31.* tests. It also has performance issues at the moment. Invert
the existing noindirect debug flag to become a indirect debug flag. Set
this flag for dEQP-GLES31 CI on G52, to make sure the code doesn't bit
rot on the hope someone will pick this up later on.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12478>

vulkan/wsi/wayland: memset members of image to zero

struct wsi_wl_image is only used as member of the swapchain, and during
the swapchain creation the image is already initialized to zero. So we
have no problems with members of the image being used uninitialized.

But for consistency, memset the members of this struct to zero in
wsi_wl_image_init(). This can help to avoid problems in the future.

Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12451>

vulkan/wsi/wayland: create swapchain using vk_zalloc()

In wsi_wl_surface_create_swapchain() we have a piece of code to init
some members of the chain to 0, in order to allow us to call
wsi_wl_swapchain_destroy() for cleanup.

Instead, we can use vk_zalloc() to allocate the chain, as it initializes
all members of the struct to zero. This help us to avoid problems when
people add new members to the struct and forget to initialize them.
Also, it makes the code look better.

Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12451>

ci/lavapipe: Add a fractional run with ASan

This catches use-after-frees and buffer overflows, but not leaks (which we
disable the checking for since the library gets dlclose()d and we end up
with useless backtraces).

Reviewed-by: Adam Jackson <ajax@redhat.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8889>

tu: Add a650-specific CCU flush workaround

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12475>

tu: Properly handle waiting on an earlier pipeline stage

I never really implemented this properly, because I wasn't aware of the
clusters when doing the original pipeline barrier implementation. It
turns out that the Vulkan stages we get as part of the barriers are
actually good for something, because it turns out that the pipeline
state is split into stages, so earlier stages can run ahead of later
stages and sometimes we need to wait when an earlier stage depends on
the result of a later stage. This happens most often whenever a shader
reads the result of a color/depth attachment write, because attachment
writes happen in a logically later stage. However this could also happen
for a FS -> VS dependency.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12475>

anv: Optimize genX(cmd_buffer_emit_gfx12_depth_wa)

Only emit the workaround as needed.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

iris: Optimize genX(emit_depth_state_workarounds)

Only emit the workaround as needed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

iris: Use constants for emitting cso_z->packets

This should be a bit faster and easier to follow.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

intel: Move the D16 workarounds out of ISL

Implement the workarounds in anv and iris instead.

Before this commit, ISL unconditionally modified workaround registers
while filling out depth stencil state. To account for this, drivers
unconditionally stalled prior to emitting depth stencil packets. This
hurt performance.

By having the drivers perform the workarounds, they can choose when to
modify the relevant registers. The drivers now avoid emitting the
workaround for NULL depth buffers. This reduces stalls and leads to
better performance.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (the ISL/Anv bits)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (the Iris bits)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

iris: Update clear_params only when HiZ is enabled

This more closely matches ISL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

iris: Emit clear_params as part of cso_z->packets

This should be a bit faster.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

iris: Update the clear value in cso_z->packets

Enables emitting the packets all at once later on.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

iris: Add genX(emit_depth_state_workarounds)

This will replace the workaround built into ISL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

anv: Add genX(cmd_buffer_emit_gfx12_depth_wa)

This will replace the workaround built into ISL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11454>

radv: fix copying depth+stencil images on compute

Using separate aspects is required.

Fixes few CTS failures (dEQP-VK.api.copy_and_blit.*) when the compute
path is forced in the driver. Note that CTS coverage of compute queue
is rather limited.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12287>

glsl: fix variable scope for instructions inside case statements

Fixes: 665d75cc5a23 ("glsl: Fix scoping bug in if statements.")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5247

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12435>

radv: remove incorrect comment about compressed writes to HTILE on GFX10+

This seems to be unsupported.
COMPRESSION_EN=1 and WRITE_COMPRESS_ENABLE=1 don't update HTILE
with image stores.

Note that there is no issue because depth/stencil images will be
decompressed for image stores, and TC-compat HTILE is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12450>

radv: remove unnecessary check in radv_layout_is_htile_compressed()

The driver doesn't enable TC-compat HTILE for storage images, so this
was actually always TRUE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12450>

st/mesa: move handling CubeMapSeamless into st_convert_sampler where it belongs

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12334>

st/mesa: set take_ownership = true in set_sampler_views

update_textures_local is removed because the only thing it did was
unreferencing sampler views, which is being removed.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12334>

gallium: add take_ownership into set_sampler_views to skip reference counting

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12334>

ac/surface: allow arbitrary swizzle modes for displayable DCC

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>

radv: allow arbitrary swizzle modes for displayable DCC

by adding retile pipeline variants

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>

radeonsi: allow arbitrary swizzle modes for displayable DCC

by adding retile shader variants

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12430>

ir3: prohibit folding of half->full conversion into mul.s24/u24

mul.s24/u24 always return 32b result regardless of its sources size,
hence we cannot guarantee the high 16b of dst being zero or sign extended.

Fixes cts tests on a650:
 dEQP-VK.spirv_assembly.type.scalar.i16.mul_test_high_part_zero_*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12471>

freedreno/ci: Add spillall tests

Only test shader tests, because the others are unlikely to have
interesting shaders.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3, turnip, freedreno: Report stp/ldp in shader stats

This is important after spilling, so that we get an indication when a
change causes spilling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Fix getting stp/ldp components in ir3_info

Noticed by inspection when adding stp_count/ldp_count.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Initial support for spilling non-shared registers

Support for spilling shared registers to normal registers is still TODO.
There are also several improvements to be made, like rematerialization.

Note, there is one behavior change to register pressure accounting: we
now include half registers in the current full pressure directly in
mergedregs mode, rather than adding the max half pressure to the max
full pressure afterwards, which might result in lower calculated max
pressure in some cases with half registers. This is needed for spilling,
since we need to make sure the total pressure including half registers
is below the maximum at each instruction. Because the entire pass is
rewritten, including the register pressure calculating parts, it didn't
seem worth it to separate out this change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Fix compress_regs_left accounting for half-regs

This was just wrong - we need to check against the entire register file,
and we need to include removed full regs even if the register we're
trying to insert is a half-reg, or else we could run out of space when
reinserting full regs after it. There does need to be an additional
check so that we don't try to insert a half-reg beyond the half-reg
limit, but that has to happen in addition to the normal check.

This fixes KHR-GLES31.core.arrays_of_arrays.InteractionArgumentAliasing6
once spilling is added.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Properly validate pcopy reg sizes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Fix RA debug printing

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Add ra_foreach_src_n/ra_foreach_dst_n

I found ra_foreach_src_n useful in one place in the spiller. But this
also aligns RA with the rest of the compiler and stops us from
reinventing the iterators.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Add loop depth to ir3_block

And while we're at it, fix adding loop_id for the continue block.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/ra: Make ir3_reg_interval_remove_all() useful for spilling

RA uses this to pop and then reinsert intervals when shuffling around
registers. For spilling, we want to remove the interval and also mark
all its descendants as removed. Since "remove_all" sounds more like the
latter, rename the old "remove_all" to "remove_temp". "remove_all" was
already exposed in ir3_ra.h, so there's no need to add it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/ra: Handle huge merge sets

It can happen that we create an enormous merge set, even larger than the
entire register file, in which case find_best_gap() would loop
infinitely. This seems to be triggered more often with
IR3_SHADER_DEBUG=spillall, since it actually happened with a CTS test.
Just bail out in that case.

Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/ra: Fix available bitset for live-through collect srcs

When we mark live-through sources that are merged with the destination
as killed, we kept the bitsets in sync, but we forgot to keep them in
sync when unmarking them after allocating the destination. The result
was that "available" wasn't correct for any instruction afterwards. This
resulted in a bad register allocation with IR3_SHADER_DEBUG=spillall for
a dEQP-VK test.

While we're changing this, use ra_foreach_src().

Fixes: 0ffcb19b9d9 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/ra: Reinitialize interval when inserting

Otherwise when an interval is removed and then re-inserted it could
have an invalid/corrupted parent link and child tree. I think RA
happened to never do this, but spilling will.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/merge_regs: Set wrmask for pcopy destinations

This was wrong, and with spilling we can now create vector phi's in rare
circumstances.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/print: Use mesa_stream_log_printf for (kill)

This was missed during the conversion.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Print physical successors/predecessors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Copy-propagate single-source phis

These can be created when removing unreachable control flow, and it
seems easier to remove them than to add special code to handle them when
spilling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3/ra: Remove logical_unreachable

This reverts 394c597b1b31842b3943e30ab7f21359b0076b13, although I had to
manually do it due to the reformatting.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

ir3: Add pass to remove unreachable blocks

Rather than continue to add special cases for these, just clean them up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12033>

draw: improve numerical stability in clipper

Floats have much better precision close to zero than close to one, so
let's make sure we compute an interpolation factor that goes in the
direction that discards the fewest bits.

This makes a big difference when interpolating from very small to very
large values for screen-space positions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12355>

gitlab-ci: Fix trace expectations for iris devices

By checking the output images against the reference ones on the failed
trace jobs, I looked for artifacts via naked eye and image diffs. No
significant change was found. So the trace produced by the failed jobs
can be considered valid.

Updated devices' traces:
* Intel Comet Lake: iris-cml-traces
* Intel Gemini Lake: iris-glk-traces
* Intel Kaby Lake: iris-kbl-traces
* Intel Whiskey Lake: iris-whl-traces

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12394>

gitlab-ci: enable testing on Intel Comet Lake (experimental)

* Integrate sarien Chromebook devices from Collabora lab
* Based on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11162

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12394>

gitlab-ci: enable testing on Intel Whiskey Lake (experimental)

* Integrate sarien Chromebook devices from Collabora lab
* Based on https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11162

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12394>

mesa: rgb10_a2 is never color-renderable in gles2

Fixes
dEQP-GLES2.functional.fbo.completeness.renderable.texture.color0.rgb10_a2 on
GLES2 drivers which support RGB10_A2 textures.
GL_OES_required_internalformat does not make it a color-renderable
format.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4972
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12464>

freedreno/a6xx: Sync TFB BO access against prior TFB writes.

CTS draw_indirect usage of TFB output was flaking due to the TFB writes
possibly not having completed.  Since GL TFB doesn't require any other
barrier between TFB and use of the BO (as seen by the CTS not emitting any
memory barrier), we have to do it ourselves.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12457>

freedreno/ir3: Align driver param upload size/offset for indirect uploads.

For indirect draws, we have to upload some of the params as indirect
references, which have a more strict size requirement.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12455>

freedreno/ir3: Apply the a6xx samgq workaround to TES/TCS/GS as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12454>

anv: Set CONTEXT_PARAM_RECOVERABLE to false

We want the kernel to ban our context immediately instead of foolhardily
attempting to recover.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12476>

aco/tests: add tests for post-RA DPP combining

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco/tests: add tests for pre-RA DPP combining

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: combine DPP into VALU after RA

Mostly helps a bunch of Cyberpunk 2077 shaders.

fossil-db (Siena Cichlid):
Totals from 26 (0.02% of 150170) affected shaders:
CodeSize: 83208 -> 81528 (-2.02%)
Instrs: 14728 -> 14308 (-2.85%)
Latency: 48041 -> 47793 (-0.52%)
InvThroughput: 10836 -> 10578 (-2.38%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: combine DPP into VALU before RA

Mostly helps a bunch of Cyberpunk 2077 shaders. Catches some of the cases
that the post-RA can't optimize because of register assignment.

fossil-db (Siena Cichlid):
Totals from 25 (0.02% of 150170) affected shaders:
CodeSize: 78808 -> 75764 (-3.86%)
Instrs: 14311 -> 13547 (-5.34%)
Latency: 278697 -> 277885 (-0.29%)
InvThroughput: 63428 -> 62754 (-1.06%)
Copies: 1348 -> 1349 (+0.07%); split: -0.07%, +0.15%
PreVGPRs: 1035 -> 1011 (-2.32%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: handle DPP in the optimizer

There are a bunch of optimizations that are broken when DPP is involved.

fossil-db (Sienna Cichlid):
Totals from 100 (0.07% of 150170) affected shaders:
CodeSize: 325204 -> 325192 (-0.00%); split: -0.06%, +0.05%
Instrs: 62773 -> 62664 (-0.17%); split: -0.18%, +0.00%
Latency: 295348 -> 295266 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 73990 -> 73946 (-0.06%); split: -0.06%, +0.01%
Copies: 1650 -> 1609 (-2.48%); split: -2.55%, +0.06%
PreSGPRs: 3554 -> 3520 (-0.96%)

Fossil-db changes are probably because v_sub_f32_dpp(v_mul_f32) is no
longer being combined into MAD and then split back into separate
instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: make optimize_postRA() work across blocks

fossil-db (Sienna Cichlid):
Totals from 46 (0.03% of 150170) affected shaders:
CodeSize: 103672 -> 103488 (-0.18%)
Instrs: 21968 -> 21922 (-0.21%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: move a bunch of helpers into aco_ir.h/aco_ir.cpp

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: add can_use_DPP() and convert_to_DPP()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

aco: fix validation of DPP v_cndmask_b32/v_addc_co_u32

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>

i915g: clang-format fixup.

I really need to get clang-format into CI so I can stop doing fixups.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12436>

i915g: Add comments explaining various xfails.

I haven't gone through every test (particularly ones I think are loop
unrolling or instruction-count-related ones I think), but this gives a
better picture of what's going on in this driver.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12436>

i915g: Clear some xfails that are now skips.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12436>

i915g: Reduce ARB_fp max tex indirections to match i915c.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12436>

i915g: Correct PIPE_SHADER_CAP_MAX_TEMPS.

This is the value that i915c reported, too, and is required for ARB_fp.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12436>

i915g: Fix polygon offset by telling draw the Z format.

This is what initializes the MRD for draw's polygon offset calculations.

Closes: #4976
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12436>

frontends/va: add num_temporal_layers check

Fixes: 51935d59

temporal_id check is valid only if the num_temporal_layers is set (>0).
When num_temporal_layers is 0, we shouldn't check temporal_id and return
error.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12463>

radeon/vcn: set min value for num_temporal_layers

Fixes: 51935d59

In the case where num_temporal_layers is not set (0), set it using the
minimum value 1, otherwise the rate control settings will be missing.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12463>

nir: return false for loops in contains_other_jump()

Allows to unwrap more loops.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12473>

v3d: implement resource_get_param

Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.

Instead, implement the resource_get_param hook to allow users to
fetch this information without WINSYS_HANDLE_TYPE_KMS.

A tiny helper function is introduced to compute the modifier of a
resource.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 7bcb22363935 ("v3d, vc4: Fix dmabuf import for non-scanout buffers")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>

vc4: implement resource_get_param

Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.

Instead, implement the resource_get_param hook to allow users to
fetch this information without WINSYS_HANDLE_TYPE_KMS.

A tiny helper function is introduced to compute the modifier of a
resource.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 7bcb22363935 ("v3d, vc4: Fix dmabuf import for non-scanout buffers")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>

panfrost: implement resource_get_param

Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.

Instead, implement the resource_get_param hook to allow users to
fetch this information without WINSYS_HANDLE_TYPE_KMS.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 4c092947df30 ("panfrost: fail in get_handle(TYPE_KMS) without a scanout resource")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>

etnaviv: add stride, offset and modifier to resource_get_param

Prior to this commit, the stride, offset and modifier were fetched
via WINSYS_HANDLE_TYPE_KMS. However we can't make such a query
succeed if the buffer couldn't be imported to the KMS device.

Instead, extend the resource_get_param hook to allow users to fetch
this information without WINSYS_HANDLE_TYPE_KMS.

Signed-off-by: Simon Ser <contact@emersion.fr>
Fixes: 9da901d2b2e7 ("etnaviv: fail in get_handle(TYPE_KMS) without a scanout resource")
Reported-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370>

gallium/nir/tgsi: initialize file_max for inputs

When this was rewritten to support Vulkan, we stopped initializing
file_max to -1 in the case of no inputs. This causes the draw module
to go down a needlessly pessimistic case, printing an error while we're
at it.

Fixes: 42b5cfdbd26 ("gallivm/nir: fix vulkan vertex inputs")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12440>

gallium/nir/tgsi: fixup indentation

This was using mixed tabs and spaces, let's fix that before we start
modifying the code.

Fixes: 42b5cfdbd26 ("gallivm/nir: fix vulkan vertex inputs")
Reviewed-by: default avatarDave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12440>

turnip: apply workaround for depth bounds test without depth test

On some GPUs when:
- depth bounds test is enabled
- depth test is disabled
- depth attachment uses UBWC in sysmem mode
GPU hangs. As a workaround we should enable z test. That's what blob
is doing for a630. And since we enable z test we should make it always pass.

Blob doesn't emit this workaround on a650 and a660. Untested on a640.

Fixes:
 dEQP-VK.pipeline.extended_dynamic_state.two_draws_static.depth_bounds_test_disable
 dEQP-VK.pipeline.extended_dynamic_state.two_draws_dynamic.depth_bounds_test_disable
 dEQP-VK.dynamic_state.ds_state.depth_bounds_1

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12407>

freedreno: rename Z_TEST_ENABLE->Z_READ_ENABLE, Z_ENABLE->Z_TEST_ENABLE

This makes their interaction with Z_BOUNDS_ENABLE more understandable.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12407>

draw: fix stippling of fractional lines

The OpenGL 4.6 specification, section 14.5.2.1 (Line Stipple) says:

> The masking is achieved using three parameters: the 16-bit line
> stipple p, the line repeat count r, and an integer stipple counter s.

This is pretty clear that the stipple counter shouldn't carry fractional
parts. But we also don't really do anything useful with the fractional
part anyway, apart from skewing the third or later line-segments

Properly carrying over the fractional parts as the Vulkan specification
allows for rectangular lines is trickier than this and would require us
to use a shorter output-line at the start of the following
line-segments.

But let's just do what the OpenGL specification describes, and the
Vulkan specification allows for now.

This, combined with the following patch for the vulkan CTS makes the
last two rasterization-tests pass for me:

https://github.com/KhronosGroup/VK-GL-CTS/pull/279

Fixes the "spec/!opengl 1.1/linestipple/line strip" piglit-test.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12327>

turnip: use nir_shader_instructions_pass in tu_lower_io

No functional changes.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12467>