Masahiro Yamada [Wed, 16 Dec 2015 01:54:07 +0000 (10:54 +0900)]
ARM: dts: uniphier: factor out common nodes to uniphier-common32.dtsi
UniPhier SoCs (except PH1-sLD3) have several nodes in common.
Factor out them into uniphier-common32.dtsi. This improves the code
maintainability.
PH1-sLD3 is so old that it has more or less different register maps
than the others. So, it cannot be included in this refactoring.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 16 Dec 2015 01:50:26 +0000 (10:50 +0900)]
ARM: uniphier: allow DDR function to return more precise error code
Return different error code depending on the reason so that the
caller can know the cause of the failure.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 16 Dec 2015 01:44:28 +0000 (10:44 +0900)]
ARM: uniphier: use BIT() macro for DDR PHY header
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 16 Dec 2015 01:42:29 +0000 (10:42 +0900)]
ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_*
The bit 27-24 of the DTCR register is described as RANKEN in the
DDR PHY databook. Follow this abbreviation.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Wed, 16 Dec 2015 01:36:13 +0000 (10:36 +0900)]
ARM: uniphier: add const qualifier to constant array
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada [Fri, 11 Dec 2015 08:17:53 +0000 (17:17 +0900)]
ARM: uniphier: add static qualifiers to locally used functions
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tom Rini [Tue, 22 Dec 2015 02:07:04 +0000 (21:07 -0500)]
Prepare v2016.01-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 21 Dec 2015 23:25:10 +0000 (18:25 -0500)]
Merge git://git.denx.de/u-boot-arc
Alexey Brodkin [Thu, 10 Dec 2015 13:56:42 +0000 (16:56 +0300)]
axs103: add support of generic OHCI USB 1.1 controller
This commit adds support of USB 1.1 storage media on AXS103 board.
For some yet unknown reason USB 2.0 doesn't work on AXS103 board issuing
messages like this:
------------------------>8-------------------
AXS# usb start
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... EHCI timed out on TD - token=0x80008c80
unable to get device descriptor (error=-1)
1 USB Device(s) found
------------------------>8-------------------
As a work-around we're falling back to USB 1.1.
Indeed it is much slower but at least USB storage devices are usable on
AXS103.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Aleksei Mamlin [Sun, 20 Dec 2015 21:45:13 +0000 (00:45 +0300)]
sunxi: Add CONFIG_SUNXI_NO_PMIC to Marsboard A10 config
Marsboard A10 haven't any PMIC at all, so add CONFIG_SUNXI_NO_PMIC=y to
Marsboard_A10_defconfig
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Mon, 21 Dec 2015 19:22:00 +0000 (20:22 +0100)]
sunxi: Select DM_KEYBOARD
We need to select DM_KEYBOARD now that the usb-kbd code has been converted
to this, otherwise usb keyboards do not work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Karsten Merker [Wed, 16 Dec 2015 19:59:40 +0000 (20:59 +0100)]
sunxi: Enable a second mmc socket as boot target in the environment
Some sunxi-based boards (such as the Olimex A20-SOM-EVB) have a
second MMC socket. This socket is not bootable hardware-wise,
i.e. u-boot itself cannot be loaded from it, but once u-boot has
started, the second socket can be used in the boot process
provided by config_distro_bootcmd.h.
If a second MMC socket is present, place it in the boot order
after the first MMC socket.
Signed-off-by: Karsten Merker <merker@debian.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Karsten Merker [Wed, 16 Dec 2015 19:59:39 +0000 (20:59 +0100)]
sunxi: A20-Olimex-SOM-EVB defconfig: enable mmc3
The Olimex A20-SOM-EVB is an evaluation board for the Olimex
A20-SOM system-on-module. The baseboard provides a full-size SD
socket (connected to mmc3) in addition to the micro-SD socket on
the SOM itself (which is connected to mmc0).
Enable the mmc3 controller in the board defconfig.
Signed-off-by: Karsten Merker <merker@debian.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Sun, 20 Dec 2015 11:30:18 +0000 (12:30 +0100)]
sun5i: Add defconfig and dts file for the Empire Electronix D709 tablet
The Empire Electronix D709 tablet is a fairly standard 7" A13 tablet,
featuring usb-wifi, a micro-sd slot, micro-usb otg and headphone jack.
Empire Electronix is written on the back of the tablet, the D709 model
info can be found in the about tablet menu in android.
The PCB has no markings to speak of.
This dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Simon Glass [Sat, 19 Dec 2015 22:44:04 +0000 (15:44 -0700)]
x86: Remove Graeme Russ from the git alias file
As requested, remove Graeme's email address.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Sun, 20 Dec 2015 03:05:31 +0000 (22:05 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-socfpga
Dinh Nguyen [Thu, 3 Dec 2015 22:05:59 +0000 (16:05 -0600)]
arm: socfpga: fix trivial header preprocessor for socfpga_common.h
Replace__CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ with
__CONFIG_SOCFPGA_COMMON_H__ as the file is now called socfpga_common.h
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh Nguyen [Wed, 2 Dec 2015 19:31:33 +0000 (13:31 -0600)]
arm: socfpga: fix up a questionable macro for SDMMC
Move the macro into the socfpga_dwmci_clksel().
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
[fix parenthesis in the sdmmc_mask]
Dinh Nguyen [Wed, 2 Dec 2015 19:31:32 +0000 (13:31 -0600)]
arm: socfpga: remove building scan manager
The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
Dinh Nguyen [Wed, 2 Dec 2015 19:31:25 +0000 (13:31 -0600)]
arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property
In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh Nguyen [Mon, 7 Dec 2015 22:48:04 +0000 (16:48 -0600)]
arm: socfpga: remove note to add CONFIG_USB_DWC2_REG_ADDR
Now that the USB DWC2 probing is done from OF, remove this note to add
CONFIG_USB_DWC2_REG_ADDR.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 20:10:44 +0000 (21:10 +0100)]
arm: socfpga: Drop the board boilerplate
Drop all the common board code, since it is not completely useless.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 20:07:23 +0000 (21:07 +0100)]
arm: socfpga: Introduce common board code
The SoCFPGA has reached a point where every single board code become
the same, since each and every single board is probed equally from OF.
Move the common board code into arch/arm/mach-socfpga/ .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 19:08:21 +0000 (20:08 +0100)]
arm: socfpga: Switch CONFIG_HOSTNAME to CONFIG_SYS_BOARD
We already have the CONFIG_SYS_BOARD variable, which defines the name
of the board. The value in CONFIG_HOSTNAME is exactly the same and is
thus just a duplicity, so switch it to reuse CONFIG_SYS_BOARD .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 19:05:46 +0000 (20:05 +0100)]
arm: socfpga: Switch CONFIG_G_DNL_MANUFACTURER to CONFIG_SYS_VENDOR
We already have the CONFIG_SYS_VENDOR variable, which defines the
manufacturer of the board. The value in CONFIG_G_DNL_MANUFACTURER
is just a duplicity, so switch it to reuse CONFIG_SYS_VENDOR .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 19:01:40 +0000 (20:01 +0100)]
arm: socfpga: sockit: Zap VIRTUAL_TARGET
There is no VT for this board, so remove this incorrect macro.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 19:00:52 +0000 (20:00 +0100)]
arm: socfpga: de0_nano: Zap VIRTUAL_TARGET
There is no VT for this board, so remove this incorrect macro.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 18:24:22 +0000 (19:24 +0100)]
arm: socfpga: socrates: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 18:24:22 +0000 (19:24 +0100)]
arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 18:24:22 +0000 (19:24 +0100)]
arm: socfpga: mcvevk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 18:24:22 +0000 (19:24 +0100)]
arm: socfpga: de0_nano: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 18:24:22 +0000 (19:24 +0100)]
arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 18:24:22 +0000 (19:24 +0100)]
arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded data
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 18:28:44 +0000 (19:28 +0100)]
arm: socfpga: Allow DWC2 UDC probing from OF
The USB gadget framework does not support DM yet, so add this bit
to let DWC2 UDC probe from OF on platforms which support it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Sat, 5 Dec 2015 16:55:36 +0000 (17:55 +0100)]
arm: socfpga: socrates: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 16:55:54 +0000 (17:55 +0100)]
arm: socfpga: sockit: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 18:00:00 +0000 (19:00 +0100)]
arm: socfpga: de0_nano: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 16:55:19 +0000 (17:55 +0100)]
arm: socfpga: cyclone5-socdk: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 16:54:35 +0000 (17:54 +0100)]
arm: socfpga: arria5-socdk: Remove Micrel PHY configuration
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 16:53:40 +0000 (17:53 +0100)]
arm: socfpga: socrates: Add missing PHY skew config
Add missing KSZ9021 PHY skew configuration for the EBV socrates board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Sat, 5 Dec 2015 16:41:58 +0000 (17:41 +0100)]
net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OF
Add code to process the KSZ9021/KSZ9031 OF props if they are present
and configure skew registers based on the information from the OF.
This code is only enabled if the DM support for ethernet is also
enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
V2: - Implement struct ksz90x1_reg_field to describe the skew register
fields more accurately.
- Fix RXDV/TXEN skew register default value and offset.
Thomas Chou [Fri, 18 Dec 2015 13:35:08 +0000 (21:35 +0800)]
altera_qspi: initialize instr.mtd in flash_erase
Initialize instr.mtd in flash_erase(). This fixes the system
hang issue when CONFIG_MTD_PARTITIONS is selected.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Thomas Chou [Thu, 17 Dec 2015 13:46:17 +0000 (21:46 +0800)]
serial-howto: remove altera_jtag_uart and altera_uart from the list
Since both altera_jtag_uart and altera_uart are converted to driver
model, remove them from the list of drivers remaining to convert.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Chin Liang See <clsee@altera.com>
Thomas Chou [Wed, 16 Dec 2015 08:07:06 +0000 (16:07 +0800)]
nios2: display altera sysid at startup
Display altera sysid at startup, which was once removed during
the move.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 16 Dec 2015 00:32:48 +0000 (01:32 +0100)]
nios2: Soup up the shell experience
Enable command auto completion and enable $version variable. This makes
working with U-Boot far more enjoyable.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Marek Vasut [Wed, 16 Dec 2015 00:32:47 +0000 (01:32 +0100)]
nios2: Enable support for fitImage
The uImage format is legacy for years now, enable support for the
fitImage format, which allows combining multiple files (kernel and
dtb) into a single file, offers better protection of the payload
and so on.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Marek Vasut [Tue, 15 Dec 2015 02:09:24 +0000 (03:09 +0100)]
nios2: Preconfigure $loadaddr variable
Preset the $loadaddr environment variable to some sane default, let's
say half of the RAM. This variable is where the kernel is loaded using
all sorts of .*load commands, so it's convenient to have it set.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Marek Vasut [Tue, 15 Dec 2015 02:09:23 +0000 (03:09 +0100)]
nios2: Up the monitor size to 512kiB
The monitor is growing much larger with various additions, like fitImage,
command line completion, UBI etc. Make the monitor area larger so these
features can be safely added.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Marek Vasut [Tue, 15 Dec 2015 02:09:22 +0000 (03:09 +0100)]
nios2: Calculate the env position from monitor size
Reorder the 10m50 and 3c120 config files such, that the environment
position can be calculated from the monitor size. The environment is
placed right after the monitor. This removes one more ad-hoc variable.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Tom Rini [Fri, 18 Dec 2015 12:28:24 +0000 (07:28 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-microblaze
Michal Simek [Wed, 9 Dec 2015 10:53:25 +0000 (11:53 +0100)]
microblaze: Do not handle watchdog and gpio in SPL
watchdog and gpio are not validated for SPL that's why do not use them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 9 Dec 2015 10:44:17 +0000 (11:44 +0100)]
microblaze: Enable DM by default
Enable DM for the whole architecture.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 2 Dec 2015 13:21:05 +0000 (14:21 +0100)]
microblaze: Enable OF_CONTROL by default
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 2 Dec 2015 16:22:07 +0000 (17:22 +0100)]
microblaze: Remove support for LL_TEMAC
LL_TEMAC is available at big endian MB and it is not properly tested
that's why the patch removes it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Dec 2015 13:45:54 +0000 (14:45 +0100)]
microblaze: Use malloc setting via Kconfig
Clean board specific file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Tue, 8 Dec 2015 13:34:13 +0000 (14:34 +0100)]
microblaze: Make room for malloc before ELF
Create space below u-boot binary for early malloc.
It means memory layout is stack grows down, space for early malloc,
u-boot code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Dec 2015 15:45:30 +0000 (16:45 +0100)]
dm: net: Fix DM for targets which use MANUAL_RELOC
All ethernet operation needs to be updated for architectures which
requires MANUAL_RELOC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Fri, 11 Dec 2015 08:14:31 +0000 (09:14 +0100)]
net: gem: Add driver dependencies to PHYLIB
Clear driver dependecies via Kconfig. Remove PHYLIB dependency from
the driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 9 Dec 2015 15:53:52 +0000 (16:53 +0100)]
net: gem: Fix typo in Kconfig entry
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Wed, 9 Dec 2015 13:26:48 +0000 (14:26 +0100)]
net: gem: Separate recv and free_pkt functions
Use core to call net_process_received_packet() instead of call inside
the driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Wed, 9 Dec 2015 13:16:32 +0000 (14:16 +0100)]
net: gem: Fix return value from recv
recv function should return 0 instead of frame_len not to
proceed the same packet again in core.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Wed, 9 Dec 2015 08:29:12 +0000 (09:29 +0100)]
net: gem: Setup default phy address to -1
Undefined phy address is -1 not 0.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Nathan Rossi [Tue, 8 Dec 2015 14:44:42 +0000 (00:44 +1000)]
arm: zynq: Update ZYBO config options
Update the ZYBO device tree and enable config options that relate to the
added devices in the device tree.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nathan Rossi [Tue, 8 Dec 2015 14:44:40 +0000 (00:44 +1000)]
spi: zynq_qspi: Add configuration to disable LQSPI feature
When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.
This ensures the Linear QSPI mode is disabled before re-enabling the
device.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nathan Rossi [Tue, 8 Dec 2015 14:44:43 +0000 (00:44 +1000)]
tools: zynqimage: Clean up check_params
Clean up the param checking, removing some code paths that will never
happen.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
Reported-by: Coverity (CID 133251)
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nathan Rossi [Tue, 24 Nov 2015 09:34:09 +0000 (19:34 +1000)]
ARM: zynq: Add default ps7_init_gpl.c/h for ZYBO
Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init
is generated by the Vivado 2015.3 tools using the system configuration
provided by Digilent located on their website.
Update the kconfig so that the defconfig is not overrided to use the
custom init ps7_init_gpl target by default.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Dec 2015 10:56:23 +0000 (11:56 +0100)]
ARM: zynq: Enable u-boot,dm-pre-reloc for sdhci
Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo.
And create aliases for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 18 Dec 2015 02:46:04 +0000 (21:46 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
Stephen Warren [Fri, 13 Nov 2015 20:34:09 +0000 (13:34 -0700)]
usb: kbd: don't use int xfers when polling via ctrl xfers
When CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP is enabled, use a
GET_REPORT control transfer to retrieve the initial state of the
keyboard. This matches the technique used to poll the keyboard state.
This is useful since it eliminates the remaining use of interrupt
transfers from the USB keyboard driver, which allows it to work with
USB HCD that don't support interrupt transfers.
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Alexey Brodkin [Mon, 14 Dec 2015 14:18:50 +0000 (17:18 +0300)]
usb: add support of generic OHCI devices
This driver is meant to be used with any OHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Lukasz Majewski [Thu, 10 Dec 2015 15:32:25 +0000 (16:32 +0100)]
usb: host: ehci: samsung: Move hcor initialization after usb phy setup
With the old order of initialization the hcor pointer has been setup to
the same address as Exynos EHCI base address (0x12110000 instead of
0x12110010).
Such behaviour was caused by reading value of 0 instead of 0x10 from EHCI
HCCPBASE register without doing proper clock initialization before.
To fix this problem hcor initialization has been moved after USB PHY setup.
Now ehci_readl(&ctx->hcd->cr_capbase) returns correct value.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Marek Vasut [Fri, 4 Dec 2015 01:51:20 +0000 (02:51 +0100)]
usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.h
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.
The rename is done automatically:
$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
`git grep "s3c_udc\.h" | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:26:33 +0000 (02:26 +0100)]
usb: s3c-otg: Rename s3c_udc_probe() function
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.
The rename is done automatically:
$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
`git grep s3c_udc_probe | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:23:29 +0000 (02:23 +0100)]
usb: s3c-otg: Rename struct s3c_plat_otg_data
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.
The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 19 Aug 2015 21:27:26 +0000 (23:27 +0200)]
usb: s3c-otg: Rename USB_GADGET_S3C_UDC_OTG* to USB_GADGET_DWC2_OTG*
The s3c-otg IP block is in fact a DWC2 OTG one, so finally rename the
config option to make it less misleading. No functional change, just
a mechanical change done using the following script:
git grep USB_GADGET_S3C_UDC_OTG | cut -d : -f 1 | sort -u | \
while read line ; do
sed -i "s/USB_GADGET_S3C_UDC_OTG/USB_GADGET_DWC2_OTG/g" $line ;
done
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:55:37 +0000 (02:55 +0100)]
usb: s3c-otg: Tweak the comments
The driver is actually for the Designware DWC2 controller.
Tweak the comments in the driver to reflect this fact.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:44:33 +0000 (02:44 +0100)]
usb: s3c-otg: Rename remaining macros
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining S3C_* macros to match the
DWC2 naming.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:34:46 +0000 (02:34 +0100)]
usb: s3c-otg: Rename sources to dwc2_*c
The driver is actually for the Designware DWC2 controller.
This patch renames the local source files to dwc2_*c and
adjusts the Makefile to use the new names.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:32:22 +0000 (02:32 +0100)]
usb: s3c-otg: Rename local headers to dwc2_*h
The driver is actually for the Designware DWC2 controller.
This patch renames the local header files to dwc2_*h and
adjusts the sources to use the new names.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:28:40 +0000 (02:28 +0100)]
usb: s3c-otg: Change the driver name to dwc2-udc
Just change the driver name.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:21:41 +0000 (02:21 +0100)]
usb: s3c-otg: Zap useless externs
The extern statements are useless, remove them. Also remove the
extern ... controller, which is completely useless.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:17:40 +0000 (02:17 +0100)]
usb: s3c-otg: Rename remaining local s3c_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the remaining local s3c_*() functions
to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:03:45 +0000 (02:03 +0100)]
usb: s3c-otg: Rename s3c_udc_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
The function s3c_udc_probe() is a special case and is not
renamed by this patch yet.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 01:13:42 +0000 (02:13 +0100)]
usb: s3c-otg: Rename s3c_ep_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep_*() functions to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:59:12 +0000 (01:59 +0100)]
usb: s3c-otg: Rename s3c_ep0_*() functions
The driver is actually for the Designware DWC2 controller.
This patch renames the s3c_ep0_*() functions to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:56:30 +0000 (01:56 +0100)]
usb: s3c-otg: Staticize functions in s3c_udc_otg_xfer_dma.c
Just staticize the functions, they are not used outside of the file.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:52:03 +0000 (01:52 +0100)]
usb: s3c-otg: Staticize s3c_udc_ep_set_stall
This function is local to s3c_udc_otg_xfer_dma.c , staticize it.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:51:07 +0000 (01:51 +0100)]
usb: s3c-otg: Rename struct s3c_request
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_request to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:48:57 +0000 (01:48 +0100)]
usb: s3c-otg: Rename struct s3c_ep
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_ep to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:46:15 +0000 (01:46 +0100)]
usb: s3c-otg: Rename struct s3c_dev_*_ep
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_dev_*_ep to reflect this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:44:41 +0000 (01:44 +0100)]
usb: s3c-otg: Rename struct s3c_usbotg_phy to dwc2_usbotg_phy
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_phy to struct dwc2_usbotg_phy
to make things more obvious and clear.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:36:36 +0000 (01:36 +0100)]
usb: s3c-otg: Split private bits from s3c_udc.h
Most of the functions are local to the s3c_udc driver, remove them
from the s3c_udc.h header to stop those bits from propagating all
over the place. Instead, move all the private stuff into new private
s3c_udc_otg_priv.h header.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Fri, 4 Dec 2015 00:11:45 +0000 (01:11 +0100)]
usb: s3c-otg: Rename struct s3c_usbotg_reg to dwc2_usbotg_reg
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_usbotg_reg to struct dwc2_usbotg_reg
to make things more obvious and clear.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 3 Dec 2015 23:57:58 +0000 (00:57 +0100)]
usb: s3c-otg: Rename struct s3c_udc to dwc2_udc
The driver is actually for the Designware DWC2 controller.
This patch renames struct s3c_udc to struct dwc2_udc to make
things more obvious and clear.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 3 Dec 2015 23:54:16 +0000 (00:54 +0100)]
usb: s3c-otg: Rename regs-otg.h to s3c_udc_otg_regs.h
Rename the header file, so it's obvious which driver it's part of.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 17 Dec 2015 12:52:56 +0000 (07:52 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Shaohui Xie [Fri, 4 Dec 2015 02:22:03 +0000 (10:22 +0800)]
net: fm: disables unused FM1-DTSEC1 MAC node in DTS
We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since it is
used by MDIO. For FMAN v3, MDIO uses dedicated controller, so we
can disable unused FM1-DTSEC1 MAC node to avoid being probed in
Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
[York Sun: revised commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
Mingkai Hu [Mon, 7 Dec 2015 08:58:56 +0000 (16:58 +0800)]
armv8/ls1043aqds/rcw: change core frequency to 1600MHz
Change RCW for SD boot and NAND boot.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Mingkai Hu [Mon, 7 Dec 2015 08:58:55 +0000 (16:58 +0800)]
armv8/ls1043ardb/rcw: change core frequency to 1600MHz
Change RCW for SD boot and NAND boot.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Mingkai Hu [Mon, 7 Dec 2015 08:58:54 +0000 (16:58 +0800)]
armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>