Bin Meng [Fri, 12 Dec 2014 13:05:29 +0000 (21:05 +0800)]
x86: queensbay: Adapt FSP support codes
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 12 Dec 2014 13:05:28 +0000 (21:05 +0800)]
x86: Initial import from Intel FSP release for Queensbay platform
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 12 Dec 2014 13:05:27 +0000 (21:05 +0800)]
x86: ich-spi: Add Intel Tunnel Creek SPI controller support
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:26 +0000 (21:05 +0800)]
x86: Add Intel Topcliff PCH device IDs
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:25 +0000 (21:05 +0800)]
x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:24 +0000 (21:05 +0800)]
x86: Add Intel Crown Bay board dts file
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:23 +0000 (21:05 +0800)]
x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:22 +0000 (21:05 +0800)]
x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:21 +0000 (21:05 +0800)]
x86: Refactor u-boot.rom build rules
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 14 Dec 2014 05:25:46 +0000 (22:25 -0700)]
x86: ifdtool: Separate out filenames for -D and -i
To allow these options to be specified together, separate them out.
Change-Id: Ib93f11cd51eb3302127f4c82936ff2b44c88d5a2
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:20 +0000 (21:05 +0800)]
tools/ifdtool: Support writing multiple files (-w) simultaneously
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 13:05:19 +0000 (21:05 +0800)]
x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Dec 2014 14:06:16 +0000 (19:36 +0530)]
x86: ich-spi: Set the tx operation mode for ich 7
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Bin Meng [Fri, 12 Dec 2014 14:06:15 +0000 (19:36 +0530)]
x86: ich-spi: Set the rx operation mode for ich 7
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Jagannadha Sutradharudu Teki [Fri, 12 Dec 2014 14:06:14 +0000 (19:36 +0530)]
sf: Enable byte program support
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 12 Dec 2014 14:06:13 +0000 (19:36 +0530)]
spi: sf: Support byte program for sst spi flash
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Simon Glass [Fri, 12 Dec 2014 14:06:12 +0000 (19:36 +0530)]
spi: Fix flag collision for SST_WP
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Jagannadha Sutradharudu Teki [Fri, 12 Dec 2014 14:06:11 +0000 (19:36 +0530)]
sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 11 Dec 2014 03:12:01 +0000 (20:12 -0700)]
bios_emulator: Correct ordering of includes
We should include common.h before other includes. This actually causes
a build error on chromebook_link.
Signed-off-by: Simon Glass <sjg@chromium.org>
Axel Lin [Sun, 7 Dec 2014 04:48:27 +0000 (12:48 +0800)]
gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()
Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 10 Dec 2014 08:35:50 +0000 (16:35 +0800)]
x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().
Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 12 Dec 2014 01:47:34 +0000 (20:47 -0500)]
Merge git://git.denx.de/u-boot-dm
Tom Rini [Thu, 11 Dec 2014 23:40:49 +0000 (18:40 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
board/freescale/mx6sxsabresd/mx6sxsabresd.c
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Thu, 11 Dec 2014 23:28:09 +0000 (18:28 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Xiubo Li [Thu, 11 Dec 2014 19:15:26 +0000 (11:15 -0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i
Earlier commit
73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ.
It should be CONFIG_TIMER_CLK_FREQ.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
[York Sun: This is the difference between two patch versions]
Reviewed-by: York Sun <yorksun@freescale.com>
Simon Glass [Wed, 10 Dec 2014 15:55:57 +0000 (08:55 -0700)]
dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:
- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2C
This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1
It has not been tested on Tegra 114 as I don't have that board.
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Allen Martin [Thu, 4 Dec 2014 13:36:30 +0000 (06:36 -0700)]
ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.
The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
Simon Glass [Thu, 4 Dec 2014 13:36:29 +0000 (06:36 -0700)]
tegra: dts: Sync tegra124.dtsi with linux kernel
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Thu, 4 Dec 2014 13:36:28 +0000 (06:36 -0700)]
dts: Bring in Chrome OS keyboard device tree definition
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 10 Dec 2014 15:55:56 +0000 (08:55 -0700)]
dm: device: Add newline to debug() messages
Some of these are missing a newline. Add it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 10 Dec 2014 15:55:55 +0000 (08:55 -0700)]
dm: i2c: Add tests for I2C
Add some basic tests to check that the system works as expected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 10 Dec 2014 15:55:54 +0000 (08:55 -0700)]
dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Simon Glass [Wed, 10 Dec 2014 15:55:53 +0000 (08:55 -0700)]
dm: i2c: dts: Add an I2C bus for sandbox
Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Simon Glass [Wed, 10 Dec 2014 15:55:52 +0000 (08:55 -0700)]
dm: i2c: config: Enable I2C for sandbox using driver model
Enable the options to bring up I2C on sandbox. Also enable all the available
I2C commands for testing purposes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Simon Glass [Wed, 10 Dec 2014 15:55:51 +0000 (08:55 -0700)]
dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Simon Glass [Wed, 10 Dec 2014 15:55:50 +0000 (08:55 -0700)]
dm: i2c: Add a sandbox I2C driver
This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Simon Glass [Wed, 10 Dec 2014 15:55:49 +0000 (08:55 -0700)]
dm: i2c: Add I2C emulation driver for sandbox
In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Simon Glass [Wed, 10 Dec 2014 15:55:48 +0000 (08:55 -0700)]
dm: i2c: Implement driver model support in the i2c command
The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Simon Glass [Wed, 10 Dec 2014 15:55:47 +0000 (08:55 -0700)]
dm: i2c: Add a uclass for I2C
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:
- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Przemyslaw Marczak [Wed, 8 Oct 2014 20:48:37 +0000 (22:48 +0200)]
lib: errno: introduce errno_str(): returns errno related message
The functions error's numbers are standarized - but the error
messages are not.
The errors are often handled with unclear error messages,
so why not use an errno standarized messages.
Advantages:
- This could decrease the binary size.
- Appended with a detailed information,
the error message will be clear.
This commit introduces new function:
- const char *errno_to_str(int errno)
The functions returns a pointer to the errno corresponding text message:
- if errno is null or positive number - a pointer to "Success" message
- if errno is negative - a pointer to errno related message
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Tom Rini <trini@ti.com>
Simon Glass [Tue, 25 Nov 2014 04:36:34 +0000 (21:36 -0700)]
dm: rpi: Move serial to driver model
Adjust the configuration to use the driver model version of the pl01x
serial driver. Add the required platform data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Simon Glass [Tue, 25 Nov 2014 04:36:35 +0000 (21:36 -0700)]
dm: serial_pl01x: Add missing private data size
The private data size is missing from the driver, so we store it at 0,
which causes problems when something overwrites memory at 0.
Fix this.
Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Masahiro Yamada [Sat, 29 Nov 2014 08:01:56 +0000 (17:01 +0900)]
dm_test: improve the appearance shown by "dm tree" command
The command "dm tree" lists devices in a tree-like format.
This commit makes it look more like what the Unix command "tree"
shows.
=> dm tree
Class Probed Name
----------------------------------------
root [ + ] root_driver
demo [ ] |-- demo_shape_drv
demo [ ] |-- demo_simple_drv
demo [ ] |-- demo_shape_drv
demo [ ] |-- demo_simple_drv
demo [ ] |-- demo_shape_drv
test [ ] |-- test_drv
test [ ] |-- test_drv
test [ ] |-- test_drv
gpio [ ] |-- gpio_sandbox
serial [ ] |-- serial_sandbox
serial [ + ] |-- serial
demo [ ] |-- triangle
demo [ ] |-- square
demo [ ] |-- hexagon
gpio [ ] |-- gpios
spi [ ] |-- spi@0
spi_emul [ ] | `-- flash@0
cros_ec [ + ] `-- cros-ec@0
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Thu, 20 Nov 2014 12:20:32 +0000 (21:20 +0900)]
lib: string: move strlcpy() to a common place
Move strlcpy() definition from drivers/usb/gadget/ether.c to
lib/string.c because it is a very useful function.
Let's add the prototype to include/linux/string.h too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Alison Wang [Wed, 3 Dec 2014 08:18:09 +0000 (16:18 +0800)]
kconfig: ls102xa: Change the prompt messages
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Jaiprakash Singh [Thu, 27 Nov 2014 07:08:12 +0000 (12:38 +0530)]
driver/mtd: Fix IFC compilation warnings
'eccstat' array elements might be used uninitialized
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:59 +0000 (17:40 +0800)]
ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:58 +0000 (17:40 +0800)]
ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.
For now we configure all the peripheral access permissions as R/W.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:57 +0000 (17:40 +0800)]
ls102xa: changing a few targets' configurations.
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:56 +0000 (17:40 +0800)]
ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.
Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:55 +0000 (17:40 +0800)]
ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.
This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Xiubo Li [Fri, 21 Nov 2014 09:40:54 +0000 (17:40 +0800)]
ARM: HYP/non-sec: add the pen address BE mode support.
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.
This patch adds BE mode support for smp pen address.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Fri, 21 Nov 2014 03:17:15 +0000 (11:17 +0800)]
fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Thu, 30 Oct 2014 04:41:28 +0000 (10:11 +0530)]
drivers: usb: fsl: Check USB Erratum A007792 applicability
Check USB Erratum A007792 applicability. If applicable, add
corresponding property in the device tree via device tree fixup
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Tue, 30 Sep 2014 05:54:07 +0000 (11:24 +0530)]
drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Nikhil Badola [Mon, 20 Oct 2014 11:20:49 +0000 (16:50 +0530)]
drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Yao Yuan [Wed, 26 Nov 2014 06:54:33 +0000 (14:54 +0800)]
ls1021aqds: add hwconfig setting to do pin mux
The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.
The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:38:14 +0000 (17:38 +0800)]
arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:38:02 +0000 (17:38 +0800)]
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:37:49 +0000 (17:37 +0800)]
arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support
The SD/NAND/QSPI boot definations are wrong for QE support, this
patch is to fix this error.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 9 Dec 2014 09:37:34 +0000 (17:37 +0800)]
arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support
This patch will fix the bug that the partitions on the SD card could
not be accessed and add the support for the FAT fs.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:48 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021ATWR board
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:47 +0000 (15:00 +0800)]
arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:46 +0000 (15:00 +0800)]
ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:45 +0000 (15:00 +0800)]
kconfig: ls1021a: add SUPPORT_SPL
Add SUPPORT_SPL feature for SD and NAND boot on
LS1021AQDS and LS1021ATWR.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:43 +0000 (15:00 +0800)]
arm: spl: Add I2C linker list in generic .lds
On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:42 +0000 (15:00 +0800)]
spl: Use u-boot.img instead of u-boot.bin
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 3 Dec 2014 07:00:41 +0000 (15:00 +0800)]
ls102xa: pblimage: Add pblimage tool support for LS102xA
For LS102xA, the size of spl/u-boot-spl.bin is variable.
This patch adds the support to deal with the variable
u-boot size in pblimage tool. It will be padded to 64
byte boundary.
Use pblimage_check_params() to add the specific operations
for ARM, such as PBI CRC and END command and the calculation
of pbl_cmd_initaddr.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Chenhui Zhao [Thu, 6 Nov 2014 02:51:59 +0000 (10:51 +0800)]
ls1021aqds: set the default I2C channel before DDR init
When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Minghuan Lian [Fri, 31 Oct 2014 05:43:44 +0000 (13:43 +0800)]
arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
chenhui zhao [Wed, 22 Oct 2014 10:20:22 +0000 (18:20 +0800)]
arm: ls102xa: clear EPU registers for deep sleep
After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tang Yuantian [Tue, 21 Oct 2014 05:51:58 +0000 (13:51 +0800)]
arm: ls102xa: fixed a bus frequency setting error
The bus frequency in SOC node should be clock frequency of platform.
That is not true if it is devided by 2.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Tom Rini [Wed, 10 Dec 2014 14:07:25 +0000 (09:07 -0500)]
Merge branch 'master' of git://denx.de/git/u-boot-imx
Tom Rini [Wed, 10 Dec 2014 14:07:06 +0000 (09:07 -0500)]
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh
Nobuhiro Iwamatsu [Wed, 3 Dec 2014 06:30:30 +0000 (15:30 +0900)]
arm: rmobile: alt: Add support MMC and MMC command
Alt board has been connected to eMMC of 8GB to MMC port.
This enables MMC port and MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 3 Dec 2014 06:30:30 +0000 (15:30 +0900)]
arm: rmobile: lager: Add support MMC and MMC command
Lager board has been connected to eMMC of 8GB to MMC1 port.
This enables MMC1 port and MMC command.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 10 Dec 2014 01:46:04 +0000 (10:46 +0900)]
arm: rmobile: rcar: Add support ext2 and ext4 file system
Board with R-Car SoC has USB and MMC. They might use the EXT2 or EXT4 file system.
This adds support ext2 and ext4 file system
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsu [Wed, 10 Dec 2014 05:12:43 +0000 (14:12 +0900)]
arm: rmobile: Add mmc.h for sh_mmcif of rmobile
R-Mobile and R-Car ARM SoCs use sh_mmcif as MMC host driver.
This adds arch-rmobile/mmc.h that defines mmcif_mmc_init().
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Vikas Manocha [Mon, 1 Dec 2014 20:27:54 +0000 (12:27 -0800)]
dm: stv0991: Move serial to driver model
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Vikas Manocha [Mon, 1 Dec 2014 20:27:53 +0000 (12:27 -0800)]
stv0991: increase the initial ram size config
It is done to make space available for driver model memory.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Vikas Manocha [Tue, 18 Nov 2014 18:42:24 +0000 (10:42 -0800)]
stv0991: enable default and misc command configs
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Vikas Manocha [Tue, 18 Nov 2014 18:42:23 +0000 (10:42 -0800)]
stv0991: enable ethernet support
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Vikas Manocha [Tue, 18 Nov 2014 18:42:22 +0000 (10:42 -0800)]
stv0991: Add basic stv0991 architecture support
stv0991 architecture support added. It contains the support for
following blocks
- Timer
- uart
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Add arch/arm/cpu/armv7/Makefile hunk]
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 8 Dec 2014 21:33:13 +0000 (16:33 -0500)]
Prepare v2015.01-rc3
Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 8 Dec 2014 21:35:07 +0000 (16:35 -0500)]
Merge git://git.denx.de/u-boot-mpc85xx
Tom Rini [Mon, 8 Dec 2014 21:35:06 +0000 (16:35 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-ti
Tom Rini [Mon, 8 Dec 2014 21:35:05 +0000 (16:35 -0500)]
Merge git://git.denx.de/u-boot-i2c
Tom Rini [Mon, 8 Dec 2014 21:35:05 +0000 (16:35 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
Masahiro Yamada [Fri, 5 Dec 2014 15:03:26 +0000 (00:03 +0900)]
ARM: UniPhier: detect the number of flash banks at run-time
Some UniPhier boards are equipped with an expansion slot that
some optional SRAM/NOR-flash cards can be attached to. So, run-time
detection of the number of flash banks would be more user-friendly.
Until this commit, UniPhier boards have achieved this by (ab)using
board_flash_wp_on() because the boot failed if flash_size got zero.
Fortunately, this problem was solved by commit
70879a92561a (flash:
do not fail even if flash_size is zero).
Now it is possible to throw away such a tricky workaround. This
commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further
refactoring.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Fri, 5 Dec 2014 15:03:25 +0000 (00:03 +0900)]
ARM: UniPhier: extend register area of init page table for PH1-sLD3
0x20000000-0x2fffffff: assigned to ARM mpcore (sLD3 only)
0xf0000000-0xffffffff: assigned to Denali NAND controller (sLD3 only)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Fri, 5 Dec 2014 15:03:24 +0000 (00:03 +0900)]
ARM: UniPhier: add device tree sources for PH1-sLD3
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Fri, 5 Dec 2014 15:03:23 +0000 (00:03 +0900)]
ARM: UniPhier: add more device nodes to device tree
Add I2C controller and NAND controller devices. Fix indentation too.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tom Rini [Mon, 8 Dec 2014 14:36:26 +0000 (09:36 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Thu, 4 Dec 2014 16:27:08 +0000 (11:27 -0500)]
doc/gitmail-rc: Update m68k alias
Signed-off-by: Tom Rini <trini@ti.com>
Peter Kümmel [Sat, 29 Nov 2014 08:26:04 +0000 (17:26 +0900)]
kconfig: Fix warning "‘jump’ may be used uninitialized"
Warning:
In file included from scripts/kconfig/zconf.tab.c:2537:0:
scripts/kconfig/menu.c: In function ‘get_symbol_str’:
scripts/kconfig/menu.c:590:18: warning: ‘jump’ may be used uninitialized in this function [-Wmaybe-uninitialized]
jump->offset = strlen(r->s);
Simplifies the test logic because (head && local) means (jump != 0)
and makes GCC happy when checking if the jump pointer was initialized.
Signed-off-by: Peter Kümmel <syntheticpp@gmx.net>
Signed-off-by: Michal Marek <mmarek@suse.cz>
[ imported from Linux Kernel, commit
2d5603060967 ]
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Fri, 28 Nov 2014 02:13:28 +0000 (11:13 +0900)]
libfdt: move CONFIG_OF_LIBFDT and CONFIG_FIT to lib/Makefile
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Fri, 28 Nov 2014 02:13:27 +0000 (11:13 +0900)]
libfdt: descend from lib/ to lib/libfdt/
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Masahiro Yamada [Fri, 28 Nov 2014 02:13:26 +0000 (11:13 +0900)]
lib: bzip2: move bzip2 files to lib/bzip2/ directory
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suriyan Ramasami [Thu, 27 Nov 2014 21:24:16 +0000 (13:24 -0800)]
fdt: Allow non-FDT kernels to boot when CONFIG_OF_LIBFDT is defined
The boot commands - bootz/bootm mandate a third argument which is the
address to the FDT blob. In cases where this argument is not specified,
boot fails with a message indicating a missing FDT.
This causes non-FDT kernels to fail to boot. This patch allows both FDT
and non-FDT kernels to boot by making the third parameter to the bootm/bootz
optional.
Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
[trini: Update again for covering appended DTB case after last revert in
this area]
Signed-off-by: Tom Rini <trini@ti.com>
Masahiro Yamada [Wed, 26 Nov 2014 07:02:54 +0000 (16:02 +0900)]
blackfin: include <linux/compiler.h> rather than define __iomem
The macro __iomem is defined in include/linux/compiler.h.
Let's include it rather than double __iomem defines.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>