util: move ASTCLutHolder from mesa/main to util

v2: remove extra u_formats.h header addition (Chia-I Wu)
    use stddef.h and not unistd.h (Chia-I Wu)

Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24672>

mesa: make astc_decoder.glsl vk-compatible

glslangValidator -V -S comp astc_decoder.glsl

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24672>

ac/surface: add astc block size to bpe_to_format() function

v2: remove old comment (Chia-I Wu)
v3: add comment on matching BC3 and ASTC4x4 (Chia-I Wu)

Acked-by: : Chia-I Wu <olvaffe@gmail.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24672>

radeonsi/vcn: Add High Quality encoding preset for AV1

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25564>

frontends/va: Add High Quality preset mode

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25564>

ir3: Fix values of #wrmask not being compatible with ir3 parser

IR3 parser expects wrmask values to be in xyzw order.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25661>

spirv: Don't use libclc for rotate

We have a nir lowering for drivers that do not support urol.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25660>

radv/ci: update list of flakes for STONEY

These should have been fixed couple of weeks ago.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25656>

radv/ci: update list of flakes for VANGOGH

This one is already skipped in radv-skips.txt.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25656>

radv/ci: update list of expected failures on RAVEN

These have been fixed a while ago but I think only a subset of CTS
is used on RAVEN.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25656>

aco/tests: test that hazards are resolved at the end of shader parts

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374>

aco: resolve all possible hazards at the end of shader parts

fossil-db (vega10):
Totals from 1266 (2.01% of 63055) affected shaders:
Instrs: 707116 -> 708382 (+0.18%)
CodeSize: 3512452 -> 3517516 (+0.14%)
Latency: 6661724 -> 6666788 (+0.08%)
InvThroughput: 4393626 -> 4393904 (+0.01%); split: -0.00%, +0.01%

fossil-db (navi10):
Totals from 1305 (2.07% of 63015) affected shaders:
Instrs: 719699 -> 722009 (+0.32%)
CodeSize: 3650836 -> 3660076 (+0.25%)
Latency: 5691633 -> 5693933 (+0.04%)
InvThroughput: 1532010 -> 1532024 (+0.00%); split: -0.00%, +0.00%

fossil-db (navi31):
Totals from 1580 (1.99% of 79332) affected shaders:
Instrs: 1678242 -> 1679879 (+0.10%)
CodeSize: 8463464 -> 8470168 (+0.08%)
Latency: 14273661 -> 14275298 (+0.01%)
InvThroughput: 3668049 -> 3668080 (+0.00%); split: -0.00%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374>

aco: consider exec_hi in reads_exec()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374>

aco: fix s_setreg hazards

s_setreg doesn't have any definitions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374>

aco: only mitigate VcmpxExecWARHazard when necessary

fossil-db (navi10):
Totals from 5059 (8.03% of 63015) affected shaders:
Instrs: 7384947 -> 7351196 (-0.46%)
CodeSize: 39393180 -> 39299196 (-0.24%); split: -0.28%, +0.04%
Latency: 119683018 -> 119585224 (-0.08%); split: -0.08%, +0.00%
InvThroughput: 29647188 -> 29623895 (-0.08%); split: -0.08%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374>

aco: fix LdsDirectVMEMHazard WaW with the wrong waitcnt

Seems we missed this case.

fossil-db (navi31):
Totals from 24 (0.03% of 79332) affected shaders:
Instrs: 3562 -> 3538 (-0.67%)
CodeSize: 18740 -> 18644 (-0.51%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 2cdb3e4b6b6d ("aco: add VMEMtoScalarWriteHazard tests")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25374>

anv: enable FCV for Gen12.5

Now that we have proper handling of FCV_CCS_E everywhere, we can turn
this on for Gen12.5.

This helps fix a performance regression where enabling fast
clears to non-zero values with CCS_E caused additional partial resolves,
regressing performance on certain games. Performance is helped on the
following games:
  - F1'22: +45%
  - RDR2: +6%

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589>

anv: ensure that FCV_CCS_E fast clears are properly tracked

Surfaces with FCV_CCS_E aux usage should be marked as fast cleared when
being rendered to, to ensure proper fast clear state tracking. We also
need to ensure that we're not trying to partially resolve surfaces with
level > 0 and layer > 0 since we don't track fast clear states for
those.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589>

intel/genxml: fix 3DSTATE_3D_MODE length to align with BSpec

Closes: #8632
Fixes: 569afd37f15 ('intel/genxml: Copy gen12.xml to gen125.xml')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25589>

anv: add support for VK_EXT_nested_command_buffer

Our implementation of secondary command buffers already jumps into
them and edits the end of the secondary command buffer to jump back
into the primary.

That implementation can work just the same with any levels of
secondary. The only possible issue would happen with a secondary
calling itself, but that's not possible.

We also cannot support simultaneous execution with self-modifying
command buffers. That's actually not a problem at the moment because
we don't have multiple queues of the same family but we choose to
reflect that in the feature bits.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25600>

anv: rename primary in container in ExecuteCommands()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25600>

vulkan: bump headers/registry to 1.3.267

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25600>

Revert "ci/etnaviv: allow failure on failing test"

This reverts commit 2ac2268ce74c, as the issue causing the
test to fail has been resolved.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25646>

etnaviv: fix read staging buffer leak

Currently we only free a potentially allocated staging buffer
when the mapping is a write mapping, but staging buffers can
also be allocated for read mappings. Fix the read staging
buffer leaks by always freeing the staging buffer.

Closes #9967

Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25646>

pvr: Clean up & fix sampler border color support

Take advantage of some vk_sampler goodness and migrate all pvr
tex_formats to map to pipe_formats in pvr_formats.c. This allows us to
get rid of all the nasty manual packing functions.

This cleanup incidentally fixes some bad swizzling that was happening
in the manual handling.

Fixes: 4a2e6284 pvr: Add support for sampler border colors
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25270>

pvr: Use vk_sampler base

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25270>

pvr: Switch to common pipeline cache implementation

We don't currently make use of pipeline caching, but the common
implementation handles the boilerplate we had in pvr_pipeline_cache.c
for us.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25422>

tu: Disable preamble push consts when they are not used

It's a common case for Zink which has to declare push consts in
pipeline layout, even if they are not actually used in shaders, due
to the compatibility rules.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25641>

pvr: Fix PPP_SCREEN sizes

The `- 1` was accidentally removed.

Fixes: aae23fe68d16 ("pvr: HWRT creation simplifications.")
Reported-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Fix SPM load shader sample rate

Reported-by: James Glanville <james.glanville@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Refactor subpass ds and sample count setup

Now we first check the sample count from the ds attachment as well
as setting it up.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Fix subpass sample count on ds attachment only

When no color attachments were used in a subpass, the sample count
was left unchanged to `1` while we should instead have picked it
up from the ds attachment if there was one.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Order tile buffer EOT emits to be last

Tile buffer emits required a load from the tile buffer into the
output regs, so they must be placed at the end of the EOT program
as to not corrupt the output register emits.

This commit orders the emit state to place output register emits
first, and tile buffer emits last.

dEQP test fixed:
  dEQP-VK.renderpass.suballocation.attachment.4.422
  ... and others from the dEQP-VK.renderpass.suballocation.*

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Fix OOB access of pbe_{cs,reg}_words

`hw_render->eot_surface_count` also includes surface which don't
need an emit. Using `i` was leading to OOB access when there were
surfaces that didn't need emits, and in total there were
`> PVR_MAX_COLOR_ATTACHMENTS` surfaces.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Fix pbe_emit assert

The `eot_surface_count` also includes surfaces which don't need an
emit. Surfaces with PVR_RESOLVE_TYPE_TRANSFER don't need an emit
since they'll be resolved through a transfer op, but they still count
against the total, thus the assert was incorrect.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

pvr: Fix MRT index in PBE state

The same MRT index was incorrectly being set for all render
targets, in the PBE state.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25584>

nvk: Improve address space and buffer size limits

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nvk: Always emit at least one color attachment

Without this, alpha to coverage doesn't work because the hardware
ignores the output of the first color from the shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nvk: Disable depth or stencil tests when unbound

Dynamic rendering requires that the client be able to bind just one
aspect of a depth/stencil image.  Because we only have interleaved
depth/stencil on NVIDIA and no actual disable bits, this means we need
to implicitly AND any enables with a vk_format != UNDEFINED check.  In
future, we might want to do that with a macro but we'll keep it simple
for today.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nil/format: Advertise R10G10B10A2_UINT texture buffer support

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nil/format: Use A for alpha blend

This lets us reserve B for buffer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nvk: Reset descriptor pool allocator when all sets are destroyed

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nvk: Set max descriptors to 2^20 for most descriptor types

Dynamic is the exception here.  Those have much stricter limits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nvk: Emit MME_DMA_SYSMEMBAR before indirect draw/dispatch

This fixes issues where we may read stale data from other parts of the
GPU when we go to do an indirect draw fetch.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

nvk: Advertise more inline uniform block limits

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25653>

ci/b2c: use latest mesa-trigger image

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25643>

ci/b2c: move to the shiny new `gfx-ci/ci-tron` repo

We've successfully moved the repo to its new location now that the
project is ready for general use.

Update the config to use the new paths.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25643>

nir/load_libclc: fix libclc memory leak

Fixes: ef453f54394 ("spirv: Add a shared libclc loader")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25649>

radeonsi: disable disk cache when use aco

This is a temp fix. Currently we mix use llvm and aco to compile
shaders when AMD_DEBUG=useaco, but disk cache need function
identifier when creation, aco compiled shader should not use llvm
function identifier, so we have to disable disk cache when use
aco for now.

After aco is able to compile all shaders, we can re-enable disk
cache by removing the llvm function identifier when aco.

Fixes: d1dd36a74e1 ("radeonsi: be able to use aco compiler for mono ps")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9673
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25607>

lavapipe: don't block begin/end cmdbuf pipeline barriers

these are now useful

fixes #9972

Fixes: 3b547a9b581 ("lavapipe: Switch to the common sync framework")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25652>

zink: set ZINK_DEBUG=quiet for polaris jobs

modifiers aren't supported here, so this will otherwise spam infinitely

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25645>

zink: apply ZINK_DEBUG=quiet to all missing feature warnings

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25645>

lavapipe + docs: update ycbcr extension enables.

This passes all the dEQP-VK.ycbcr* tests and updates the docs.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25628>

rusticl/memory: fix potential use-after-free in clEnqueueSVMMemFill

Fixes: bfee3a8563d ("rusticl: add support for fine-grained system SVM")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reported-by: @LingMan <18294-LingMan@users.noreply.gitlab.freedesktop.org>
Reviewed-by: @LingMan <18294-LingMan@users.noreply.gitlab.freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25637>

pvr: emit PPP state when vis_test dirty bit is set

Unlike other dirty bits, the vis_test dirty bit wasn't being taken into
consideration when determining whether PPP state needed to be emitted as part
of a draw call.

Fixes a large number of tests in dEQP-VK.query_pool.occlusion_query.*.

Fixes: 2b1992a0005 ("pvr: Implement vkCmdBeginQuery API.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25491>

pvr: fix setup of load op unresolved msaa mask

Bits were being assigned rather than ORed into the mask during setup. Noticed
through code inspection.

Fixes: e089166776d ("pvr: Add support for VK_ATTACHMENT_LOAD_OP_LOAD.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25487>

pvr: change a few places to use PVR_DW_TO_BYTES()

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25489>

pvr: fix allocation size of clear colour consts shared regs buffer

The number of const shared registers was being used for the allocation size
rather than the number of bytes. In practice this doesn't make a difference as
the max allocation size is 24 bytes, which then gets rounded up to 64 bytes by
the buffer allocation function. However, we might as well make the allocation
size correct to avoid any future confusion. Noticed through code inspection.

Fixes: 7509e259f85 ("pvr: Implement color/depth/depth+stencil attachment clear.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25489>

pvr: fix attachments segfault in pvr_is_stencil_store_load_needed()

pvr_is_stencil_store_load_needed() may be called on secondary command buffers,
which don't have any attachments. This wasn't being taken into account, meaning
a segfault could occur.

Fixes a segfault seen in:
dEQP-VK.renderpass.suballocation.attachment_allocation.input_output.39

Fixes: 54876512a14 ("pvr: Add mid fragment pipeline barrier if needed.")
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25486>

zink/ci: remove 42 tests from the zink-radv-polaris10-fails list

Not sure which MR fixed them, but I'll take these fixes!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25629>

dri: Remove __driDriverExtensions leftovers

Android-14/clang-17 throws an error with it:

ld.lld: error: version script assignment of 'global' to symbol
   '__driDriverExtensions' failed: symbol not defined

Fixes: d43e6a9a497f ("dri: Remove the megadriver compat stub")
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25587>

zink: fix wording of warning

The string-argument for this function is the name of the feature, not
the entire message.

Fixes: ea0e22da442 ("zink: use warn_missing_feature for missing modifier support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25644>

ac/nir: only consider overflow for valid feedback buffers

Otherwise the ordered operation above (ie. a GDS atomic return) might
return non-zero offsets for invalid buffers.

Fixes: f7076d129db ("amd: add nir_intrinsic_xfb_counter_sub_amd and fix overflowed streamout offsets")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25613>

radv: allocate only 1 GDS OA counter for gfx10 NGG streamout

It works with just one counter.

This mitigates https://gitlab.freedesktop.org/drm/amd/-/issues/2902
quite a lot when you run dEQP-VK.transform_feedback.* in parallel on
more than 16 threads with RDNA3.

For example, on my GPU the kernel reports 16 GDS OA counters which means
that if you run VKCTS with 16 threads (ie. 16 Vulkan devices are
created) it's fine. Otherwise, the kernel might report ENOMEM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25619>

radv: fix destroying GDS/OA BOs

Otherwise, we have dangling BO pointers in the global BO list. Not
quite sure why this hasn't been triggered before.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25623>

freedreno/ci: Minetest

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

nir/opt_preamble: Respect ACCESS_CAN_SPECULATE

In general, it is unsafe to speculatively hoist conditionally executed loads
into the preamble. For example, if the shader does:

   if (ptr is valid) {
      foo(*ptr)
   }

we cannot dereference ptr in the preamble without knowing that the pointer is
valid (which may not be determinable, since it might not be uniform).
nir_opt_preamble needs to stop speculating in this case, or otherwise using
preambles can cause faults on legal shaders.

However, some platforms may be able to speculate loads safely. For example,
Apple hardware is able to suppress MMU faults, making speculation safe.  This is
controlled global register to control this behaviour, set at boot-time by the
kernel.  (macOS suppresses these faults unconditionally, this feature may be
used in their implementation of sparse textures. Currently Linux does not
suppress any faults but this may change later.)

Since nir_opt_preamble should work soundly and optimally on a variety of
platforms, we need to respect the ACCESS flag.

Thanks to the if-else hoisting implemented earlier in the series, this isn't too
terrible of a band-aid on Asahi:

    total instructions in shared programs: 1499674 -> 1507699 (0.54%)
    instructions in affected programs: 78865 -> 86890 (10.18%)
    helped: 0
    HURT: 337
    Instructions are HURT.

    total bytes in shared programs: 10238284 -> 10279308 (0.40%)
    bytes in affected programs: 554504 -> 595528 (7.40%)
    helped: 3
    HURT: 334
    Bytes are HURT.

    total halfregs in shared programs: 452049 -> 454015 (0.43%)
    halfregs in affected programs: 7569 -> 9535 (25.97%)
    helped: 7
    HURT: 150
    Halfregs are HURT.

There are no shader-db changes on ir3 as expected, since ir3 can safely
speculate all instructions in my shader-db.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

nir/opt_preamble: Move phis for movable if's

Add infrastructure to reconstruct if's. Later in the series, this will let us
hoist loads from inside uniform if's without speculating. For now, it lets us
handle phi's in nir_opt_preamble in a straightforward way.

Results on AGX are good:

   total instructions in shared programs: 1504730 -> 1499674 (-0.34%)
   instructions in affected programs: 153673 -> 148617 (-3.29%)
   helped: 496
   HURT: 0
   Instructions are helped.

   total bytes in shared programs: 10287768 -> 10238284 (-0.48%)
   bytes in affected programs: 1113724 -> 1064240 (-4.44%)
   helped: 496
   HURT: 0
   Bytes are helped.

   total halfregs in shared programs: 452669 -> 452049 (-0.14%)
   halfregs in affected programs: 14825 -> 14205 (-4.18%)
   helped: 152
   HURT: 99
   Halfregs are helped.

   total threads in shared programs: 16469504 -> 16470784 (<.01%)
   threads in affected programs: 8960 -> 10240 (14.29%)
   helped: 10
   HURT: 0
   Threads are helped.

Results on ir3 is a bit more of a wash but still should be a win overall: The
regression in moves seems scary, but the cost model already accounts for them as
evidenced by instruction count coming out ahead.

   total instructions in shared programs: 3108750 -> 3105993 (-0.09%)
   instructions in affected programs: 317367 -> 314610 (-0.87%)
   helped: 675
   HURT: 242
   Instructions are helped.

   total nops in shared programs: 673152 -> 675048 (0.28%)
   nops in affected programs: 74551 -> 76447 (2.54%)
   helped: 353
   HURT: 347
   Inconclusive result (%-change mean confidence interval includes 0).

   total non-nops in shared programs: 2435598 -> 2430945 (-0.19%)
   non-nops in affected programs: 232664 -> 228011 (-2.00%)
   helped: 816
   HURT: 38
   Non-nops are helped.

   total mov in shared programs: 78201 -> 84011 (7.43%)
   mov in affected programs: 10726 -> 16536 (54.17%)
   helped: 60
   HURT: 781
   Mov are HURT.

   total cov in shared programs: 74964 -> 74906 (-0.08%)
   cov in affected programs: 273 -> 215 (-21.25%)
   helped: 17
   HURT: 0
   Cov are helped.

   total dwords in shared programs: 6716814 -> 6748726 (0.48%)
   dwords in affected programs: 879778 -> 911690 (3.63%)
   helped: 12
   HURT: 948
   Dwords are HURT.

   total full in shared programs: 193210 -> 193212 (<.01%)
   full in affected programs: 278 -> 280 (0.72%)
   helped: 12
   HURT: 22
   Inconclusive result (value mean confidence interval includes 0).

   total constlen in shared programs: 493632 -> 494816 (0.24%)
   constlen in affected programs: 19904 -> 21088 (5.95%)
   helped: 9
   HURT: 306
   Constlen are HURT.

   total cat0 in shared programs: 742476 -> 745046 (0.35%)
   cat0 in affected programs: 84455 -> 87025 (3.04%)
   helped: 277
   HURT: 489
   Cat0 are HURT.

   total cat1 in shared programs: 153303 -> 159059 (3.75%)
   cat1 in affected programs: 17810 -> 23566 (32.32%)
   helped: 69
   HURT: 780
   Cat1 are HURT.

   total cat2 in shared programs: 1144508 -> 1140731 (-0.33%)
   cat2 in affected programs: 121284 -> 117507 (-3.11%)
   helped: 841
   HURT: 0
   Cat2 are helped.

   total cat3 in shared programs: 942098 -> 934804 (-0.77%)
   cat3 in affected programs: 87140 -> 79846 (-8.37%)
   helped: 855
   HURT: 1
   Cat3 are helped.

   total cat4 in shared programs: 65261 -> 65249 (-0.02%)
   cat4 in affected programs: 42 -> 30 (-28.57%)
   helped: 12
   HURT: 0
   Cat4 are helped.

   total sstall in shared programs: 237311 -> 241281 (1.67%)
   sstall in affected programs: 33755 -> 37725 (11.76%)
   helped: 179
   HURT: 493
   Sstall are HURT.

   total (ss) in shared programs: 58166 -> 58795 (1.08%)
   (ss) in affected programs: 4535 -> 5164 (13.87%)
   helped: 35
   HURT: 664
   (ss) are HURT.

   total systall in shared programs: 503784 -> 503805 (<.01%)
   systall in affected programs: 3170 -> 3191 (0.66%)
   helped: 16
   HURT: 13
   Inconclusive result (value mean confidence interval includes 0).

   total (sy) in shared programs: 27261 -> 27259 (<.01%)
   (sy) in affected programs: 76 -> 74 (-2.63%)
   helped: 8
   HURT: 5
   Inconclusive result (value mean confidence interval includes 0).

   total waves in shared programs: 439848 -> 439872 (<.01%)
   waves in affected programs: 160 -> 184 (15.00%)
   helped: 12
   HURT: 0
   Waves are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

nir/opt_preamble: Unify foreach_use logic

Deduplication in prep for reconstructing if's.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

nir/opt_preamble: Preserve IR when replacing phis

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

nir/opt_preamble: Walk cf_list manually

The way backends walk NIR when translating. This will make it easy to filter
can_move based on the parent control flow.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

ir3: Model cost of phi nodes for opt_preamble

It can be beneficial to move phi nodes, even though they can often be coalesced.
Model this cost so nir_opt_preamble can make good decisions about hoisting phi
nodes (and by extension, if-statements) into the preamble.

At this point in the series, this has no effect, but it will avoid certain
shader-db regressions associated with the nir_opt_preamble changes later in the
series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

ir3: Set CAN_SPECULATE before opt_preamble

Speculating these loads is safe, but nir_opt_preamble doesn't know that. Set the
ACCESS bits appropriately to let it know.

This will avoid any code gen regression from the nir_opt_preamble change.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

nir: Add ACCESS_CAN_SPECULATE

Determining whether it is safe to hoist a load instruction out of control flow
depends on complex hardware and driver details. Rather than encoding this as
knobs in every NIR pass that wants to do so (notably nir_opt_preamble and
nir_opt_peephole_select), add a per-load ACCESS flag for backends to set.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24011>

docs/vulkan: fixup some typos

The type is called vk_object_base, not vk_vk_objet_base... This should
fix the cross-referencing of this type.

Fixes: f6d4641433e ("vulkan,docs: Document vk_instance")
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25634>

ci/traces: rename upload function to reflect it works with S3

Cosmetic change.

Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>

ci/traces: keep images for every job except the performance testing

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8354

Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>

ci/traces: upload only missing trace images

Right now, S3 always returns something, so we need to check
the content-type .

Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25606>

zink: use warn_missing_feature for missing modifier support

To avoid spamming VKCTS output.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25636>

ci/etnaviv: allow failure on failing test

This test has been failing every nightly pipeline on the CI for a long,
long time. It seems nobody is currently interested in fixing it, so
let's just allow the failure for now.

See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9967

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25635>

ci/etnaviv: update ci expectation

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25635>

tu: Zero init tu_render_pass and tu_subpass for dynamic rendering

The way we init render pass related structures is dangerous with when
structs are not zero initialized - too easy to miss a field. There
were already at least two issues with it.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25592>

tu: Fix stale tu_render_pass_attachment::store_stencil with dyn rendering

Attachment initialization helpers expect zeroed memory by default.

Fixes a hang when running Subnautica with TU_DEBUG="gmem".
See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8702#note_1932003

Fixes: ed125e6cca188275631641784fcf3ddcbcfef193
("tu: Initial support for dynamic rendering")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25592>

nir: Use a tagged pointer for nir_src parents

This allows us to pack the is_if boolean into the bottom bit of the parent
pointer, eliminating the boolean and hence shrinking the nir_src by 8 bytes (due
to the extra 63 bits of padding incurred in the old layout).

Because all access is forced through helpers now, this is a local change.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>

nir: Assert the nir_src union is used safely

It is undefined behaviour in C to read a different member of a union than was
written. Nothing in-tree should be using this behaviour with the nir_src union:
nir_if should never be read as nir_instr and vice versa. Assert this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>

nir: Use getters for nir_src::parent_*

First, we need to give the parent_instr field a unique name to be able to
replace with a helper.  We have parent_instr fields for both nir_src and
nir_def, so let's rename nir_src::parent_instr in preparation for rework.

This was done with a combination of sed and manual fix-ups.

Then we use semantic patches plus manual fixups:

    @@
    expression s;
    @@

    -s->renamed_parent_instr
    +nir_src_parent_instr(s)

    @@
    expression s;
    @@

    -s.renamed_parent_instr
    +nir_src_parent_instr(&s)

    @@
    expression s;
    @@

    -s->parent_if
    +nir_src_parent_if(s)

    @@
    expression s;
    @@

    -s.renamed_parent_if
    +nir_src_parent_if(&s)

    @@
    expression s;
    @@

    -s->is_if
    +nir_src_is_if(s)

    @@
    expression s;
    @@

    -s.is_if
    +nir_src_is_if(&s)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>

nir: Use set_parent_instr internally

This properly clears is_if.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>

nir: Add trivial nir_src_* getters

These will become nontrivial later in the series. For now these have no smarts
in them, in order to make the conversion completely mechanical.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>

lima/pp: Do not use union undefined behaviour

It is invalid to read parent_instr for an if-use (or parent_if for a
non-if-use). Make sure we read the right one when handling if-uses.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24671>

radv: fix IB alignment

This re-introduces "radv: fix alignment of DGC command buffers" and
"radv/amdgpu: fix alignment of command buffers" which were valid
changes.

IBs need to be aligned to the IB size requirement, not the number of
padded NOPs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25588>

lavapipe: expose planar ycbcr formats and new ycbcr features

This enables some extensions and a bunch of formats for ycbcr
support.

dEQP-VK.api.info.format_properties.g8_b8_r8_3plane_420_unorm,Fail
dEQP-VK.api.info.format_properties.g8_b8r8_2plane_420_unorm,Fail

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: handle planes in texture lowering.

This uses the descriptor set info to lower the texture/sampler
handlers properly using the stride.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: add descriptor sets bindings for planar images

This adds strided descriptor bindings that are used to handle
planar image/samplers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: handle planes in get image sub resource

image sub resources need to take planes into account in the calculations.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: handle planes in copies

This adds plane support to the various copy paths.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: allocate image and image view planes.

This allocate planes and handles disjoint.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: start introducing planes structure.

this just introduces a single plane and refactors code to use it.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: cleanup copy code to use a local region variable.

This should make no functional difference, except cleanup the code.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

lavapipe: convert sampler to use vk base class.

This just makes things a bit cleaner, and reuses the common code.

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>

llvmpipe: don't support planar formats for buffers.

This stops lavapipe exposing incorrect support.

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25609>